JPH01211138A - Resetting circuit for supervising circuit of computer system - Google Patents

Abstract

PURPOSE:To confirm the travelling normality of a microprogram on a main storage in a computer system by periodically resetting in the manner of software a watch dog timer in a watch dog system supervising circuit at the period shorter than a time-out and preventing the time-out of the dog timer. CONSTITUTION:During the on-line action, a microprogram muPROG as control data is outputted and impressed to a control memory instruction register 42 and a parity checking circuit 51. At the time of the parity error, an error is outputted from the circuit 51, this is checked with an FF52, the output from here is given to a delay circuit 53 and the watch dog timer of a supervising circuit 6 is resetted through an OR gate 56. The output of the FF 52 is given to a differentiating circuit 54a composed of a circuit 54 and an AND gate 55 and a differentiating signal S55 is outputted. Thereafter, the output is inputted to a selector 34, the output from here is selected by a selector 35, an initial address and a micro-address muADDE are outputted from counters 32 and 36 and a system is supervised.

Description

[Detailed Description of the Invention] [Summary] Regarding a reset circuit of a watchdog type monitoring circuit of a computer system, to substantially prevent the watchdog timer of the monitoring circuit from operating when a program is transferred from an external memory to an internal memory. It has a watchdog type monitoring circuit, a microprogram memory, and an external memory that stores the microprogram to be transferred to the microprogram memory, and is restarted at startup or by a failure detection circuit that detects a defect in the microprogram memory. In a computer system configured to occasionally transfer a microprogram from an external memory to a microprogram memory, the watchdog type monitoring is performed during a period of microprogram transfer from the external memory to the microprogram memory by the failure detection circuit at the time of restart. Configure the circuit to reset the watchdog timer.

[Industrial application field]

The present invention relates to a computer system configured to transfer a microprogram from an external memory to a microprogram memory at startup or restart, and then cause a program in main memory to perform a predetermined operation, and particularly relates to such a computer system. The present invention relates to a reset circuit for a watchdog type monitoring circuit of a computer system which substantially prevents the operation of a watchdog timer of the watchdog type monitoring circuit during a microprogram transfer period.

A watchdog type monitoring circuit is used to check the normality of running microprograms on the main memory in a computer system. That is, the watchdog timer in the automatic monitoring circuit is periodically reset by software at a cycle shorter than the expiration of the watchdog timer, for example, 100 m5ec, thereby preventing the watchdog timer from expiring. If some kind of failure occurs that prevents the watchdog timer from being reset periodically, such as a program stall, the watchdog timer expires, generates an interrupt, and reports an abnormality in program execution.

On the other hand, in addition to the high-speed volatile microprogram memory used for online processing, computer systems used in automatic switchboards and the like use microprograms operated by microprogram memory, or EPROMs in which microprograms are stored.

An external memory using ROM such as PROM is provided. There are various reasons for using external memory, some of which are described below. The first reason is that if the microprogram in the microprogram memory is destroyed when the power is cut off or a system failure occurs, the microprogram in the external memory is reloaded to restore the system. The second reason is that when a change occurs in the processing content of the automatic exchange system, the changed processing content is debugged in advance on another computer system and the ROM is replaced. Furthermore, it is possible to configure the same hardware configuration with different instruction specifications, improving flexibility in use. For example, the same hardware configuration can be used as either a telephone exchange or a bucket exchange.

[Conventional technology]

FIG. 8 shows a reset circuit for a monitoring circuit of a conventional computer system.

The operation of the circuit shown in FIG. 8 will be briefly described.

At initial startup, the counters 32 and 36 in the load circuit 3 are cleared, the selector 34 selectively outputs the output of the counter 32, and the selector 35 selectively outputs the output of the selector 34. Therefore, the count value of the counter 32 and the microaddress μADDC are applied to the control memory 1a as a microprogram memory. On the other hand, the external ROM 2a as an external memory has a counter 3.
Micro address μADD□ is applied from 6 onwards. As a result, the microprogram data μDATA of μADDE is output from the external ROM 2a to the control memory 1a. A write enable signal WE is applied from the NAND gate 37 to the control memory 1a, and μDATA from the external ROM 2a is stored at the address of μADDC.

Thereafter, each time the clock CLK is updated, the micro addresses μADDC and μADDE are updated, and the external 5R
Continue until all of the microprograms in OM 2a have been transferred to control memory 1a.

After the program transfer is completed, the selector 34 is switched to the vector address generation circuit 33 side, and the process starts from address A0. After that, the selector 35 selects the decoder section 4
The control memory instruction register (CMIR) 42 in the control memory instruction register (CMIR) 42 is switched to the output side. This will start the online process.

During online processing, the C
MII? A watchdog timer reset command applied to the decoder 41 via the decoder 42 is outputted as a clear signal CLRO to the watchdog timer built-in monitoring circuit 6 via the decoder 41 to reset the watchdog timer. The watchdog timer reset operation command is programmed in advance to be output according to a command programmed in the main memory so as to be repeated at a cycle shorter than the timer expiration time of the watchdog timer.

If a parity error occurs in the control memory 1a during online operation, the parity check circuit 51 in the failure detection circuit 5' detects it. Parity error detection is J-
is stored in the flip-flop 52, and the delay circuit 54
The counters 32 and 36 are reset by the output from the differentiating circuit 54a consisting of the AND gate 55. The output of the 1τ delay circuit 53, which is further delayed by the clock CLKI pulse, is applied to the selector 35, selects the output of the selector 34, enables the NAND gate 37, and enables the AND gate 31. As a result, after a parity error is detected, the external ROM is
The microprogram is automatically retransferred from control memory 2a to control memory 1a.

After the automatic transfer ends, the process shifts to online processing again.

As for automatic retransfer of the microprogram, it is conceivable to perform automatic retransfer of only the address where a parity error has occurred. However, retransferring only that address requires a complicated control circuit, and if a parity error is detected at one location, parity errors are likely to occur at multiple other addresses as well. In the example above, automatic retransmission is performed when a parity error is detected, but automatic retransmission may be performed due to other failures.
All microprograms in the external ROM are transferred to the control memory at once.

[Problem to be solved by the invention]

The watchdog timer in the monitoring circuit 6 is reset by the clear signal CLRO1 via the decoder 41, that is, by software, except that it is reset by hardware when all the circuits are initialized by hardware when the power is turned on. only. This is because the watchdog timer is originally used to check the normality of software running.

Therefore, the watchdog timer continues to operate even when the microprogram is retransferred. However, since no microprogram instructions are decoded by the decoder 41 when the microprogram is retransferred, the watchdog timer may run out when the microprogram is retransferred.

When the watchdog timer expires, an interrupt is generated and the process shifts to failure recovery processing. However, even if the normal routine is resumed after the failure recovery process is completed, the microprogram is not completely retransferred and there is a high possibility that it will be detected as a failure again. Further, if the failure recovery processing routine is destroyed and is not reloaded before proceeding to the failure recovery processing, it will similarly become a failure.

In such a case, there is no hardware recovery means, so the computer system becomes stuck.

Therefore, when retransferring a program after a failure occurs, it is desired that the watchdog timer be substantially not operated in terms of hardware to prevent the above-mentioned problem from occurring.

[Means to solve the problem]

FIG. 1 shows a principle block diagram of a reset circuit for a watchdog timer type monitoring circuit of a computer system according to the present invention.

The computer system includes a microprogram memory l for online processing, a decoder unit 4. It has a watchdog type monitoring circuit 6 and a failure detection/reset circuit 5 for detecting a failure in a microprogram memory or other computer circuit, for example, an arithmetic control unit.

Furthermore, the computer system transfers the microprogram to the external memory 2 which stores the microprogram to be transferred to the microprogram memory 1 at the time of initial startup or restart, and transfers the microprogram in the external memory 2 at the time of initial startup or restart. It has a load circuit 3 that controls data transfer to the microprogram memory 1.

The watchdog timer of the monitoring circuit 6 is configured not only to be reset by software by the clear signal CLRO from the decoder section 4 but also by hardware to be reset by the clear signal CLRI from the fault detection/reset circuit 5. .

[For production]

When the failure detection/reset circuit 5 detects a failure and starts retransfer of the program, it outputs a clear signal CLRI and resets the watchdog timer of the monitoring circuit 6 in a controlled manner. As a result, even if the watchdog timer is about to expire, the watchdog timer will not expire for a certain period of time until the next timeout.

Further, if the program retransfer time takes longer than the original watchdog timer time, the failure detection/reset circuit 5 makes the watchdog timer longer than the original time until the microprogram transfer is completed.

As a result of the above, the watchdog timer does not expire during the program retransfer period.

〔Example〕

A first embodiment of the present invention will be described with reference to FIG.

FIG. 2 shows an embodiment corresponding to the conventional reset circuit for a monitoring circuit shown in FIG.
The microprogram code stored in 2a is used as microprogram data μDATA, and tlJ? as microprogram memory 1 is used. The data is transferred to the wholesale memory 1a at the time of initial startup or restart. I
li wholesale mememory 1a static RAM, external ROM
2a is composed of a replaceable FROM. The load circuit 3, decoder section 4, and watchdog type monitoring circuit 6 themselves are the same as conventional ones.

In FIG. 2, the failure detection/reset circuit 5a includes a parity check circuit 51 for detecting a parity error in the control memory 1a, a JK flip-flop 52.1 clock frequency (lτ) delay circuit 53, a delay circuit 54, and an AND It has a differentiating circuit 54a consisting of a gate 55. This circuit configuration itself is similar to that shown in FIG. However, in FIG. 2, an OR gate 56 extracts a clear signal CLRI from the Q output of the flip-flop 52, and further combines this clear signal CLRI and a software rear signal CLRO from the decoder 41 to reset the ORL watchdog timer. is provided.

The restart operation in FIG. 2 will be described with reference to FIGS. 3(a) to (n).

During online operation, at time t1, control memory 1a
The microprogram μPROG is output as data (FIG. 3(b)). This μPROG is applied to a control memory instruction register (CMIR) 42 and a parity check circuit 51. If there is a parity error,
The parity check circuit 51 outputs an error output (FIG. 3(d)). At the next time L2, flip-flop 5
2 responds to the application of the clock CLK (FIG. 3(a)) and latches the parity check error state (FIG. 3(a)).
e)). The Q output of flip-flop 53 has a 1τ delay.
It is output to the circuit 53, and at the next time t3, the delay
The output S53 of the circuit 53 is turned on (FIG. 3(f)).

The Q output of the flip-flop 53 resets the watchdog timer of the monitoring circuit 6 via the OR gate 56 as a clear signal CLRI at time t2. As a result, the watchdog timer does not run out for a certain period of time. Further, by applying the Q output of the flip-flop 52 to a differentiating circuit 54a consisting of a delay circuit 54 and an AND gate 55, a differentiated signal S55 is output (third
Figure (g)).

Due to the differential signal S55, at time t2, the counter 3
2 and 36 are cleared. Output S36 of counter 36
, the selector 34 selects the output of the counter 32, and N
Enable AND gate 37. At the next time t3, the 1τ delay signal S53 enables the NAND gate 37, causing the selector 35 to select the output from the selector 34. When clock CLK rises, AND
A counter sidewalk pulse S31 is output from the gate 31,
The initial address a from the counters 32 and 36 is applied to the control memory 1a and the external memory 2a as micro addresses μADD and μADDE (FIG. 3(i)). As a result, the microprogram data μDATA at address a of the external memory 2a is outputted and inputted to the control memory 1a (FIG. 3(j)). When the clock CLK falls, the write enable signal WE rises, and the external memory 2
Microprogram data μDATA from a is stored at address a of control memory 1a.

Thereafter, in response to the clock CLK, the external memory 2a is
The microprogram data μDATA is continuously transferred from the control memory la to the control memory la. During this period, CMI
Address μADD from R62 is not applied to control memory la (FIG. 3(m)).

When the transfer of the microprogram data to addresses a-b is completed, the counter 36 overflows and its output S36 disables the NANO gate 37, resets the flip-flop 52, and selector 34 outputs the counter 32. The output of the vector address generation circuit 33 is selected from the output of the vector address generation circuit 33.

At this point, as shown in FIG. 4, all programs are reloaded into the control memory 1a from the external memory 2a, a microprogram start processing command is placed at address A0, and a parity error processing microprogram is sent from address AI to the control memory (CM). Suppose that is loaded.

In this case, the vector address generation circuit 33
Outputs 0. As a result, after the transfer is completed, address A0
The microprogram is output from the control memory 1a,
This is processed via the decoder 41. After that, it jumps to address A1.

At time 7.1, the output of the lτ delay circuit 53 turns off (FIG. 3(f)). Selector 35 is CMI
The address from R42 will be selected.

Therefore, CM parity error processing for addresses A1 and subsequent addresses is performed as normal processing (FIG. 4), and then normal online processing begins.

A reset circuit according to a second embodiment of the present invention is shown in FIG.

The reset/node circuit shown in FIG. 5 is configured to reset the watchdog timer using the differential signal S55 of the differential circuit 54a. Further, as shown in FIG. 7, before address Al-1, that is, CM parity error processing, an instruction to clear the watchdog timer is stored in the external ROM 2.
a and control memory 1a.

Therefore, as shown in FIGS. 6(a) to (n), time t2
At time t, the watchdog timer is reset by the clear signal CLRI, which is the same as the differential signal S53. +l software clear signal C
The watchdog timer is reset by LRO.

In the first embodiment, the watchdog timer is reset only at the start of microprogram transfer. In this case, the watchdog timer is about to run out after the transfer ends, and the timer runs out before the normal program's watchdog timer reset process is performed (especially when the amount of transfer is large). for). The second embodiment solves this problem by resetting the watchdog timer by software after the transfer is completed.

In any case, if the microprogram transfer time is longer than the watchdog timer, a monostable multipipe rake is added to the rear stage of the differentiating circuit 54a with a cycle shorter than the watchdog timer. etc., and periodically clear the clear signal CLR.
I can be output to prevent the watchdog timer from running out during the transfer.

Although the case where a parity error is detected and retransfer is performed has been exemplified above, the same applies to other failures.

Furthermore, the program to be retransferred is not limited to microprograms, but may also include data or regular programs.

[Effects of the Invention] - As described above, according to the present invention, with a simple circuit configuration,
A supervisory circuit reset circuit can be provided that substantially stops the watchdog timer during the program transfer period.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a reset circuit for a monitoring circuit in a computer system of the present invention, FIG. 2 is a reset circuit diagram for a monitoring circuit in an embodiment of the present invention, and FIGS. Figure 4 is a configuration diagram showing the process of Figure 2; Figure 5 is a reset circuit diagram for a monitoring circuit according to another embodiment of the present invention; Figures 6 (a) to (n). ) is an operation timing diagram of the reset circuit in FIG. 5, FIG. 7 is a form diagram showing the process of FIG. 5, and FIG. 8 is a diagram of a conventional reset circuit for a monitoring circuit. (Explanation of symbols) 1... Micro program memory, la... Control memory, 2... External memory, 2
a...External ROM, 3...Load circuit, 4.
... Decoder section, 5... Failure detection/reset circuit, 6... Watchdog type monitoring circuit, 32... Counter, 33... Vector address generation circuit, 34, 35...
...Selector, 36...Counter, 41...
Decoder, 42... Control memory instruction register, 51... Parity check circuit, 53, 54... Delay circuit.

Claims (2)

[Claims] 1. It has a watchdog type monitoring circuit, a microprogram memory, and an external memory that stores the microprogram to be transferred to the microprogram memory. In a computer system configured to transfer a microprogram to a microprogram memory, during a period of transfer of a microprogram from the external memory to the microprogram memory by the failure detection circuit at the time of restart, the watchdog of the watchdog type monitoring circuit is activated. A supervisory circuit reset circuit for a computer system, characterized in that the circuit is configured to reset a timer. 2. 2. The supervisory circuit reset circuit according to claim 1, wherein the failure detection circuit extends the period of a watchdog timer used to confirm the normal operation of the microprogram when restarting.