JPS59119453A - Cpu run-away monitoring circuit - Google Patents

Cpu run-away monitoring circuit

Info

Publication number
JPS59119453A
JPS59119453A JP57226612A JP22661282A JPS59119453A JP S59119453 A JPS59119453 A JP S59119453A JP 57226612 A JP57226612 A JP 57226612A JP 22661282 A JP22661282 A JP 22661282A JP S59119453 A JPS59119453 A JP S59119453A
Authority
JP
Japan
Prior art keywords
circuit
cpu
abnormal signal
output
wdt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57226612A
Other languages
Japanese (ja)
Other versions
JPH0218503B2 (en
Inventor
Hidenori Hayashi
秀紀 林
Satoru Tsushima
悟 津島
Noriyuki Suzuki
紀之 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57226612A priority Critical patent/JPS59119453A/en
Publication of JPS59119453A publication Critical patent/JPS59119453A/en
Publication of JPH0218503B2 publication Critical patent/JPH0218503B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

PURPOSE:To prevent the malfunction of a CPU run-away monitoring circuit by providing a gate circuit in the output side of a watchdog timer circuit, thereby preventing sending out of an abnormal signal from this circuit. CONSTITUTION:The power source is turned on and the system is started. The CPU18 performs processing normally, and long time initial processing is performed at a software reset time. Accordingly, as an access time to the first watchdog timer WDT circuit 13 exceeds the reference time; an abnormal signal is given by a monostable multivibrator of the WDT circuit 13 due to the noise of a power source. However, data stored in an ROM 19 is held in a controlling register 16 by the output of the second address decoding circuit 12 through a data bus interface circuit 17 and an interface circuit 15. Accordingly, a gate circuit 14 is retained in a closed state, and the abnormal signal US is not outputted.

Description

【発明の詳細な説明】 （１）発明の技術分野 本発明はＣＰＵ暴走監視回路、特にウォッチドッグタイ
マ回路を用いたＣＰＵ暴走監視回路に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a CPU runaway monitoring circuit, and particularly to a CPU runaway monitoring circuit using a watchdog timer circuit.

（２）従来技術と問題点 一般に、ＣＰ　Ｕ　（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓ
ｉｎｇ　Ｕｎｉｔ：中央処理・装置）が暴走したか否か
を監視する場合に、ウオッチドックタイマ（ＷａｔＣｈ
ＤＯｇＴｉｍｅｒ；以下ＷＤＴと称する）回路が使用さ
れることがある。(2) Prior art and problems In general, CPU (Central Process
When monitoring whether a central processing unit (Central Processing Unit) has gone out of control, the watchdog timer (WatCh
A DOgTimer (hereinafter referred to as WDT) circuit may be used.

との〜Ｖ　ｉＤ　Ｔ回路は、第１のアクセスと第２のア
クセスとのインターバル時間を測定し、このインターバ
ル時間が所定の基準時間の下限以下または上限以上の場
合Ｋ、異常検出信号を出力するようになっている。The ~ViD T circuit measures the interval time between the first access and the second access, and outputs an abnormality detection signal if this interval time is less than or equal to the lower limit or more than the upper limit of a predetermined reference time. It looks like this.

しかし、このＷＤＴ回路はモノステーブルマルチバイブ
レータにより４成されている。従って、従来のようにＷ
ＤＴ回路だけでＣＰＵ暴走監視回路を組み立てた場合、
電源のノイズ等が原因でＷＤＴ回路が一度もアクセスさ
れていないのに異常信号を発生することがある。However, this WDT circuit is made up of four monostable multivibrators. Therefore, W
When a CPU runaway monitoring circuit is assembled using only DT circuits,
Due to power supply noise or the like, an abnormal signal may be generated even though the WDT circuit has never been accessed.

また、ＣＰＵによるソフトウェア処理時間中のイニシャ
ルプログラム処理が長くなるとＷＤＴ回路のアクセスイ
ンターバル時間が長くなり、ＣＰＵが暴走していないに
も拘らずＷＤＴ回路から異常信号が出力することがある
。Furthermore, if the initial program processing during the software processing time by the CPU becomes longer, the access interval time of the WDT circuit becomes longer, and an abnormal signal may be output from the WDT circuit even though the CPU is not out of control.

ｆ３ｉ　　発明の目的 本発明の目的は、ＷＤＴ回路の出力側にゲート回路を設
けることにより正常処理時に１はこのゲート回路を閉じ
てＷＤＴ回路から異常信号が送出されないようにしてＣ
ＰＵ暴走監視回路の誤動作を防止することにある。f3i Object of the Invention An object of the present invention is to provide a gate circuit on the output side of the WDT circuit so that during normal processing, 1 closes this gate circuit and prevents abnormal signals from being sent out from the WDT circuit.
The purpose is to prevent malfunction of the PU runaway monitoring circuit.

（４）発明の構成 本発明によれば、バスを介してＣＰＵとウォッチドッグ
回路を相互接続し、ウォッチドッグ回路から出力される
異常信号の有無によりＣＰＵの暴走を監視する回路にお
いて、ウォッチドッグ回路の出力側にゲート回路が設け
られていると共に該ゲート回路の入力側と上記バス間に
は制御レジスタが設けられ、ＣＰＵが暴走した場合には
制御レジスタによりゲート回路が開かれて異常信号が出
力されＣＰＵが暴走しない場合には制御レジスタにより
ゲート回路が閉鎖されて異常信号が出力されないように
なっていることを特徴とするＣＰＵ暴走監視回路が提供
される。(4) Structure of the Invention According to the present invention, in a circuit that interconnects a CPU and a watchdog circuit via a bus and monitors runaway of the CPU based on the presence or absence of an abnormal signal output from the watchdog circuit, the watchdog circuit A gate circuit is provided on the output side of the CPU, and a control register is provided between the input side of the gate circuit and the bus, and when the CPU goes out of control, the gate circuit is opened by the control register and an abnormal signal is output. Provided is a CPU runaway monitoring circuit characterized in that when the CPU does not runaway, a gate circuit is closed by a control register so that an abnormal signal is not output.

１５）発明の実施例 以下、本発明を実施例により添付図面を参照して説明１
−る。15) Embodiments of the Invention The present invention will be explained below by way of embodiments with reference to the accompanying drawings.
-ru.

図は本発明に係るＣＰＵ暴走監視回路の構成図である。The figure is a configuration diagram of a CPU runaway monitoring circuit according to the present invention.

図の回路は、ＷＤＴ回路１３の出力側にゲート回路１４
が設けられこのゲート回路１４を制御レジスタ１６で制
御することにより、正常時であってもＷＤＴ回路を所定
の基準時間内にアクセスできない場合には異常信号ＵＳ
が出力されないようにしたものである。The circuit shown in the figure has a gate circuit 14 on the output side of the WDT circuit 13.
By controlling this gate circuit 14 with a control register 16, if the WDT circuit cannot be accessed within a predetermined reference time even under normal conditions, an abnormality signal US is generated.
This is so that it is not output.

ＣＰ０１８は、例えばマ・ｆクロプロセッサであす、該
ＣＰ　Ｕ　１８　ｉｄマイクロプロセッサバス１７を介
して１％ＯＭ　１９　、　ＲＡＭ２０と接続されている
。−上記マイクロプロセッサパス１７にはアドレスバス
インタフェイス回路１０及びデータバスインタフｚ−（
ス回路１５が接続されてＣＰＵ側とＷＤ’Ｔ回路１３側
との間で相互接続が確保されている。The CPU 18 is, for example, a macroprocessor, and is connected to the 1% OM 19 and the RAM 20 via the CPU 18 id microprocessor bus 17. - The microprocessor path 17 includes an address bus interface circuit 10 and a data bus interface z-(
A bus circuit 15 is connected to ensure interconnection between the CPU side and the WD'T circuit 13 side.

アドレスバスインタフェイス回路１０の出力は第１アド
レスデコード回路１１と第２アドレスデコード回路１２
へ供給される。廿たデコード回路１１の出力はＷＤＴ回
路１３へ、他方デコード回路１２の出力は制御レジスタ
１６へ供給される。The output of the address bus interface circuit 10 is a first address decode circuit 11 and a second address decode circuit 12.
supplied to The output of the decode circuit 11 is supplied to the WDT circuit 13, and the output of the decode circuit 12 is supplied to the control register 16.

制御レジスタ１６Ｆｉデータパスインタフヱイス回路１
５を介して供給されるデータを上記デコード回路１２の
出力により保持し、ゲート回路１４を制御する役割を有
する。Control register 16Fi data path interface circuit 1
It has the role of holding the data supplied via the decoding circuit 5 by the output of the decoding circuit 12 and controlling the gate circuit 14.

上記の構成を有する本発明に係るＣ　Ｐ　Ｕ暴走監視回
路は次のように動作する。The CPU runaway monitoring circuit according to the present invention having the above configuration operates as follows.

今、電源が投入されてシステムが起動し、ＣＰＵは正常
に処理を行なっている。しかし、ソフトウェアリセット
時で非常に長い時間イニシャル処理が行なわれている。Now, the power has been turned on, the system has started up, and the CPU is processing normally. However, initial processing is performed for a very long time during software reset.

従って最初のＷＤＴ回路１６へのアクセス時間が基準時
間を越えるので電源ノイズによりＷＤＴ回路１３のモノ
マルチが異常信号を発する。Therefore, since the first access time to the WDT circuit 16 exceeds the reference time, the monomulti of the WDT circuit 13 issues an abnormal signal due to power supply noise.

ところがＲＯＭ１９に予め格納されたデータがデータバ
スインクフェイス回路１７、インタフェイス回路１５を
経由してデコード回路２の出力により制御レジスタ１６
に保持されてｂる。従ってゲート回路１４は閉鎖された
状態を維持し、異常信号ＵＳは出力されない。However, the data previously stored in the ROM 19 is transferred to the control register 16 via the data bus ink face circuit 17 and the interface circuit 15 by the output of the decode circuit 2.
It is held in b. Therefore, the gate circuit 14 remains closed and the abnormal signal US is not output.

（６）発明の効果 上記のＪＪｆｌ、ｂ、不発明によればＷＤＴ回路の出力
側にゲート回路が設けられ該ゲート回路が制御レジスタ
により制御されることにより、正常処理時にはＷＤＴ回
路から異常信号が送出されずＣＰＵ暴走監視回路の誤動
作が防止される。(6) Effects of the Invention According to JJfl, b, and the non-invention described above, a gate circuit is provided on the output side of the WDT circuit and the gate circuit is controlled by a control register, so that an abnormal signal is generated from the WDT circuit during normal processing. This prevents the CPU runaway monitoring circuit from malfunctioning.

【図面の簡単な説明】[Brief explanation of drawings]

図１−ｊ本発明に係るＣＰＵ暴走監視回路の構成図であ
る。FIG. 1-j is a configuration diagram of a CPU runaway monitoring circuit according to the present invention.

Claims (1)

【特許請求の範囲】[Claims] パスを介してＣＰＵとウォッチドッグ回路を相互接続し
、ウォッチドッグ回路から出力される異常信号の有無に
よりＣＰＵの暴走を監視する回路において、ウォッチド
ッグ回路の出力側にゲート回路が設けられていると共に
該ゲート回路の入力側と上記バス間には制御レジスタが
設けられ、ＣＰＵが暴走した場合には制御レジスタによ
りゲート回路が開かれて異常信号が出力されＣＰＵが暴
走しない場合には制御レジスタによりゲート回路が閉鎖
されて異常信号が出力されないようになっていることを
特徴とするＣＰＵ暴走監視回路。In a circuit that interconnects a CPU and a watchdog circuit via a path and monitors runaway of the CPU based on the presence or absence of an abnormal signal output from the watchdog circuit, a gate circuit is provided on the output side of the watchdog circuit. A control register is provided between the input side of the gate circuit and the bus, and when the CPU goes out of control, the control register opens the gate circuit and outputs an abnormal signal.If the CPU does not go out of control, the control register opens the gate. A CPU runaway monitoring circuit characterized in that the circuit is closed so that no abnormal signal is output.
JP57226612A 1982-12-27 1982-12-27 Cpu run-away monitoring circuit Granted JPS59119453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57226612A JPS59119453A (en) 1982-12-27 1982-12-27 Cpu run-away monitoring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57226612A JPS59119453A (en) 1982-12-27 1982-12-27 Cpu run-away monitoring circuit

Publications (2)

Publication Number Publication Date
JPS59119453A true JPS59119453A (en) 1984-07-10
JPH0218503B2 JPH0218503B2 (en) 1990-04-25

Family

ID=16847923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57226612A Granted JPS59119453A (en) 1982-12-27 1982-12-27 Cpu run-away monitoring circuit

Country Status (1)

Country Link
JP (1) JPS59119453A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61296443A (en) * 1985-06-24 1986-12-27 Mitsubishi Electric Corp Watchdog timer
JPS6260038A (en) * 1985-09-10 1987-03-16 Hochiki Corp Watchdog circuit
JPS6310248A (en) * 1986-06-30 1988-01-16 Nec Corp Detecting system for abnormal state of microprocessor
JPH01211138A (en) * 1988-02-19 1989-08-24 Fujitsu Ltd Resetting circuit for supervising circuit of computer system
JPH01172152U (en) * 1988-05-24 1989-12-06
JPH0325943U (en) * 1989-07-24 1991-03-18
JP2007095688A (en) * 2005-09-27 2007-04-12 Xerox Corp Wire assembly removing/housing tool for dicorotron unit
JP2012155454A (en) * 2011-01-25 2012-08-16 Nec Corp System monitoring device and system monitoring method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103723A (en) * 1980-01-23 1981-08-19 Nippon Denso Co Ltd Automatic reset method for computer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103723A (en) * 1980-01-23 1981-08-19 Nippon Denso Co Ltd Automatic reset method for computer

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61296443A (en) * 1985-06-24 1986-12-27 Mitsubishi Electric Corp Watchdog timer
JPH0519738B2 (en) * 1985-06-24 1993-03-17 Mitsubishi Electric Corp
JPS6260038A (en) * 1985-09-10 1987-03-16 Hochiki Corp Watchdog circuit
JPS6310248A (en) * 1986-06-30 1988-01-16 Nec Corp Detecting system for abnormal state of microprocessor
JPH01211138A (en) * 1988-02-19 1989-08-24 Fujitsu Ltd Resetting circuit for supervising circuit of computer system
JPH01172152U (en) * 1988-05-24 1989-12-06
JPH0325943U (en) * 1989-07-24 1991-03-18
JP2007095688A (en) * 2005-09-27 2007-04-12 Xerox Corp Wire assembly removing/housing tool for dicorotron unit
JP2012155454A (en) * 2011-01-25 2012-08-16 Nec Corp System monitoring device and system monitoring method

Also Published As

Publication number Publication date
JPH0218503B2 (en) 1990-04-25

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