JPS5935216A - Multiple information processing system - Google Patents

Abstract

PURPOSE:To protect data in an information processor in case of abnormality of a power source by providing a request arbitration adding circuit having specific functions in a main storage device. CONSTITUTION:A power source device 1, when detecting power source abnormality, reports the anrormality to the information processor 4 and main storage device 7 through a power source abnormality report line 100. The information processor 4 once receiving the report starts enqueuing its own information in the main storage device 7 through a main storage access request line 103. The main storage device 7, on the other hand, inputs the report of the power source abnormality by the request arbitration adding circuit 8. This adding circuit 8 gives higher priority to an access request from the information processor 4 to the main storage device than that from other information processors 5 and 6. Therefore, information in the information processor is read to the main storage at a high speed and the data is protected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a multiplex information processing system, and more particularly to a multiplex information processing system that protects data contained within an information processing device when a power failure occurs.

[Prior art]

Conventionally, this type of information processing apparatus has been almost defenseless against power failures, and data protection has been inadequate because of the requirement to turn off the power as soon as possible to protect the apparatus. For some power supply abnormalities (such as AC line abnormalities), it is possible to lengthen the time from when the power supply abnormality is detected until the power is actually turned off by adding various devices to the AC line. For data protection, information in an information processing device and information in a main storage device is flushed to an external file device.

However, in the case of a DC abnormality (overcurrent, overvoltage), the first priority is to protect the device, so it is necessary to shorten the time from when a power abnormality is detected until the power is actually turned off as short as possible.

In addition, due to demands for performance, recent information processing devices have been incorporating more and more information into them.
It is becoming difficult to clean out the information that has been captured internally in such a short period of time.

In a multiplex information processing system, there is no need to flush to the external file device like in the case of AC abnormality, and it is only necessary to flush to the main memory (other information processing can continue to operate). ), the flushing to the main memory competes with the access to the main memory of other information processing devices, does not complete within a predetermined short time, and has the disadvantage that data cannot be protected.

(Object of the Invention) An object of the present invention is to provide a multiplex information processing system that makes it possible to protect data in an information processing device when an abnormality is detected in the power supply of the information processing device.

[Structure of the invention]

The multiple information processing system of the present invention includes a plurality of information processing devices, a main storage device shared by the information processing devices, and a power supply device capable of independently detecting power supply abnormalities for each information processing device. In a multiple information processing device system that saves data in a corresponding information processing device into a main storage device when a power supply device detects an abnormality, a notification means notifies the main storage device of a power abnormality when a power supply device detects an abnormality; The main storage device includes request arbitration means that responds to the notification means and prioritizes access requests to the main memory from the information processing device corresponding to the notification higher than access requests from other information processing devices. It consists of

[Explanation of Examples]

Next, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a system configuration diagram showing an embodiment of the present invention, which includes a plurality of information processing devices 4, 5, . . . 6, and power supplies 1, 2, . . . 3 and -main storage device 7. The main memory device 7 further includes a request arbitration addition circuit 8 and a main memory device main body 9.

FIG. 2 is a detailed circuit diagram of an example of the request arbitration addition circuit 8 in the main memory.

In the embodiment shown in FIGS. 1 and 2, the processing devices 4.5, . . .
...6 and power supply devices 1, 2. . . . 3 have the same configuration, so the following description will mainly focus on the processing device 4.
Describe about.

When power supply 1 detects a power abnormality, power abnormality report line 1
00, the information processing device 4 and the main storage device 7
report to. When the information processing device 4 receives this report, it starts an operation to save the information in its own information processing device into the main storage device γ via the main storage access request line 103.

On the other hand, in the main memory 7, the above report is sent to the request arbitration circuit 8.
is input. The request arbitration circuit 8 is connected to the power supply devices 1, 2, . ...Power abnormality report signal line 10 from 3
0. '101. ...The contents of 102 are led to Noah Gate 200. 5- output of 200 (or game) 204, 205 via signal line 300
゜...It is sent to 206. Orgate 204.
Power abnormality report lines 100, 101;""103 from the corresponding power supply devices 1, 2, . . . 3 are input to other inputs of 205. In other words, the outputs of (or game) 204, 205...206 are output from other information processing devices because the corresponding power supply devices of the corresponding information processing devices 4, 5...6 have become abnormal. Set to 1 when priority should be higher than main memory access requests.

The outputs of the AND gates 201, 202...206 (or game) 204, 205...206 are transmitted through signal lines 301, 302...303, respectively. . . . is connected to one input of 203. ANDGATE 201, 202...
. . . Another input of 203 is a main memory access request signal line 103.104゜ from each corresponding information processing device.
...105 is input.

The output of the AND gate 201 is sent to the main memory device body 9 via the signal line 106'f. The subsequent operation is the same as that of a conventional main memory device, and will therefore be omitted. The output of the AND gate 201 is 1 when there is a main memory access request from the information processing device 6-4 and the power supply of the information processing device 4 is abnormal or the power supply of other information processing devices is not abnormal.
becomes.

A signal obtained by inverting the output of the AND gate 201 by an inverter 207 is input to another input of the AND gate 202 via a signal line 304'.

The output of the AND gate 202 is sent to the main memory device body 9 via the signal line 107'r. The output of 202 is when there is no main memory access from the information processing device 5, main memory access from the information processing device 4 is not prioritized, and the power supply of the information processing device 5 is abnormal or the other information processing device is Flashes 1 when there is no abnormality in the power supply. The subsequent operation is the same as that of a conventional main memory device, and will therefore be omitted.

The other input of AND gate 203 is Noah gate 2.
09 is input via the signal line 306. The main memory main body 9 located at the upper level in FIG.
Signal lines 106, 107.・・・・・・
... has been input.

That is, the output of the NOR gate 209 becomes 1 when the access request to the upper main memory is low.

The output of the AND gate 203 indicates that there is an access to the main memory from the information processing device f6, and there is no request for access to the main memory main body 9 located at the upper level in FIG.
When there is no abnormality in the power supply of other information processing devices, the signal becomes 1 and is input to the main memory main body 9 via the signal line 108. The subsequent operation is the same as that of a conventional main memory device, and will therefore be omitted.

The above explanation can be generally described as follows. A main memory access request from a certain information processing device is made when the power supply device of another information processing device is not abnormal or when the power supply device of the information processing device is abnormal and there is no main memory access request at a higher level in Fig. 2. is sent to main memory.

In the above embodiment, the main memory access requests at the top in FIG. 2 have the highest priority, but it is easy to change this according to the acceptance history of past access requests.

〔Effect of the invention〕

In the multiple information processing device system of the present invention, when a power supply device supplying power to a certain information processing device detects an abnormality,
By giving a main memory access request from the information processing device a higher priority than other requests, information in the information processing device can be flushed out to the main memory at high speed, thereby making it possible to fully protect the data.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram showing one embodiment of the present invention;
The figure is a circuit diagram showing details of the request arbitration addition circuit in the main memory. 1.2.3...Power supply device, 4,5.6...
・・Information□Processing device, 7・・・・Main storage device, 8・
. . . Request arbitration additional circuit, 9 . . . Main storage device main body. 9-Z f diagram

Claims (1)

[Claims] The information processing apparatus includes a plurality of information processing apparatuses, a main memory shared by the information processing apparatuses, and a power supply unit capable of independently detecting a power supply abnormality for each information processing apparatus, and that responds when the power supply apparatus detects an abnormality. In a multiple information processing system in which data in a device is saved in a main memory, a notification means for notifying the main storage of a power abnormality when a power supply detects an abnormality; Multiplex information processing characterized by having a request arbitration means that responds to the notification and prioritizes a request for access to the main memory from an information processing device corresponding to the notification higher than access requests from other information processing devices. system.