JPS5999554A - Fail-safe circuit of electronic computer system - Google Patents

Abstract

PURPOSE:To prevent the occurrence of an abnormal interruption at power-off by providing the power-off detecting circuit of a process input/output device control part, and inhibiting the interruption by its detection signal. CONSTITUTION:The process input/output device control part (P-I/O control part) 6 is provided with the power-off detecting circuit 9 consisting of a photocoupler which detects break of a power supply instantaneously in the system wherein a CPU1 and the P-I/O control part 6 are coupled together by an input/output bus 2. A gate circuit 3 provided between the input/output bus 2 and P-I/O control part 6 is provided with an inhibiting circuit which inhibits the transmission of an abnormal interruption signal to the input/output bus 2 by the detection output of the power-off detecting circuit 9. Consequently, the abnormal interruption signal is prevented securely from being inputted to the CPU when the power supply of P-I/O control part is disconnected.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention solves the problem of failure and failure in the electronic d calculator (hereinafter referred to as ``double calculator'') system which is widely used in fields such as military swords and general industry. Safe circuit [Technical background of the invention and its points of reference] Figure 1 shows the central processing unit C and below in this type of computer system, CP (referred to as J) and process input/output. Figure C' shows an example of an interface configuration with data a = lS (hereinafter referred to as -)' -I control unit), where 1 is CP[j.

2 is an input/output path consisting of an input/output data line, a control gland, and a control line, 3 is a gate circuit, and 4 is an input/output data and control line.
1 is a signal gate, 5 is an interrupt (M gate, 6 is for exchanging information between an external operation vehicle, control device, etc. (not shown) and the CPU Z)'-I/u control unit, 1
Multiple units may be connected to one e and t'uz unit. Further, 7 is an input/output circuit for input/output data and a control number, and 8 is an interrupt signal output circuit for issuing a service request to the CPU Z 1m, which are constructed as shown in FIG.

In the configuration described above, when performing a demta transfer between the CPUI and the i'-1/11 control unit 6, the 1 interrupt signal traces from the interrupt signal output circuit 8 to the interrupt gate 5, iJ, and the human output. By connecting CP [JZl] via bus 2, the input/output circuit 7 of CPUI and P-I/U controller 6 is connected.

C data transfer is started via gate 4.

Naturally, one of the P-Is is scheduled for inspection.
7'o If the power to the control unit 6 is cut off or if this power is cut off due to a failure, the power will be cut off.
The logic level of the interrupt signal output circuit 8 of the 174J control unit 6 is unstable, and a continuous interrupt signal is generated, and this signal is transmitted via the interrupt signal group gate 5'a;J&3 input/output bus 2. This abnormal interrupt signal may be input to the CPUI and cause the CPU Z to stop. □As mentioned above, in the conventional system, the power of one P-I/U control unit 6 in the computer system is If the CPCJI is stopped due to a shutdown, there is a problem that it will have a direct negative impact on the operation of the system. The purpose is 1' - When the I/U control glS power is cut off: CPυC2 Is a strange interrupt signal input? The object of the present invention is to provide a fail-safe circuit for a computer system that can reliably prevent failure.

[Summary of the invention]

In order to achieve the above object (2), in the present invention, in an electronic computer system in which a central processing unit and a process input/output device control unit are interconnected by an input/output bus, the process input/output device is In order to prevent a power outage of the control unit, a detection signal from a power outage detection circuit and a power outage detection circuit is used to prevent abnormal interrupt signals from being sent to the input/output bus (2). □[A further example of the invention] The following is a diagram showing the present invention (1). (23
This figure shows an example of the interface between the CPU and the P-I/V pricing department, and the same parts as those in FIG.

I will only discuss two different parts here.

Figure CM Ite, 9 Ha@'Qki P -17U system 7,11
A power-off detection circuit consisting of a photocoupler that instantaneously detects the power-off of section 6 C: 4, 10 detects an abnormality to the serious crime input/output bus 2 by means of a measure-off detection signal from the power-off detection circuit 9. This is an interrupt prohibition gate consisting of a transistor as a side stop circuit that prevents the sending of an interrupt signal, and is internally a safe circuit. Since it is in the on state, the photocoupler of the power failure detection circuit 9 is in the on state, and the transistor of the 1-interrupt inhibiting gate 10 is in the off state, and the collector of this transistor is at the logic value "11" at the time of b01.

P --i/(J control unit 6 makes a service request to CPUZ, so interrupt with logical value "1"/"F lb
When the interrupt signal is output from the interrupt signal output circuit 8.

This signal passes through the interrupt signal gate 5, is sent out to the input/output path 21, and is input to the CPU.

As a result, CPUZ and P-I/u control unit 6 (7
) Data transfer is started with the input/output circuit 7 via the gate 4.

Partly, when the power of the P-1/LJ control unit 6 is cut off, the -source cut-off circuit 9 instantly detects the power cut and the photocoupler turns off. by 1
The interrupt disabling gate 100J transistor is turned on, and the collector of this transistor has a logical value of "1". As a result, this abnormal interrupt signal is not sent to the input/output path 2 and is not input to the CPOJC. [Effect of the Invention] As explained above, the present invention p-i/.

Power outage of the control unit is detected by the power outage calibration circuit.

In addition, this detection signal was used to prevent abnormal interrupts to the input/output path C2 from being sent out. It is possible to reliably prevent T=j from the occurrence of an abnormal interrupt signal being input to the system (+7), thereby preventing the CPU from shutting down (2) of one P-I10 control E915 in the system. It can provide a fail-safe circuit for computer systems that do not have

[Brief explanation of the drawing]

Figure 1 shows the CPU and P in the conventional t
-Ilo Control g (<A diagram showing an example of interface development, Fig. 2 is a configuration factor showing one implementation f9il of the present invention □ I...L: PLl, 2... Input/output bus, 3...・
Gate circuit, 4... Gate for input/output take and control signal, 5... Gate for interrupt signal p, 6... P -I/(
J control ff1S. 7... Input/output circuit, 8... Egg j included signal output circuit,
9... Electrical disconnection detection circuit, 10... Gate for inhibiting interrupts.

Claims (1)

[Claims] An electronic computer system comprising a central processing unit and a process input/output device control unit coupled by an input/output path, where ≦2, l
A power-off detection circuit that instantaneously detects a power-off of a process input/output device control unit. A fail-safe circuit for a Soshi computer system characterized by comprising a detection signal from this power-off detection circuit (1) a stop circuit for preventing sending of an abnormal interrupt signal to the input/output path;