JP2828331B2 - Reset control method for large-scale hardware - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a reset control method for large-scale hardware in which a plurality of hardwares each having an individual power supply system are connected, and directly connects a plurality of hardwares each having an individual power supply system. The purpose of the present invention is to provide a large-scale hardware reset control method that can prevent the destruction of elements even when power is turned on / off individually or an abnormality occurs in the power supply voltage. Connection circuit with hardware
Equipped with a power supply voltage monitoring circuit that generates an abnormal output signal when it detects a drop in the power supply voltage of its own power supply system. Each hardware inputs the output signal of the OR circuit and the abnormal output signal of its own power supply system,
A control circuit is provided for generating a signal for deactivating the connection circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-scale hardware reset control system in which a plurality of hardware units each having an individual power supply system are connected.

In recent years, large-scale hardware in which a plurality of pieces of hardware having a large number of circuits are connected to each other has been configured. Specifically, for example, there is a highly parallel processor system in which many processors are interconnected.

As such hardware becomes larger and faster, its power consumption also increases. Generally, in a large-scale hardware, a power supply current is supplied by a plurality of power supply systems. In the case of using a bipolar element such as a TTL, when the power supply voltage is not applied, the power supply is turned off, so that there is no restriction on the order of turning on and off the power.
However, when a CMOS device is used, if the power supply sequence cannot be followed, an excessive current may flow to destroy the device.

[Prior Art] FIG. 3 is an explanatory diagram of a conventional example.

In the figure, reference numeral 30 denotes hardware equipped with a large number (for example, 20) of processors 31 for parallel processing, each having an individual power supply 33. A large number of such hardware 30 is provided, and a large-scale highly parallel processor system is configured by connecting the respective hardware and transferring data to each other. A data bus 34 is provided for connecting the hardware to transfer data. The elements (including the processor) in the hardware are composed of CMOS elements that are suitable for integration into a circuit and that can suppress power consumption. Conventionally, when the power is turned on and off, or when a power failure occurs in hardware having an individual power supply 33 as described above, due to the operating principle of the CMOS device, the hardware is connected via the interconnected bus 34. An abnormal current may flow in the CMOS device of other hardware, causing the device to be destroyed.

In order to avoid such a situation, there is a method of performing a sequence control so as not to affect the turning on / off of the power supply 33 of each hardware 30 to others, but it is necessary to provide a control device. Instead of controlling the power-on / off sequence, the configuration shown in FIG. 3 uses a buffer 32 composed of a bipolar element (such as TTL) at the interface with the data bus.
Was established so that they do not affect each other.

[Problems to be Solved by the Invention] As described above, in the related art, an extra buffer using a bipolar element must be provided in order to prevent the destruction of other hardware elements when power is turned on / off or an abnormality occurs. There was a problem that had to be.

The present invention relates to a large-scale hardware capable of directly connecting a plurality of pieces of hardware having respective power supply systems to prevent the destruction of elements even when power is turned on / off individually or an abnormality occurs in the power supply voltage. An object is to provide a reset control method.

[Means for Solving the Problems] FIG. 1 is a block diagram showing the principle of the present invention.

In FIG. 1, reference numeral 10 denotes a plurality (# 0 to #n) each including therein a number of electronic circuits (not shown) such as processors.
11 is a power supply voltage monitoring circuit that generates an abnormal output (reset) signal when the power supply voltage drops or power is turned on in each hardware, and 12 is an output circuit that outputs a signal to a bus connected to other hardware , 13 is the reset control circuit, 14
Represents an OR circuit provided only in one piece of hardware (# 0), and 15 represents a connection circuit (bus) for connecting the respective pieces of hardware.

The present invention monitors each power supply in a plurality of hardware and generates an abnormal signal when the power supply is abnormal (when the power is turned on).
When an abnormal signal is generated from one of the hardware, the signal is detected, and a reset signal is supplied to all other hardware including the normal one to reset the entire system. It is.

[Operation] Each hardware 10 includes a power supply voltage monitoring circuit 11 that generates an abnormal output signal when a power supply voltage drop of a power supply system provided therein is detected. A disconnection is detected, and an abnormal output signal (or a reset signal) is generated from the abnormal signal generating means 111 by the detection output. Abnormal output signal is reset control circuit 13.
And resets the output circuit 12 in its own hardware. As a result, the output circuit 12 is reset to a state in which other hardware is not affected at all. An abnormal output signal is also generated when the power is turned on.

Each abnormal output signal from each hardware 10 is input to an OR circuit 14 provided in one of the many hardwares 10 (# 0 in FIG. 1), and the output is internally output as a reset signal. To the reset control circuit 13 of all the other hardware 10, and resets the respective output circuits 12 and turns off the connection with the connection circuit 15.

In this way, when the power supply voltage of all hardware is constantly monitored and an abnormality is detected, a reset signal is sent to a normal system, and the internal logic circuit such as a CMOS circuit is reset by the reset signal. Even if the interface part is turned off and the logic elements are directly connected to each other with a plurality of power supplies, it is possible to prevent the destruction of the CMOS elements when the power is turned off and on or when the power supply is abnormal. In addition, fail-safe control can be performed even in the case of cable disconnection or the like depending on the logic.

Embodiment FIG. 2 is a configuration diagram of an embodiment.

In FIG. 2, reference numeral 20 denotes a housing (corresponding to the hardware shown in FIG. 1) on which a plurality of electronic circuits such as processors are mounted. A power-on reset circuit having a mechanism for generating a reset signal (corresponding to the power supply voltage monitoring circuit in FIG. 1), 22 is for inputting and outputting data between an internal circuit and another housing via a bus CMOS gate array (CMOS
G / A), 23 is an AND circuit (corresponding to the reset control circuit 13 in FIG. 1), 24 is a wired or provided in only one housing (# 0 in this example) 10 in the whole system. Circuits (corresponding to the OR circuit 14 in FIG. 1), 25 and 26 are inverter circuits.

As shown in FIG. 2, the system includes (n + 1) housings, each of which is supplied with power of a different power supply system. Each housing generates a reset output (output of the inverted RESET terminal) from the power-on reset circuit 21 and receives a reset input output from one specific housing 20 (# 0). One specific case 20 (# 0) receives reset outputs from all cases, performs a logical sum operation, outputs the signal as an all-reset signal, and is supplied as a reset input for all cases 20. All of these circuits for reset control use bipolar elements (such as TTL) and use positive logic to realize fail-safe.

When a reset signal (“0”) is input to the reset terminal (RESET), the gate array 22 provided in each case unconditionally turns its output terminal (bus side) off (high impedance). To interrupt mutual signal exchange.

The power-on reset circuit 21 outputs a "1" signal from the inverted RESET output terminal when the power supply is normal, and outputs a "0" signal (representing a reset signal) having a fixed width when the power supply voltage decreases or when the power supply is turned on. Occurs and then returns to the original "1" signal.

On the other hand, the wired-OR circuit 24 outputs an output signal from a reset output terminal (represented by an inverted RESET) of the power-on reset circuit 21 of each of the housings # 0 to #n to the inverter circuit 2.
The data is input through the circuit 5 and a logical OR is obtained by a wired OR circuit 24 driven by an open collector element.

When the power of all the enclosures 20 is normal, a “0” signal is input from each enclosure and the output of the wired-OR circuit 24 becomes “0” and is supplied to all the other enclosures 20 . In each case, this signal is inverted by the inverter circuit 26 and input to the AND circuit 23 as “1”. At this time, if the power supply of each case is normal, since “1” is output from the power-on reset circuit 21, “1” is output from the AND circuit 23 to the reset terminal (indicated by inverted RESET) of the gate array 22. However, the reset terminal performs a reset operation when "0" is input, so that no change occurs even when "1" is input. Each input of the wired-OR circuit 24 is connected to a power supply (5 V) via a pull-up resistor. If the power is cut off at the case where the input signal is generated, the "1" A signal is generated. The output signal (all reset signal) of the wired-OR circuit 24 is supplied to all the casings 20, but the power is supplied via a pull-up resistor on the input side of the casing 20, and the wired / If no signal arrives from the OR circuit 24, a "1" signal is generated.

 The operation in each case will be described below.

When power is first turned on in the case of # 0.

When the power of the chassis # 0 is turned on, the internal power-on reset circuit 21 operates to generate the reset signal (“0”) for a fixed time as described above. At the same time, the CMOS element of the internal gate array 22
Is input to the reset terminal and reset. On the other hand, at this time, since the power is not supplied to the other casings # 1 to #n, the input side of the wired-OR circuit 24 is a "1" signal due to the pull-up resistor. Therefore, the all reset signal becomes "1" and is supplied as a reset input of each of the cases # 1 to #n. When the power is turned on to all other housings and the operation period of the power-on reset circuit 21 ends, the all-reset output becomes "0" for the first time, and the reset of the entire system is released.

When the power is first turned on in a case other than the case # 0 When the power is turned on in a case other than the case (# 0), the internal power-on reset circuit 21 operates and the reset output is performed for a fixed time ( “0”). At the same time, “0” is also input to the gate array 22 inside the own case via the AND circuit 23 to perform a reset operation. When the power-on reset operation is released, the reset output from the inverter circuit 25 becomes “0”. At this time, since the power is not supplied to the housing 20 of # 0, the output from the wired-OR circuit 24 is not supplied. No output has occurred. However, since the power supply is connected to the all-reset signal line, which is the output of the wired-OR circuit 24, via a pull-up resistor in each case, a "1" signal is generated. This signal is supplied as a reset signal to all cases. Then, in the case where the power is turned on, the signal is inverted by the inverter circuit 26 to “0”, input to the AND circuit 23, and the output is output as the reset signal (“0”).
And reset.

Only when the power is turned on to all other chassis and the power-on reset period ends, the all-reset output becomes “0” and the reset of the entire system is released.

When the power is cut off in the case # 0 When the power is cut off or the voltage drops due to the abnormality in the case 20 of # 0, the power-on reset circuit 21 operates and sets the reset output to “0”. At the same time, the gate
Reset array 22. The output signal "1" inverted by the inverter circuit 25 generates an all reset signal "1" from the wired OR circuit 24, and resets the entire system. Even if the power supply voltage drops and the internal reset control element does not operate, the all-reset output is an open collector element, so that the off-state is maintained. Other housings detect the all-reset signal that has become “1” by their own internal pull-up resistor, and reset each of them.

When power-off occurs in the case other than # 0 When the power of the case other than # 0 is cut off or the voltage drops due to an abnormality, a reset output of a fixed width ("0") is performed by the function of the power-on reset circuit 21. Occurs and circuit 23
From the gate array 22. At the same time, the signal which has become "1" in the inverter circuit 25 is input to the wired or circuit 24 of the chassis # 0, and the all-reset signal is set to "1" to reset the entire system.

When the cable is disconnected If the cable is disconnected for any reason, there are two cases: i) the reset output signal of the block of each case does not reach, and ii) the all reset signal does not reach from the case of # 0. .

In either case, the pull-up resistor inside each housing
All the casings are in the reset state, and the fail-safe control is realized.

[Effects of the Invention] According to the present invention, even when the CMOS elements are directly connected to each other by a plurality of power supply systems, it is possible to prevent the CMOS elements from being destroyed when power is turned on / off or when the power is abnormal. Further, by devising the logic (positive logic, negative logic), fail-safe control can be performed even for failures such as cable disconnection.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG.
FIG. 3 is an explanatory view of a conventional example. In FIG. 1, 10: hardware (# 0 to #n) 11: power supply voltage monitoring circuit 12: output circuit 13: reset control circuit 14: OR circuit 15: connection circuit (bus)

Claims (2)

(57) [Claims] In a large-scale hardware reset control system in which hardware each having an individual power supply system is connected in a cascaded manner, each hardware (10) is connected to a connection circuit (15) to another hardware. A power supply voltage monitoring circuit (11) that generates an abnormal output signal when it detects a drop in the power supply voltage of its own power supply system, and ORs the abnormal output signals from all power supply systems including its own power supply system into one piece of hardware A control circuit (13) having an OR circuit, each of which receives the output signal of the OR circuit and the abnormal output signal of its own power supply system and generates a signal for deactivating the connection circuit; A large-scale hardware reset control method characterized by comprising: 2. The large-scale hardware according to claim 1, wherein the power supply voltage monitoring circuit comprises a power-on reset circuit that generates a reset signal when a power supply voltage drop and power-on are detected. Reset control method.