JPS5812062A - Output device for parallel electronic computer system - Google Patents
Output device for parallel electronic computer systemInfo
- Publication number
- JPS5812062A JPS5812062A JP56111132A JP11113281A JPS5812062A JP S5812062 A JPS5812062 A JP S5812062A JP 56111132 A JP56111132 A JP 56111132A JP 11113281 A JP11113281 A JP 11113281A JP S5812062 A JPS5812062 A JP S5812062A
- Authority
- JP
- Japan
- Prior art keywords
- computer
- slave
- output device
- control signal
- main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、一方の電子計算機が主系として稼動し、他方
の電子計算機が従系として稼動する並列電子計算機シス
テムの出力装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output device for a parallel computer system in which one computer operates as a main system and the other computer operates as a slave system.
第1図は従来の並列電子計算機システムのブロック図で
、同図において、[1)は主系電子計算機、(2)は従
系電子計算機、(3)は従来の出方装置、(4)は従来
の出方装置(3)に内蔵される切換回路である。Figure 1 is a block diagram of a conventional parallel computer system, in which [1] is the main computer, (2) is the slave computer, (3) is the conventional output device, and (4) is the main computer. is a switching circuit built into the conventional output device (3).
上記構成に係る並列電子計算機システムの制御信号の出
力動作について説明すると、出力装置(3)に内蔵され
る切換回路(4)は主系電子計算機(1)からの制御信
号を外部に出力するように切換えられている。し九がっ
て、出プ装置(3)位主系電子計算慎(1)および従系
電子計算機(2)からの制御信号を入力するが、切換回
路(4)は主系電子計算機(1)からの制御信号のみを
選択して外すへ出力するようになっている。To explain the output operation of the control signal of the parallel computer system according to the above configuration, the switching circuit (4) built in the output device (3) outputs the control signal from the main computer (1) to the outside. has been switched to. Then, the output device (3) inputs the control signals from the main electronic computer (1) and the slave electronic computer (2), but the switching circuit (4) inputs the control signals from the main electronic computer (1). ) is selected and output to the control signal.
しかしながら、第1図に示す従来の並列電子計算機シス
テムの出力fe II(3)は、主系電子計X機(1)
の故障にょシ制御信号が出方装置(3)に正しく入力さ
れなければ、たとえ従系電子計算機(2)からの制御信
号が出力装置(37に正しく入力されても、制御信号を
外部へ出力することはできず、さらに出方装置(3)が
故障した場合にも制御信号を外部へ出力することはでき
ないなどの欠点があった。However, the output fe II (3) of the conventional parallel computer system shown in FIG.
If the control signal is not correctly input to the output device (3), even if the control signal from the slave computer (2) is correctly input to the output device (37), the control signal will not be output to the outside. Further, even if the output device (3) fails, the control signal cannot be outputted to the outside.
本発明は上記のような従来のものの欠点を除去するため
になされたもので、主系電子計算機、従系電子計算機、
及び出力装置のいずれかが故障しても正しい制御信号を
外部へ出力できる並列電子計算機システムの出力装置を
提供するものである。The present invention has been made in order to eliminate the drawbacks of the conventional ones as described above.
The present invention provides an output device for a parallel computer system that can output a correct control signal to the outside even if one of the output devices fails.
上記目的を達成するために、本発明は、主系電子計算機
および従系電子計算機からの制御信号を入力する主系の
出力装置および従系の出方装置をそれぞれ設けると共に
、この主系の出方装置および従系の出力装置に、主系電
子計算機及び従系電子計算機からの制御信号を時間監視
する時間監視回路と照合回路を備えたものであり、以下
、第2図に基いて詳細に貌明する。In order to achieve the above object, the present invention provides a main system output device and a slave system output device that input control signals from the main system electronic computer and the slave system electronic computer, respectively, and also provides a main system output device and a slave system output device, respectively. This system is equipped with a time monitoring circuit and a verification circuit for time-monitoring control signals from the main computer and the slave computer in the main system computer and the slave system output device. Become clear.
第2図は本発明に係る並列電子計算機システムの出力装
置の一実施例を示すブロック図で、同図に2いて、(5
)は主系の出力装置、(6)は従系の出力vcr1tで
メジ、さらに(7)および(lj)はそれぞれ主系の出
力装置(5)および従系の出力装@ (61に内蔵され
、主系電子計算機(1)および従系電子計算機(2)か
らの制@信号を時間監視する時間監視回路、また、(9
)およびαGは、それぞれ主系の出力装置t(5)およ
び従系の出力装置(6)に内蔵され、主系電子計算!(
])および従系電子計算機(2)からの制御信号を照合
する照合回路である。FIG. 2 is a block diagram showing an embodiment of the output device of the parallel computer system according to the present invention.
) is the main output device, (6) is the slave output vcr1t, and (7) and (lj) are the main output device (5) and the slave output device @ (built in 61), respectively. , a time monitoring circuit for time-monitoring control @ signals from the main computer (1) and the slave computer (2), and (9
) and αG are built into the main system output device t(5) and the slave system output device (6), respectively, and are used for main system electronic calculation! (
]) and the control signal from the slave electronic computer (2).
上記構成に係る並列電子計算機システムの出方装置は、
まず、外部に対し制御を行う場合に、主系の出力装置(
5)が主系電子計算機(1)および従系電子計算機(2
)からの制御信号を入力し主系の時間監視回路(7)を
用いて核内制御信号があらかじめ定められた所定の時間
差内に入力された事全監視するとともに、主系の照合回
路(9)ヲ用いて、眼内制御信号の内容が一致している
ことを照合した後、外部に対し制御信号を出力する。The output device of the parallel computer system according to the above configuration is as follows:
First, when performing external control, the main output device (
5) is the main computer (1) and the slave computer (2).
), and uses the main system time monitoring circuit (7) to monitor whether the nuclear control signal is input within a predetermined time difference. ) to verify that the contents of the intraocular control signal match, and then output the control signal to the outside.
同様に、従系の出力装置(6) v′i、主系電子計算
機(1)および従系電子#f算機(2)からの制御信号
を入力し、従系の時間監視回路(8)を用いて該両制御
信号があらかじめ定められた所定の時間差内に入力され
た事を監視するとともに、従系の照合回路α(jを用い
て、該両制御信号の内容が一致していることを照合する
が、外部に対しては制御信号全出力しない。Similarly, control signals from the slave output device (6) v'i, the master electronic computer (1) and the slave electronic #f calculator (2) are input, and the slave time monitoring circuit (8) is used to monitor that the two control signals are input within a predetermined time difference, and a slave matching circuit α (j is used to check that the contents of the two control signals match). , but does not output all control signals to the outside.
次に、このような状態で、従系電子計算機(2)が故障
した場合には、主系の出力装置(5)の時間監視回路(
7)と照合回路(9)は機能を停止し、主系電子計算機
(1)の制御信号がそのまま外部へ出力され、また、主
系の出力装置(5)が故障した場合には、従系の出力装
置(6)によシ制御信号が外部へ出力される。Next, if the slave electronic computer (2) fails in such a state, the time monitoring circuit (
7) and the verification circuit (9) stop functioning, the control signal of the main computer (1) is output to the outside as is, and if the main output device (5) fails, the slave computer A control signal is output to the outside through the output device (6).
そして、主系電子計算機(1)が故障した場合には、従
系電子計算機(2)がこれを検知し、以後従系電子計算
機(2)の制御信号が従系の出力装置(b)により外部
へ出力される。If the main computer (1) malfunctions, the slave computer (2) will detect this, and from then on, the control signal of the slave computer (2) will be transmitted by the output device (b) of the slave system. Output to the outside.
さらに、主系電子計算機(1)および従系電子計算機(
2)からの制御信号が主系の出力装置t (5)に入力
されて動作している状態で、主系の時間監視回路(力に
よシ該両制御信号があらかじめ定められた時間差以上経
過して入力されたと判定された場合、あるいは主系の照
合回路(9)によシ該両制御信号が一致しないと判定さ
れた場合に1よ、運転員に制御出力不一致の警報を発令
し、以後従系電子計算機(1)の制御信号によシ運転を
継続するか、主系電子計算機(1)を停止して従系電子
計算機(2)の制御信号によシ運転を継続するかの判断
を運転員にまかせることができ、常に安全で確実な運転
を行うことができることになる。Furthermore, the main electronic computer (1) and the slave electronic computer (
When the control signal from 2) is input to the main system output device (5) and is operating, the main system's time monitoring circuit (by force) detects whether the two control signals have elapsed by a predetermined time difference or more. If it is determined that the two control signals have been input, or if the verification circuit (9) of the main system determines that the two control signals do not match, issue a warning to the operator that the control outputs do not match; Thereafter, it is determined whether to continue operation based on the control signal of the slave computer (1), or to stop the main computer (1) and continue operation based on the control signal of the slave computer (2). The decision can be left to the driver, allowing safe and reliable driving at all times.
なお、上記実施例では電子計算機(1)と出力装置(5
)を主系とし、電子計算機(2)と出力装置(6)を従
系としたが、電子計算機(1)と出力装置(5)を従系
とし、電子計算機(2)と出力装置(6)を主系として
もよいことは勿論である。また、並列システムを二重で
構成したが、多重系の場合にも同様に用いることができ
る。In the above embodiment, the electronic computer (1) and the output device (5)
) is the main system, and the computer (2) and the output device (6) are the slave system. ) may of course be used as the main system. Further, although the parallel system is configured with duplex systems, it can be similarly used in the case of multiple systems.
以上のように、本発明に係る並列電子計算機システムの
出力装置によれば、主系の出力装置および従系の出力装
置に、時間監視回路および照合回路が内蔵されているの
で、電子計算機あるいは出力装着が故障した場合にも制
御動作を継続して行うことができ、しかも電子計算機あ
るいは出力装置の故障を明確に検知できない場合にも、
以後の処r1tt−運転員の総合判断にまかせることに
よシ、誤った制御信号を出力することを防止できるなど
、システムの信頼性を向上できるという効果を奏する。As described above, according to the output device of the parallel computer system according to the present invention, since the main output device and the slave output device have built-in time monitoring circuits and collation circuits, Control operations can be continued even in the event of a failure in the installation, and even if failure of the electronic computer or output device cannot be clearly detected.
By leaving the subsequent processing to the comprehensive judgment of the operator, it is possible to prevent the output of erroneous control signals, thereby improving the reliability of the system.
第1図は従来の並列電子計算機システムの出力装置を示
すブロック図、第2図は本発明に係る並列電子計算機シ
ステムの出力装置の一実施例を示すブロック図である。
(1)・・主系電子計算機
(21曇・従系電子計算機
(3)#・従来の出力装置
(4J・・切換装置
(5)−・主系の出力装置
(6)−・従系の出力装置
(7)’−主系の時間監視回路
(8)―・従系の時間監視回路
(9)・・主系の照合回路
αQ・・従系の照合回路
なお、図中、同一符号は同一、または相尚部分を示す。
第1図
第2図FIG. 1 is a block diagram showing an output device of a conventional parallel computer system, and FIG. 2 is a block diagram showing an embodiment of the output device of a parallel computer system according to the present invention. (1) Main system computer (21 clouds, slave system computer (3) #, conventional output device (4J) - switching device (5) - main system output device (6) - slave system Output device (7)' - Main system time monitoring circuit (8) - Slave system time monitoring circuit (9) - Main system verification circuit αQ - Slave system verification circuit Note that the same symbols in the diagram Indicates the same or similar parts. Figure 1 Figure 2
Claims (1)
して稼動する並列電子計算機システムにおいて、主系電
子計算機および従系電子計算機からの両制御信号をそれ
ぞれ人力する主系の出力装置および従系の出力装置を設
けると共に、この主系の出力装置および従系の出力装置
に、主系電子計算機および従系電子計算機からの両制御
信号の時間監視と照合を行う時間監視回路および照合回
路をそれぞれ設けたことを特徴とする並列電子計X機シ
ステムの出力装置。In a parallel computer system in which one computer operates as the main computer and the other computer operates as the slave system, the main system output device and the slave computer manually input both control signals from the main computer and the slave computer, respectively. In addition to providing a system output device, the main system output device and the slave system output device are equipped with a time monitoring circuit and a collation circuit for time monitoring and comparison of both control signals from the main system electronic computer and the slave system computer. An output device for a parallel electronic meter X machine system, characterized in that each of them is provided.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56111132A JPS5812062A (en) | 1981-07-15 | 1981-07-15 | Output device for parallel electronic computer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56111132A JPS5812062A (en) | 1981-07-15 | 1981-07-15 | Output device for parallel electronic computer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5812062A true JPS5812062A (en) | 1983-01-24 |
Family
ID=14553253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56111132A Pending JPS5812062A (en) | 1981-07-15 | 1981-07-15 | Output device for parallel electronic computer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5812062A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0362229A (en) * | 1989-07-31 | 1991-03-18 | Toshiba Corp | Control system for collating duplex program |
JP2011113416A (en) * | 2009-11-27 | 2011-06-09 | Hitachi Ltd | Control device and control method |
JP2018169841A (en) * | 2017-03-30 | 2018-11-01 | 日本電気株式会社 | Control unit, multiplex system, multiplex method and program |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5680749A (en) * | 1979-12-05 | 1981-07-02 | Hitachi Ltd | Multiple computer system |
-
1981
- 1981-07-15 JP JP56111132A patent/JPS5812062A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5680749A (en) * | 1979-12-05 | 1981-07-02 | Hitachi Ltd | Multiple computer system |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0362229A (en) * | 1989-07-31 | 1991-03-18 | Toshiba Corp | Control system for collating duplex program |
JP2011113416A (en) * | 2009-11-27 | 2011-06-09 | Hitachi Ltd | Control device and control method |
JP2018169841A (en) * | 2017-03-30 | 2018-11-01 | 日本電気株式会社 | Control unit, multiplex system, multiplex method and program |
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