JPS61267810A - Deciding circuit for detection of service interruption - Google Patents

Abstract

PURPOSE:To eliminate the misjudgement of a service interruption by providing plural transmission lines for service interruption detecting signals and deciding no service interruption as long as no other output exists even when an interruption is given from an interruption controller. CONSTITUTION:A service interruption detector 1 monitors the power supply voltage of a system containing a CPU 4 and delivers its detecting signal when a service interruption occurs. The detector 1 is connected to an interruption controller 2 to produce an interruption signal from the service interruption detecting signal. This interruption signal is delivered to the CPU 4. Here an input interface 6 is provided in parallel to the controller 2 and at the same time a service interruption deciding program is provided to the CPU 4. Then the service interruption detecting signal is supplied to the controller 2 and the interface 6. It is decided whether the output of the interface 6 is supplied or not after the CPU 4 received an interruption. Then no service interruption is decided if no output of the interface 6 is detected. Then another routine is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power failure detection and determination circuit for a system having a central processing unit (CPU).

[Conventional technology]

FIG. 3 is a block diagram showing an example of a conventional power failure detection/judgment circuit. In the same figure, 1 is a power failure detector tare, and C
The power supply voltage of the system including the PU 4 is monitored and a power outage detection signal is output when a power outage occurs. Reference numeral 2 denotes an interrupt controller, which is connected to the power failure detector 1 through a transmission line 3a, and generates an interrupt signal when receiving the power failure detection signal, and the separate signal is input to the CPt 14 via the bus 5. .

By the way, when the power supply of the system including the CPU 4 is normal, the CPU 4 processes each routine based on a predetermined program and makes the system function stably, but when a power outage occurs to the power supply, the CPU 4 goes out of control. It causes great damage, especially to software, such as destruction of built-in memory. Therefore, when a power outage begins to occur, the occurrence of a power outage is notified to the CPU 4, and the CPU 4
It is necessary to execute a power outage countermeasure processing routine such as saving memory, and this power outage countermeasure processing routine is executed before the energy stored in the backup power supply or the capacitance of each device in the system is used up, and Usually, it must be completed in a very short time.

In the above conventional example, when the above-mentioned power supply is normal, the power failure detector 1 does not output, so the power failure detection judgment circuit does not operate. A power failure detection signal is output, and this power failure detection signal is transmitted to the interrupt controller 2 via the transmission line 3a. The interrupt controller 2 sends an interrupt signal to the CPU 4 via the bus 5. The CPU 4 recognizes that a power outage has occurred based on this interrupt signal, and starts executing the above-described power outage countermeasure processing routine.

[Problem that the invention seeks to solve]

Since the conventional power outage detection/judgment circuit is configured as described above, when noise occurs on the transmission line 3a or the interrupt controller 2 malfunctions, the CPU 4 erroneously determines that a power outage has occurred and performs the power outage countermeasure processing described above. Since the routine starts to be executed, in the worst case, the CPU 4 always executes only the power outage countermeasure processing routine and becomes unable to execute other routines, causing the system to malfunction.

This invention was made to solve the above problem.
The purpose of this invention is to obtain a highly reliable power outage detection/judgment circuit that is resistant to noise and malfunction.

[Means to solve the problem]

In order to achieve the above object, the present invention has a configuration in which one or more input interfaces are provided in parallel with the interrupt controller and connected through separate transmission lines to connect the CPU and the bus.

[Effect]

In this invention, even if the interrupt controller operates, the power outage countermeasure processing routine is not immediately entered, but after checking the input interface signal, the power outage countermeasure processing routine is entered, so even if the interrupt controller malfunctions, the CPtJ
There is no risk of misidentification.

〔Example〕

FIG. 1 shows one embodiment of the present invention, in which the interrupt has an input interface 6 parallel to the controller 2, and the CPU 4 has a power failure determination program shown in FIG. This is different from the conventional one shown in the figure. The input interface 6 is connected to the power failure detector 1 via a transmission line 3b, and is also connected to the CPU 4 via a bus 5 in terms of software by appropriate address assignment.

Next, the operation of this circuit will be explained with reference to the flow chart shown in FIG.

When the power failure detector l generates a power failure detection signal, the interrupt controller 2 creates an interrupt signal and puts it on the bus 5.
The input interface 6 also receives and outputs a power failure detection signal via the transmission line 3b. CPU4 is interrupt controller 2
If an interrupt is received from the input interface 6
If the output is input, it is determined that a power outage has occurred, and the above-described power outage countermeasure processing routine is executed.

However, if the output of the input interface 6 is "no", the power failure countermeasure processing routine is not executed even if the above-mentioned interrupt occurs, and the process returns to another routine, for example, the routine before the interrupt.

That is, even if there is an interrupt from the interrupt controller 2 side, if it is due to noise that has entered the transmission line 3a or a malfunction of the interrupt controller 2, it is determined that there is no power outage and other routines are executed. Execute.

Note that in the above embodiment, the program determines the presence or absence of an output from the input interface 2 only once.
Depending on the surrounding conditions, etc., a majority decision process may be performed in which the determination is made multiple times.

Further, in the above embodiment, the case where only one input interface is used has been described, but reliability can be improved by connecting a plurality of input interfaces to the power outage detector 1 through individual transmission lines. It can be increased further.

〔Effect of the invention〕

As explained above, this invention has a plurality of transmission lines carrying a power failure detection signal, and even if there is an interrupt from the interrupt controller side connected to the negative transmission line, the input interface connected to other transmission lines By adopting a configuration in which it is determined that there is no power outage if there is no output, even if the above-mentioned noise or malfunction occurs, the CPU is prevented from making a false determination, and reliability can be improved compared to the past. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart for explaining the operation of the above embodiment,
FIG. 3 is a block diagram of a conventional power failure detection/judgment circuit, and FIG. 4 is a flowchart for explaining the operation of the conventional example. In the figure, 1--power failure detector, 2--interrupt controller, 3a, 3b-transmission lines 1. l-CPU, 5-
...Bus, 6-Human interface. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A power outage detector that monitors the power supply voltage of a system that has a central processing unit and sends out a power outage detection signal when a power outage occurs;
An interrupt controller is connected to the power outage detector via a transmission line and sends an interrupt signal to the central processing unit via the bus upon receiving the power outage detection signal, and the central processing unit receives the interrupt signal from the interrupt controller side. A power outage detection/judgment circuit that executes a power outage countermeasure processing routine based on a signal interruption has an input interface through which the output of the power outage detector is guided via a transmission line different from the above, and the input interface is connected to the central processing unit. connected to via a bus and assigned to a predetermined address of the central processing unit,
The central processing unit has a built-in power outage determination program that executes the power outage countermeasure processing routine using the interrupt when the output of the input interface is present, and executes another routine when there is no output. Power outage detection judgment circuit. (2) The power failure detection and determination circuit according to claim 1, wherein the other routine is a routine before the interrupt.