JPS6091415A - Digital controller - Google Patents

Abstract

PURPOSE:To ensure the easy and assured self-diagnosis and to improve the reliability of a digital controller by using a master CPU and a checker CPU for self- diagnosis. CONSTITUTION:A CPU1 supplies the output of a sensor 10 through an input part 7 and a bus conversion part 4 and performs a prescribed control operation. The result of this control operation is delivered to a process via an output part 8 and a switch 9. In this case, the switch 9 is connected to a controller A serving as a primary system. At the same time, the above-mentioned result of operation is sent also to a follower controller B via a coupling device 3. The CPU1 and a CPU16 write data on their operation results to the registers in a monitor 5 respectively. These data are referred to and a fault detection signal is delivered to a double system control logic part 6 when the discordance is detected between both data of the CPU1 and CPU16. In this case, the fault detection signal is delivered by an OR with a double collation signal. The part 6 monitors the working states of both controllers A and B and decides a primary system between them.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital control device that is used to control a digital control system and includes a self-diagnosis function.

[Conventional solo technique]

Typically, in a duplex system, the controller that operates as the main system performs processing such as input processing, control processing, output processing, self-diagnosis processing, and sending tracking data to the slave system. These processes are executed at the required control cycle. Controller malfunctions are detected by the self-diagnosis function of a program run by a microcomputer.

This self-diagnosis function includes a watchdog timer, a memory parity check, a function to detect machine errors, and a check for the occurrence of illegal instructions.

However, depending on the application, various things may be added in consideration of the cost or controller control processing time required to perform, for example, checking the operation of the input/output section or checking the sum of ROM data. Possible, depending on the product.

Conventionally, this barrel device has a dual lettuce configuration as shown in FIG. In the figure, A.

B is a controller that operates as a main system or a slave system.

In controllers A and B, 1 is a central processing unit (cp
u), 2 is expansion memory, 3 is controller A's cp
A coupling device that tracks data between the ui and the cpul of the controller B and connects the controller A and the BY; 4 is a converter that converts the signal level of the paths 4a and 4b; 5 is the respective bus 4a and 4b; A monitor that diagnoses
6 is a controller A for the output of the monitor 5, a switch for switching from Blk main system to slave system or vice versa, 7 is an input section for inputting signals, 8 is an output section for outputting signals, 9 is controller A, B 10 is a sensor for selecting the output of
Reference numeral 11 denotes an actuator that operates based on the signal sent through the switch 9. 14 and 15 are circuits that receive operation commands.

The operation will be briefly explained. When controller A is operating as the main system, when CPU of controller A or monitor 5 is detected to be malfunctioning, an instruction is given to dual system management logic 6 to operate mechanical switch 9, Another movement command? Circuit 14f? c of controller B via
Switching between the main system and the slave system is performed by supplying it to pul.

In response to this, the controller A changes the software processing from the tracking mode in 1 to the control mode and performs process control.

Since the conventional digital control device is configured as 0 or more, most of the failures can be detected by the watchdog timer, memory parity, etc.

Errors occurring in the bus interface section of the CPU, errors in two or more bits of memory, etc. cannot be detected.

In the worst case, this kind of error can cause the CPU to run out of control, so such a digital control device has the drawback of not being sufficiently reliable.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and both the main system and the slave system have the first and second
EPTM, the first CPU serves as a mask, and the second
It works as a cpuld checker and the calculation result of 0 epu is 'a? The purpose is to provide a highly reliable digital control device by combining the following methods.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Second
In the figure, 1 to 15 are the same as in FIG. 1, and 9.
This is EPTM for 18H Teenka.

c p u 1 * 16 , the coupling device 3 and the bus converter 4.

, < By connecting via <4a'ic',
A /-F-processor system is configured. 'J
It has a built-in 2-board memory that can send and receive data for other partial forces by using a bus 4ak valve on the 7t c p ul.

Next, the operation will be explained. The cpul inputs the output of the sensor 10 through the input section 7 and the bus converter 4, and performs the necessary control calculations. The result is usually bus converter 4.
It is output to the process through the output section 8 and the switch 9.

At this time, the switch 9 is connected to the controller A operating as the main system. The cpul arithmetic processing results and intermediate arithmetic results are transmitted as tracking data to the slave controller B through the coupling device 3. The above is the same as the normal duplex operation. The cpul of the main controller A performs the above operations, and at the same time,
Pass the input image to Cpul6's 2-vote memory. This is because the calculations are performed using the same human data in order to compare the calculation results of the two CPUs 16, which will be described later.

The process output is performed from the cpul, and the cpul 16 writes the operation result data to the register in the monitor 5.

The monitor 5 collates this data, and if it does not match, outputs a failure detection signal to the dual system management logic unit 6. At this time, a failure detection signal such as a watchdog timer or a memory parity check is output as a logical sum with the duplex verification signal. Is it true that the results of controller A's CPU 1 * 16 match? Is it always the health of controller A? Checking. At the same time, perform the same check on the slave system to check the health of the slave system. Dual system management logic 6 monitors the operating states of controllers A and B and decides which one to select as the main system. Of course.

The design also allows for manual switching. Furthermore, if a failure occurs in either controller A or B, the switch 9 will not be switched to the opposite position as shown in the illustration, and the actuator 1 will not be switched.
I tried to output an alarm to 1.

The design allows maintenance personnel to be notified and repair work to be carried out.

In addition, in the above embodiment, the data from the master epu to the teekka cp
We have explained the case where the input data is transferred to U and checked, but it is also possible to transfer the data in the opposite direction.It is also applicable to applied products where transient changes in the input data are not a problem (for example, for application products that only have digital input). Even if it is an analog quantity, the response of the system is very slow compared to the sampling time), there is no need to say that the CPU of the mask and checker can be manually processed.

Furthermore, the present invention is not only limited to a dual system but also as a single system.

It can also be applied as a single system for products that do not require urgent response in the event of a failure.

〔Effect of the invention〕

As mentioned above, in this invention, LfL is equipped with two CPUs for self-diagnosis, one for a mask and one for a checker, so that self-diagnosis can be easily and reliably carried out, which has the effect of increasing reliability. be.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional digital control device, Figure 2 is a block diagram of a conventional digital control device.
The figure is a block diagram of a digital control device according to an embodiment of the present invention. 1.16... CPU, 2... Memory, 3... Coupling device. 4... Bus converter, 5... Monitor, 6... Dual system management logic, 7... Input section, 8... Output section, 9...
...Switcher. 10...Sensor, 11...Actuator, A, B
···controller. Note that in FIG. 1, the same reference numerals indicate the same parts. Agent Masuo Oiwa Figure 1

Claims (1)

[Claims] Read the same data from the controlled object at the required intervals. A central processing unit for counting that independently performs the same data processing, and a monitor that inputs and collates the results of data processing by each of the above central processing units, and outputs a failure detection signal when there is a discrepancy. A digital control device equipped with