JPH01103761A - Device for diagnosing trouble of multiple system bus synchronizing system - Google Patents

Abstract

PURPOSE:To detect the trouble of an I/O interface by successively switching a latch circuit in each system with a CPU, a cross-reading is executed per system each time the switching is executed and collating obtained status information and receiving information. CONSTITUTION:When an information input RXD to I/O interfaces 3 and 4 of the respective systems is completed, a signal INT is inputted through a logical sum circuit 11 to CPUs 1 and 2. A latch circuit 5 latches status information STSA from the interface 3 by a command RCH of the CPU 1 and information STSa are read by the CPUs 1 and 2. Next, an instruction is given to a specified address DVA by the switching command RCH and a latch is switched to a B system. Then, information STSb are respectively read. After the information STSb of a latch circuit 6 are returned to the information before inversion, systems A and B collate the STS information of the self-system and other system and receiving information RDT. When the information are not coincident, reception or transmission is repeated in several times. When the information are not coincident even after this repetition, it is decided as the trouble of the interfaces 3 and 4. Thus, the trouble of the I/O interface of the respective systems, which are operated with non-synchronizing, can be detected without fail.

Description

[Detailed Description of the Invention] <Industrial Application> The present invention is characterized by a plurality of CPUs that synchronously perform the same processing on the same input information, and a CPU that is provided for each CPU and operates asynchronously with each other. Regarding a fault diagnosis device for a multi-system bus synchronous system equipped with a plurality of input/output interfaces (hereinafter referred to as I10 interfaces), each system is provided with a latch circuit that latches status information read from the I10 interface, and this latch circuit is provided for each system. As the circuits are sequentially switched, the status information latched by one of the latch circuits is read out by each CPt1 at each switching, and the status information and received data are collated in each CPU to detect a failure of the I10 interface. By diagnosing this, it is possible to detect failures in multiple I10 interfaces that operate asynchronously.

<Conventional technology> For example, in a computer system introduced into a railway signal safety system, etc., one of the techniques to increase the reliability of the system is to use multiple CPUs (computers), so that when one CPU fails, the other Multi-system systems that can perform backup using a CPU are known, and one of them is a multi-system bus synchronous system. This multi-system bus synchronization system compares the output information of multiple CPUs that perform the same processing with each other at the bus level, detects matches and mismatches, and determines whether the system is normal or abnormal. In the event of an abnormality, the control output is set to the safe side. It has a fail-safe configuration. Each CPU is provided with an I10 interface, and when information is transferred between the CPU and input/output devices, an interrupt signal (hereinafter referred to as IN) is sent from the I10 interface.
It is called the T signal. ) is given to each CPU to notify the CPU of completion of preparation for information transfer, completion of reception, etc.

<Problems to be Solved by the Invention> In a multi-system bus synchronous system, when a failure occurs in the I10 interface of the 8 systems, failure detection is necessary. As a means of achieving this, a diagnostic system is developed that assumes that simultaneous failures do not occur in the I10 interfaces of the 8 systems, compares the processing status of each I10 interface, and when the results do not match, determines that one of the I10 interfaces is at fault. Be taken. However, the I10 interface
The I10 interface of the 8 series operates in response to external signals, regardless of the timing, and synchronization is difficult in terms of hardware, so the I10 interface of the 8 series usually operates asynchronously. . For this reason, there is a problem in that the data recognized by the 8-system CPU has a discrepancy in a critical area, and a mismatch occurs in the bus comparison, resulting in a determination that a failure has occurred.

Means for Solving the Problems> In order to solve the problems described above, the present invention provides a system in which a plurality of CPUs synchronously perform the same processing on the same input information.
and a plurality of I10 interfaces that are provided for each CPU and operate asynchronously with each other, in which each system is provided with a latch circuit that latches status information read from the I10 interface; sequentially switching latch circuits, each time reading the status information latched by one of the latch circuits by each of the CPUs;
The present invention is characterized in that a failure of the I10 interface is diagnosed by collating status information and received data in each CPU.

Function> The latch circuits provided for each system are sequentially switched by the CPU, and each CPU reads out the status information for each system latched by one of the latch circuits each time it is switched. This reading method is sash reading,
The status information and received data obtained by this cross-reading are checked in a failure determination section provided inside or outside the CPU. If there is no match even after several times of verification, it is determined that the I10 interface is malfunctioning.

That is, the present invention is based on the premise that simultaneous failures do not occur in the I10 interfaces of 8 systems, and when the processing states of each I10 interface are compared and they do not match,
When using a diagnostic system that determines that one of the devices is at fault, the status information is latched and stabilized, and the stabilized latch information is read by each CPU by cross-reading and compared. , it is possible to easily and reliably detect failures in 8-system I10 interfaces operating asynchronously.

<Embodiment> FIG. 1 shows a block diagram of a multi-system bus synchronization system equipped with a fault diagnosis device according to the present invention. Although this embodiment shows an inter-bus system with two main systems, A system and B system, the number of systems is arbitrary. In the figure, reference numeral 1.2 denotes a CPU provided in each of the A system and B system, which performs the same processing in synchronization while checking at the bus level.

3.4 is an I10 interface provided in each of the A system and B system, which perform the same operation in parallel asynchronously with each other. These I10 interfaces 3.4 are constituted by high level data link integrated circuits (HDLC).

5.6 is a latch circuit provided in each of the A system and B system, which latches the status information STS^ and 5TSa read from the I10 interface 3.4. The latch circuit 5.6 is sequentially switched by a latch switching command RCH given from the CPU 1, for example, and transmits the status information S T S a - S T S b latched by the latch circuit 5 or 6 each time it is switched, to the CPU 1. ,
2, read by sash reading. Inverted status information 5T from latch circuit 6
Sb and received data RDTb are read. this is,
This is to identify a failure in the latch switching command (RCH).

7.8 is buffer y RAM (random acc
essmemory), 9.10 is D M A (d
11 is an OR circuit, 12 is a modem, SDT is transmission data, CNT
is a command.

When the information input RXD to the A-system and B-system I10 interfaces 3.4 is completed, each I10 interface 3.
．． 4 inputs the INT signal to the CPUI and 2 via the OR circuit 11, respectively.

The processing routine is started by inputting the INT signal to the CPU I,2. First, in response to the latch switching command RCH from the CPU, the A-system latch circuit 5 latches the status of the I10 interface 3 and the status information 5TSA read from the register, and the latched status information STS is transmitted by the CPU 2. read out.

Next, the latch switching command RCH switches to the B system output, and the I10 interface 4 is switched from the B system latch circuit to the I10 interface 4.
The status information STSb, which is the latch/invert information of the status information 5TSe read from the register, is read out by the CPUI, 2, respectively. Latch switching from A system to B system is done using a specific address DVA.
This is done by issuing a write command to. Also,
Immediately after reading out the B system, latch switching is performed to return to the A system. During latch switching, latch switching from A system to B system is performed by issuing a write command to a specific address DVA, and when returning from B system to A system, status information is transferred to the hard drive by extracting B system. The received data is returned to the A system in terms of software, and a read command is issued to a specific DVA.

Next, the status information ST read into the CPUI, 2.
S! , 5TSb and received data RDT, ,RD T b
are compared at CPUI,2. That is, C
In PU1, the status STS of own system and 5TS of other system B
b, and also compares the received data RDT of the own system and the received data RDTb of the other system B. The CPU 2 also compares the status information 5TSb of the own system B with the status information STS of the other system A, and also compares the received data RD T b of the own system B with the received data RDT of the other system A. In addition, the status information S T of the latch circuit 6
Since Sb has been inverted, it is returned to the state before being inverted and compared.

If the above comparison results in a match, it is determined that there is no failure and normal data processing begins. In case of discrepancy, I
10 Reset the interface 3.4 and initialize and start receiving or sending several times. If there is still a mismatch, it is determined that the I10 interface 3.4 is malfunctioning, and the system is stopped. Messages that do not match shall be discarded.

For example, as shown in Fig. 2, if the A system and B system are latched at the same time at time t1, and the status flag of the A system is on, the status information 5TSa read into the CPU 1.2 will be at a high level H, for example. Become. Next, t
If the latch is switched from system A to system B at 2 o'clock,
Since the status flag of the B system is not set at time t1, the status information 5TSb is at a low level.

Then, due to the latch at time t4 when the status flag of the B system is set, the status information STSB is high.
Becomes level H. In this state, there is a match and normal processing begins. If the status flag of the B system does not go off even after several repetitions, and no match is found, it is determined that the 10 interface 3.4 has failed, and the system is stopped.

<Effects of the Invention> As described above, the present invention has a plurality of CPUs that synchronously perform the same processing on the same input information, and each CPU
In a multi-system bus synchronous system comprising a plurality of I10 interfaces provided for each system and operating asynchronously with each other, each system is provided with a latch circuit for latching status information read from the I10 interface, and the latch circuit is Switching is performed sequentially based on latch switching information given from the CPU, and status information latched by one of the latch circuits is transferred to the C at each switching.
Since it is characterized in that it is read by all of the PUs and collated with the status information and received data in each CPU to diagnose a failure of the I10 interface, it is possible to easily and reliably diagnose failures of multiple I10 interfaces that operate asynchronously. Accordingly, it is possible to provide a fault diagnosis device for a multi-system bus synchronization system that can detect failures.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multi-system bus synchronization system equipped with a failure diagnosis device according to the present invention, and FIGS. 2(A) to 2(F) are time charts thereof. 1.2...CPU 3.4...I10 interface 5.6...Latch circuit

Claims (2)

[Claims] (1) In a multi-system bus synchronous system that includes multiple CPUs that synchronously perform the same processing on the same input information, and multiple input/output interfaces that are provided for each CPU and operate asynchronously, Each system is provided with a latch circuit that latches the status information read from the input/output interface, the latch circuits are sequentially switched, and each time the latch circuits are switched, the status information latched by one of the latch circuits is transferred to each of the CPUs. 1. A failure diagnosis device for a multi-system bus synchronous system, characterized in that a failure of the input/output interface is diagnosed by reading out the information from the input/output interface and comparing the status information and the received data in each CPU. (2) The failure diagnosis device for a multi-system bus synchronous system as set forth in claim 1, wherein the input/output interface is a high-level data link integrated circuit.