JPH09152995A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the defect of an I/O device, to separate the I/O device from a backboard bus and to prevent the generation of an error output. SOLUTION: When a computer accesses a bus receiver/bus driver 31 in an I/O device IOn through the backboard bus BBS, output data are reread out, and if the reread output data are different from the original output data, the access is interrupted, a CPU part in the computer is informed of the generation of an error in the rereading and the I/O bus receiver/bus driver 31 and the backboard bus BBS are separated by an I/O bus receiver/bus driver I/O switching device 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention detects a defect of the I / O device and backs up the I / O device in a system in which at least one computer and various I / O devices are connected to a backboard bus. The present invention relates to a computer system provided with a function for disconnecting from the board bus.

[0002]

2. Description of the Related Art FIG.
FIG. 3 is a configuration conceptual diagram showing an example of a redundant computer system disclosed in Japanese Patent Publication No. In the figure, BBS is a common backboard bus, and computers FC1 and F having a dual configuration are provided.
C2 and various I / O devices IO1 to IOn are respectively connected. The computers FC1 and FC2 of the redundant configuration are
CPU via CPU sections 11 and 21 and internal bus IBS
The CPUs 11 and 21 are provided with memories 12 and 22 connected to the units 11 and 21, and the CPU units 11 and 21 perform various self-diagnosis, and output an error to the duplex switching control units 13 and 23 when an abnormality is detected. The signal RDY is made inactive.
The duplexing switching control units 13 and 23 use the computers FC1 and F
It is configured such that one of the C2s is used as a main system and is in an operating state, and the other is a slave system and is in a standby state.
When the CPU section accesses the backboard bus BBS, the backboard interfaces 14 and 24 read back the signals (data) on the respective signal lines output to the backboard bus, and compare them to read the signals on the backboard bus. It has a function to check whether the signal can be output correctly. If the read-back results do not match, the access is interrupted and the CPU is notified that this read-back error has occurred.

Next, the operation of the above system will be described. First, it is assumed that both the computers FC1 and FC2 of the redundant configuration are operating normally, the computer FC1 is in control operation (master system), and the computer FC2 is in standby operation (slave system). Next, it is assumed that the backboard interface unit 14 of the computer FC1 fails and a correct signal cannot be transmitted to the backboard bus BBS. In this case, when the computer FC1 attempts to access the I / O device, the read-back function of the interface unit 14 detects an error and interrupts the access. Further, the CPU 11 is notified that a read-back check error has occurred. When the CPU section 11 receives the read-back error signal from the interface section 14, the CPU section 11 sets the self-diagnosis result to not-ready, and performs the access operation,
The control operation is interrupted to prevent erroneous data from being transferred to the I / O device side. C in the duplex switching control unit 13
When the ready signal from the PU unit 11 becomes inactive, a duplication control signal for transferring the control right to the computer FC2 side is output. As a result, the computer FC2, which has been on standby until then, starts the control operation, and the function as the system continues.

[0004]

In the above-mentioned conventional computer system, failure detection of bus drivers and bus receivers of various I / O devices is not performed, and all I / O devices due to buffer failures of I / O devices are not detected. There was a problem that the O device was down and there was a possibility of incorrect output.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to detect a defect in an I / O device, disconnect the I / O device from the backboard bus, and output an error. It is an object of the present invention to provide a computer system capable of preventing the above.

[0006]

According to a first aspect of the present invention, there is provided a computer system in which a common backboard bus has a CPU.
In a case where a computer having a section and various I / O devices are connected, when the computer accesses the I / O bus receiver / bus driver of each I / O device via the backboard bus, O The bus receiver / bus driver reads back the output data output on the backboard bus and if the two do not match, the access is interrupted and the CPU is notified that an error has occurred in this read back I / O
It controls the I / O bus receiver / bus driver input / output switching unit of the device. The I / O bus receiver / bus driver input / output switching unit disconnects the I / O bus receiver / bus driver and the backboard bus when receiving a read error. As a result, all the I / O devices due to defective I / O devices
It is possible to prevent the down of the / O device.

According to a second aspect of the present invention, an I / O bus receiver /
When the bus driver input / output switching unit receives a read-back error, it performs a 3-state OC switching to electrically disconnect the connection between the backboard bus and the I / O receiver / driver to disconnect the I / O device from the system. As a result, it is possible to prevent all I / O devices from going down due to defective I / O devices.

According to the third aspect of the invention, an I / O bus receiver /
When the bus driver input / output switching unit receives a read-back error, the output or input of the I / O bus receiver / bus driver for the backboard bus is disconnected by switching the direction. As a result, it is possible to prevent all I / O devices from going down due to defective I / O devices.

According to a fourth aspect of the present invention, the same value is written from a computer to two registers equipped in the I / O device, and they are compared by a comparison circuit. If the two values do not match, the I / O bus receiver / bus driver input / output switching device is notified that an error has occurred, and the input / output of the I / O bus driver / bus receiver is controlled. Claim 1
By adding to the inventions of 3 to 3, it is possible to monitor the defects in both the CPU unit and the I / O device of the computer.

According to a fifth aspect of the present invention, a certain value and its inverted value are written from a computer to two registers equipped in the I / O device, and the value obtained by NOTing the inverted value and the original value are compared by a comparison circuit. . By using the inverted value, it is possible to avoid a failure in the case where there is a problem of transmitting only a fixed value on the bus. If the two values do not match, the I / O bus receiver / bus driver input / output switching device is notified that an error has occurred, and the input / output of the I / O bus driver / bus receiver is controlled.

According to a sixth aspect of the present invention, certain values are written from a computer to one register equipped in the I / O device at a constant cycle, and a comparison circuit determines whether those values are the same value within a certain time. judge. If the two values do not match, the I / O bus receiver / bus driver input / output switching device is notified that an error has occurred, and the input / output of the I / O bus driver / bus receiver is controlled. Compared with the invention of claim 4, there is an advantage that only one register is required.

According to a seventh aspect of the present invention, a certain value and its inverted value are alternately written from a computer to one register equipped in the I / O device in a constant cycle, and those values are the same within a constant time. Whether or not it is determined by the comparison circuit. By using the inverted value, it is possible to avoid a failure in the case where there is a problem of transmitting only a fixed value on the bus. If an error due to a value mismatch occurs, it is notified to the I / O bus receiver / bus driver input / output switching device to control the input / output of the I / O bus driver / bus receiver. Compared with the invention of claim 5, there is an advantage that only one register is required.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, Embodiment 1 of the present invention will be described with reference to FIG. In FIG. 1, backboard bus B
The I / O device IOn connected to the BS switches between the I / O bus receiver / bus driver 31 for transmitting / receiving data from the backboard bus BBS and the data input / output of the I / O bus receiver / bus driver 31. I / O to control
A bus receiver / bus driver input / output switching device 32 and a register determination device 33 are provided. And the above I
The / O receiver / driver 31 has a function of reading back the signal (data) on the output signal line when the CPU unit (not shown) of the computer accesses the I / O device IOn via the backboard bus BBS. There is. Further, the signal 34 is the I / O receiver / driver input / output switching device 32.
The signal 35 is a signal sent from the CPU unit for operating the CPU, and the signal 35 is a start signal from the CPU unit for causing the I / O device to execute the register determination. The computer connected to the backboard bus BBS has the same configuration as the redundant computers FC1 and FC2 shown in FIG. Further, the activation signal 35 from the register determination device 33 and the CPU unit is not used in the first embodiment (used in the third and subsequent embodiments).

Next, the operation of the first embodiment will be described. It is assumed that the duplicated computers FC1 and FC2 are those that have been used conventionally, and that internal faults of the bus interface section inside the computer can be detected. The present invention provides I / O when the redundant computer is operating normally.
It detects the failure of the bus driver and bus receiver of the device. Now, assume a failure in which the I / O bus receiver / bus driver 31 of the I / O device IOn fails and cannot transmit a correct signal. At this time, computer F
When C1 attempts to access the I / O device, an error is detected by the read-back function of the interface unit 31 and the access is interrupted, and the CPU unit 11 is notified that a read-back error has occurred. After the error is detected, the signal 34 from the CPU unit 11 is sent to the I / O receiver / driver input / output switching device 32, and the OC switching causes the backboard bus BBS and the I / O device IOn to be electrically cut off to input data. Stop output. As a result, it is possible to prevent all I / O devices from going down due to a defect in one I / O device IOn.

Embodiment 2 Next, a second embodiment of the invention will be described with reference to FIG. The configuration of the IOn of the I / O device is similar to that of the first embodiment, and its operation will be described. Now, assume a failure in which the I / O bus driver / bus receiver 31 of the I / O device IOn fails and cannot transmit a correct signal. Similar to the first embodiment, the read-back function of the interface unit 31 causes the I / O bus receiver / bus driver input / output switching device 32.
Is informed that an error has occurred. Here, in the first embodiment, the backboard bus BBS and the I / O device IOn are separated by OC switching in the I / O bus receiver / bus driver input / output switching device 32, but in the second embodiment, Either the input or the output is cut off by the Direction switching function of the I / O bus receiver / bus driver input / output switching device 32. The selection for shutting off either the input or the output is comprehensively judged by the CPU section of the computer, and the I / O receiver / driver input / output switching device 32 is instructed by the signal 34. According to the second embodiment, one I / O device can be dealt with more flexibly in response to a defect of the I / O device.
It is possible to prevent all I / O devices from going down due to one of the I / O device failures.

Embodiment 3 Third Embodiment A third embodiment of the present invention will be described with reference to FIG. In the figure, the I / O bus receiver / bus driver input / output switching device 32 and the register determination device 33 are on the I / O device IOn, and two registers 41 and 42 and a comparison circuit 43 are included in the register determination device 33. .

Next, the operation of the third embodiment will be described. It is assumed that the redundant computers FC1 and FC2 have the same structure as that described above and can detect the internal failure of the bus interface section inside the computer. In the third embodiment, when the redundant computer is operating normally, a failure of the bus driver or bus receiver of the I / O device is also detected in the I / O device to prevent erroneous output. . Now, I / O bus driver of I / O device IOn /
It is assumed that the bus receiver 31 fails and cannot transmit a correct signal. In the third embodiment, as shown in FIG. 3, first, the same value is written from the CPU section 11 to the registers 41 and 42, and those values are compared by the comparison circuit 43. If the compared results are the same, an EQUAL signal is output, and if the compared results do not match, an error output is transmitted to the I / O bus receiver / bus driver input / output switching device 32. When the error output is transmitted, the I / O bus receiver / bus driver input / output switching device 32 causes the OC
The backboard bus BBS and the I / O device IOn are disconnected by switching or direction switching to prevent erroneous output of the I / O device IOn. That is, by adding the third embodiment to the first or second embodiment of the present invention, it is possible to monitor the defect of the I / O device in both the CPU section and the I / O device of the computer.

Embodiment 4 Embodiment 4 of the present invention will be described with reference to FIG. In the figure, the configurations of the register determination device 33 and the I / O bus receiver / bus driver input / output switching device 32 are similar to those of the third embodiment. Now, assume a failure in which the I / O bus driver / bus receiver 31 of the I / O device IOn fails and cannot transmit a correct signal. In the third embodiment, as shown in FIG. 3, first, the value (A) stored in the register 41 from the CPU unit 11 is first stored.
Is written, and the inverted value (A bar) of that value is written in the register 42. Next, NOT of the value of the register 42
Then, the comparison circuit 43 compares the two values. If the compared results are the same, it is output as an EQUAL signal,
If the comparison result does not match, an error output is transmitted to the I / O bus receiver / bus driver input / output switching device 32.
When the error output is transmitted, the I / O bus receiver / bus driver input / output switching device 32 causes the backboard bus BBS and the I / O bus switching by the OC switching or the direction switching.
The I / O device IOn is disconnected to prevent erroneous output of the I / O device IOn. In the case where a defect that the same value is always written in the register occurs, the defect cannot be detected in the third embodiment, but in the fourth embodiment, the inverted data can be dealt with to cope with such a defect. Is used.

Embodiment 5 The fifth embodiment of the present invention will be described with reference to FIG. In the figure, the I / O bus receiver / bus driver input / output switching device 32 and the register determination device 33 are on the I / O device IOn, and one register 41 and one comparison circuit 43 are included in the register determination device 33.

Next, the operation of the fifth embodiment will be described. Now, assume a failure in which the I / O bus driver / bus receiver 31 of the I / O device IOn fails and cannot transmit a correct signal. First, the value A stored in the register 41 is written from the CPU section 11 in a fixed cycle, and the comparison circuit 43 determines whether the written values are the same within a fixed time. If the compared results are the same, an EQUAL signal is output, and if the compared results do not match, an error output is transmitted to the I / O bus receiver / bus driver input / output switching device 32. When the error output is transmitted, the I / O bus receiver / bus driver input / output switching device 32 causes the OC
The backboard bus BBS and the I / O device IOn are disconnected by switching or direction switching to prevent erroneous output of the I / O device IOn. According to the fifth embodiment,
Compared with the third embodiment, there is an advantage that only one register is required.

Embodiment 6 Embodiment 6 of the invention will be described with reference to FIG. In the figure, the configurations of the register determination device 33 and the I / O bus receiver / bus driver input / output switching device 32 are the same as those in the fifth embodiment. Now, assume a failure in which the I / O bus driver / bus receiver 31 of the I / O device IOn fails and cannot transmit a correct signal. In the sixth embodiment, as shown in FIG. 6, the value (A) in the register 41 and the inverted value (A bar) of the value are alternately written from the CPU unit 11 in a constant cycle, and the written value (A) and The comparison circuit 43 determines whether the NOT value of (A bar) is the same within a fixed time. If the compared results are the same, an EQUAL signal is output, and if the compared results do not match, the I / O bus receiver /
The error output is transmitted to the bus driver input / output switching device 32. When the error output is transmitted, the I / O bus receiver / bus driver input / output switching device 32 causes the backboard bus BB by OC switching or direction switching.
The S and the I / O device IOn are separated to prevent erroneous output of the I / O device IOn. According to the sixth embodiment, it is possible to deal with the case where a defect that the same value is always written in the register occurs, and there is an advantage that the number of registers is one as compared with the invention of the fourth embodiment. is there.

Other Embodiments In the above-described embodiment, the system having the redundant computers FC1 and FC2 has been described as a premise, but the same operation and effect can be obtained even if the number of computers is one or more.

[0023]

As described above, according to the present invention, I / O
It is possible to provide a computer system capable of disconnecting an I / O device from a backboard bus in the event of a device bus driver or bus receiver failure, and to provide all I / O devices due to a defective I / O device.
It is possible to prevent the O device from going down.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an I / O device according to a first embodiment of the present invention.

FIG. 2 is a configuration block diagram of an I / O device according to a second embodiment.

FIG. 3 is a configuration block diagram of a register determination device and an I / O bus receiver / bus driver input / output switching device in an I / O device according to a third embodiment.

FIG. 4 is a configuration block diagram of a register determination device and an I / O bus receiver / bus driver input / output switching device in an I / O device according to a fourth embodiment.

FIG. 5 is a configuration block diagram of a register determination device and an I / O bus receiver / bus driver input / output switching device in an I / O device according to a fifth embodiment.

FIG. 6 is a configuration block diagram of a register determination device and an I / O bus receiver / bus driver input / output switching device in an I / O device according to a sixth embodiment.

FIG. 7 is a configuration block diagram showing an example of a redundant computer system.

[Explanation of symbols]

BBS backboard bus, IO1 to IOn I / O devices, FC1, FC2 computers, 11, 21 CPU section, 1
2,22 memory, 13,23 redundant switching control unit, 1
4,24 Backboard bus interface, 31
I / O bus driver / bus receiver, 32 I / O bus receiver / bus driver input / output switching device, 33 register determination device, 34 I / O device disconnection signal, 35
Register determination start signal, 41, 42 register, 43
Register comparison circuit.

Claims (7)

[Claims] 1. In a computer system in which a computer having a CPU section and various I / O devices are connected to a common backboard bus, the I / O device transmits and receives data from the backboard bus. An I / O bus receiver / bus driver and a switching means for switching and controlling data input / output of the I / O bus receiver / bus driver are provided, and the I / O bus receiver / bus driver is provided from the computer to the backboard. The output data received via the bus is read back, and it is detected whether the read-back data and the output data match. If the two data do not match, the CPU section causes the I / O
I / O to O bus receiver / bus driver input / output switching means
A computer system characterized by commanding disconnection control between a bus receiver / bus driver and a backboard bus. 2. The I / O bus receiver / bus driver input / output switching means disables the buffer of each I / O device from the CPU section by OC switching when a defect in the I / O device is detected. I have a function, I /
2. The computer system according to claim 1, wherein the O device is separated from the backboard bus. 3. The I / O bus receiver / bus driver input / output switching means disables the buffer of each I / O device from the CPU section by switching the direction when a defect in the I / O device is detected. 2. The computer system according to claim 1, wherein the computer system is provided with a function and the I / O device is disconnected from the backboard bus. 4. The I / O device is provided with two registers and a comparison circuit, the same data value output from a computer is written to both the registers, and the comparison circuit compares the defective data of the I / O device. 4. The computer system according to claim 1, wherein the computer system detects the occurrence of an error and sends an error occurrence to the I / O bus receiver / bus driver input / output switching device. 5. The I / O device is provided with two registers and a comparison circuit, the data value output from the computer is written in one register, and the inverted value of the data value is written in the other register. By comparing the values of both with a comparison circuit, a defect of the I / O device is detected, and the above I / O device is detected.
An error occurrence is transmitted to a bus receiver / bus driver input / output switching device.
The computer system according to any one of 1. 6. The I / O device is provided with one register and a comparison circuit, and a data value output from a computer is written in the register at regular intervals to check whether the same data value is written within a certain time. Defective I / O devices are detected by the comparison circuit, and the I / O bus receiver /
4. The computer system according to claim 1, wherein an error occurrence is transmitted to the bus driver input / output switching device. 7. The I / O device is provided with one register and a comparison circuit, and a data value output from a computer is written in the register at a constant cycle, and a data value within a certain time and its inverted value are alternated. The comparison circuit determines whether or not the data has been written to detect a defect in the I / O device, and
The computer system according to any one of claims 1 to 3, wherein an error occurrence is transmitted to an O bus receiver / bus driver input / output switching device.