JPH0726762Y2 - Bus mismatch circuit - Google Patents

Description

[Detailed description of the device] "Industrial application field" The present invention is a CP that works in accordance with a common program.
The present invention relates to a bus disagreement generation circuit for causing a disagreement for testing when a U is provided in a control unit, a bus is extended from each CPU, and a coincidence of each bus is monitored to determine an abnormality.

"Prior art" In order for a vehicle to operate safely on a track that includes traffic lights and trollers, a certain order and restrictions are placed on the control and operation of these traffic lights and trollers. There is an electronic interlocking device as a device for this.

In order to ensure reliability and fail-safety, the interlocking device has a pair of CPUs in the control unit that operate with a common program, monitors these CPUs, and confirms that they are operating normally. It is judged that the outputs match, and if they do not match, it is judged that an abnormality has occurred.

Furthermore, in order to determine whether or not the monitoring itself is normally performed, a bus inconsistency is intentionally generated in each CPU, and whether or not the inconsistency is determined to be abnormal determines whether the control unit is operating normally. I will check.

Conventionally, when a bus mismatch occurs, 0 or 1 is set in hardware for each designated port, and if necessary, input to that port to cause a mismatch, or a watchdog timer relay with soft output is used. I made it and stopped the output to this, and as a result, made the disagreement operation.

"Problems to be solved by the invention" However, in such a conventional way of generating a bus mismatch, in the case of setting by hardware, when a fixed failure occurs in the hardware element, the bus mismatch does not occur, Since it is not clear whether the cause is the hard element or not, it is difficult to find the cause and it is impossible to secure the fail-safe property.

Further, the soft output requires a program process, and thus the watchdog timer relay cannot be operated promptly, and there is a problem that it takes a long time for detection.

The present invention has been made by paying attention to such problems in the conventional technology, and it is possible to quickly generate a bus mismatch and to easily detect a failure of the circuit itself. The purpose is to provide a mismatch generation circuit.

[Means for Solving the Problem] The gist of the present invention for achieving such an object is to provide a pair of CPUs in a control unit so that they operate under a common program, and extend a bus from each CPU. A bus mismatch generation circuit for causing a mismatch for testing by checking the match of each bus and judging an abnormality, wherein the information of different bits of the signal of one of the buses is different from each other. A first flip-flop and a second flip-flop each having a clock input port for inputting and starting a test signal, an output of the first flip-flop and a test start signal are input, and one of the buses A first AND gate that outputs the result to the second flip-flop, and a second start gate that outputs the result to the other of the buses. It consists in bus mismatch generating circuit, characterized in that a gate.

"Action" The CPUs of each pair are constantly monitored for the matching of buses extending from each other, and normal operation is guaranteed.

To test for proper monitoring, a bus mismatch is deliberately generated.

For example, when 1 is sent to the signal of one of the buses, 1 can be input to the first flip-flop and 0 can be input to the second flip-flop. When the creation start signal is input to the clock input port for starting the test signal creation, 1,0 is input to the first flip-flop and the second flip-flop.

The output of the first flip-flop is 1, which is input to the first AND gate, and the output of the second flip-flop is 0, which is input to the second AND gate. Therefore, the inputs of the first and second AND gates are different.

Therefore, when the test start signal 1 is input to the first AND gate and the second AND gate, the output of the first AND gate is 1 and the output of the second AND gate is 0.
Since this output is output to each bus of the paired CPUs, a bus mismatch occurs.

When 2 is sent to the signal of the one bus, 0 can be input to the first flip-flop and 1 can be input to the second flip-flop, so that a bus mismatch similarly occurs.

For example, if 0 is sent to the signal of one of the buses, 0 can be input to the first flip-flop and 0 can be input to the second flip-flop. By inputting the creation start signal to the clock input port for starting the test signal creation, 0,0 is input to the first flip-flop and the second flip-flop.

The outputs of the first flip-flop and the second flip-flop are 0, and are input to the first AND gate and the second AND gate, respectively. Therefore, the inputs of the first and second AND gates are the same.

When the test start signal 1 is input to the first AND gate and the second AND gate, both outputs of the first and second AND gates become 0, and the bus mismatch does not occur.

When 3 is sent to the signal of the one bus, 1 can be input to both the first flip-flop and the second flip-flop, and both the outputs of the first AND gate and the second AND gate are output. Similarly, at 1, no bus mismatch occurs.

As described above, when the outputs of the first AND gate and the second AND gate according to the inputs to the first flip-flop and the second flip-flop are clear and there is a response other than that. Can be determined as a hardware failure of the bus mismatch generating circuit itself.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the control unit 10 of the electronic interlocking device has a pair of one-chip CPU1 and CPU2, and each CPU1 and CPU2 is set to perform the same operation by the same program.

A monitoring unit 11, an I / O means 12 and a bus mismatch generation circuit 20 are attached to the CPU1 and CPU2.

The I / O means 12 mediates the exchange of signals between the CPU1 and CPU2 and a device control terminal (not shown) or a control panel.
U1 and CPU2 1-system bus 15 and 2 system bus 16 for transmission and a bus for receiving information from equipment control terminals, etc.
17 connected.

The bus mismatch generation circuit 20 is composed of a first flip-flop 21 and a second flip-flop 22, and a first AND gate 25 and a second AND gate 26.

The first flip-flop 21 has an input port, a clock input port C for starting the test signal generation from the monitoring unit 11, an output port and a reset port R. The OB (bit) information of the signal of the 1-system bus 15, which is one of the 1-system bus 15 and the 2-system bus 16, is connected to the input port so as to be input.

Similarly, the second flip-flop 22 has an input port, a clock input port CC for starting the test signal creation, an output port and a reset port R, and is a 1-system bus for transmission.
1B information of 15 signals is connected to input.

The first AND gate 25 has a first flip-flop 21
Output and test start signal are input, and the 1-system bus 1 for transmission
One of the 5, 2 system buses 16 is connected to the 1 system bus 15 to output the result.

The second AND gate 26 has a second flip-flop 22
Output and test start signal are input, and 1-system bus for each transmission
It is connected to the other 2nd system bus 16 of the 15,2nd system bus 16 so as to output the result.

Next, the operation will be described.

The paired CPU1 and CPU2 are constantly monitored by the monitoring unit 11 for coincidence of the sending 1-system bus 15 and the 2-system bus 16 extending from each other through the I / O means 12, and normal operation is guaranteed. .

In the device control terminal or the like, control processing is performed by the matched signals of the 1st system bus 15 and the 2nd system bus 16 for transmission. Further, the states of the device control terminal and the like are input from the I / O means 12 to the CPU1 and CPU2 through the receiving bus 17.

In order to test whether or not the monitoring section 11 is properly monitoring, a mismatch between the sending 1-system bus 15 and the sending 2-system bus 16 is intentionally generated. The reset port R of each of the first flip-flop 21 and the second flip-flop 22 is input at the time of rising or when an abnormality occurs to set an initial state.

1-system bus which is one of 1-system bus 15 and 2-system bus 16 for each transmission
When 2 is sent to the signal of 15, the first flip-flop 21
0 is input to the second flip-flop 22, and 1 can be input to the second flip-flop 22.

2 and 3 are signal timing diagrams, in which the wavy line indicates that the signal on the bus is changing, and the signal changing to either 1 or 0 continues. It means that It is a convenient representation to show that the circuit is operating. Further, although there is a description such as "0" output, this indicates that both the flip-flops output 0 and the bus output becomes 0. Similarly,
The "3" output has a bus output of 1 and a flip-flop of 1,0
The output of the bus becomes 1, and the outputs of "1" and "2" indicate that the flip-flops are 1,0 or 0,1 and do not match.

Input ON and input OFF refer to the input of 1 to the common input line of the first and second AND gates 25 and 26 in FIG. 1 and the input of 0 to OFF. is there.

As shown in FIG. 3, when the creation start signal is input to the clock input port C for starting the test signal creation, 0, 1 is input to the first flip-flop 21 and the second flip-flop 22.

The output of the first flip-flop 21 is 0, which is input to the first AND gate 25, and the output of the second flip-flop 22 is 1, which is input to the second AND gate 26. .

Therefore, the first AND gate 25 and the second AND gate 26
When the test start signal 1 is input to and, since the inputs to the first AND gate 25 and the second AND gate 26 from the first flip-flop 21 and the second flip-flop 22 are different, The output of the AND gate 25 is 0 and the output of the second AND gate 26 is 1.

The output 0 of the first AND gate 25 is output to the 1-system bus 15 which is one of the buses of the CPU1 and CPU2 forming a pair, and the output 1 of the second AND gate 26 is the 2-system bus 16 for transmission which forms a pair. Therefore, there is a mismatch between the first system bus 15 and the second system bus 16 for transmission.

If 1 is sent to the signal of the 1-system bus 15 for sending at the start of the test, 1 can be input to the first flip-flop 21 and 0 can be input to the second flip-flop 22. Therefore, similarly, a mismatch occurs between the 1st system bus 15 and the 2nd system bus 16 for transmission.

In this case, contrary to the above, 1 is output to the 1-system bus 15 and 0 is output to the 2-system bus 16.

When 0 is sent to the signal of the 1-system bus 15 for sending one, 0 can be input to the first flip-flop 21 and 0 can be input to the second flip-flop 22 as well. By inputting the creation start signal to the clock input port C of 0, 0,0 is input to the first flip-flop 21 and the second flip-flop 22.

The outputs of the first flip-flop 21 and the second flip-flop 22 are 0, and they are the first AND gates, respectively.
25 and the second AND gate 26.

As shown in FIG. 2, when the test start signal 0 is input to the first AND gate 25 and the second AND gate 26, the first flip-flops to the first AND gate 25 and the second AND gate 26 are input. The inputs from the flip-flop 21 and the second flip-flop 22 are both 0, and the outputs of the first AND gate 25 and the second AND gate 26 are both 0,
No mismatch occurs between the 1st system bus 15 and the 2nd system bus 16 for transmission.

When 3 is sent to the signal of the 1st system bus 15 for sending one, the first flip-flop 21 and the second flip-flop
1 can be input to both 22, and the outputs of the first AND gate 25 and the second AND gate 26 are both 1 and similarly, a mismatch between the 1-system bus 15 and the 2-system bus 16 for transmission occurs. do not do.

The first AND gate 25 and the second AND gate 25 corresponding to the inputs to the first flip-flop 21 and the second flip-flop 22, respectively.
If the output of the AND gate 26 is clear and there is a response other than that, it can be determined as a hardware failure of the bus mismatch generation circuit 20 itself. That is, not only can the failure be determined in the case of bus mismatch and the case of bus match, but also in the same configuration, a hardware failure can be determined.

"Effect of device" According to the bus mismatch generating circuit of the present invention, it is possible to easily and quickly generate the bus mismatch by specifying the signal of the bus that sends the signal to the control device terminal.
It is possible to reliably check that the monitoring means is operating normally. Further, since the relationship between the input and the output to the circuit is limited to a specific one, it is possible to easily detect the hardware failure of the circuit itself in addition to the bus matching and non-matching, and it becomes a highly reliable bus mismatch generating circuit. .

[Brief description of drawings]

Each drawing shows an embodiment of the present invention. FIG. 1 is a block diagram of an electronic interlocking device provided with a bus mismatch generating circuit, and FIG. 2 is a signal timing diagram in the case of bus matching.
The figure is a signal timing diagram in the case of bus mismatch. 10 …… Control unit, 11 …… Monitoring unit 12 …… I / O means, 15 …… 1 system bus 16 …… 2 system bus, 17 …… Accepting bus 20 …… Bus mismatch generation circuit 21 …… No. 1st flip-flop 22 ... 2nd flip-flop 25 ... 1st AND gate 26 ... 2nd AND gate

Claims (1)

[Scope of utility model registration request] 1. Pairs to operate with a common program
CPU is provided in the control unit, and the bus is extended from each CPU,
A bus discrepancy generation circuit for causing a discrepancy for a test to monitor the coincidence of each bus and judge an abnormality, wherein information of different bits of a signal of one bus of each bus is separately A first flip-flop and a second flip-flop each having a clock input port for inputting and starting a test signal, an output of the first flip-flop and a test start signal are input, and one of the buses A first AND gate for outputting the result to the other, and a second AND gate for receiving the output of the second flip-flop and the test start signal and outputting the result to the other of the buses. Characteristic bus inconsistency generation circuit.