JPH03222020A - Reset system for multi-micro processor system - Google Patents

Abstract

PURPOSE:To eliminate a wasteful processing time by permitting a selected micro processor to control the resetting of the other micro processor when the abnormality of the other micro processor is detected. CONSTITUTION:When a program runaway occurs in the micro processor 12 and a watch dog timer (WDT) 15 diagnoses abnormality, the output of abnormality diagnosis is given to a reset control circuit 17. Information on the presence of abnormality is given to the micro processor 11 by the operation of the circuit 17. The processor 11 always supervises the state of the processor 12. When the presence of abnormality is recognized, it is judged which method is optimum for systematically operating the micro processor with abnormality. A reset signal is outputted to the reset circuit 17 based on the judgement result and resetting as against the processor 12 is controlled.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a multi-microprocessor in which a plurality of microprocessors are electrically coupled to exchange data between each microprocessor. Regarding the reset method.

(Prior Art) In FIG. 4, a first microprocessor 1 and a second microprocessor 2 are electrically coupled by a path line 3, and form a so-called multi-microprocessor system in which they exchange data with each other. is building.

1st. Each second microprocessor 1.2 is provided with a watchdog timer (hereinafter abbreviated as VDT) 4.5 as an abnormality diagnostic circuit for detecting an abnormal loop or runaway of the program. The output signals of each are input to the corresponding microprocessor 1.2 via a gate circuit 6.7.

On the other hand, a reset detection circuit 10 detects the on operation of the power switch 8 or the on operation of the reset switch 9 of the system and generates a reset signal.
1st through 7. each connected to a second microprocessor 1.2.

When the reset detection circuit 1o detects the ON operation of the power switch 8 or the ON operation of the reset switch 9 and outputs a reset signal, this reset signal is transmitted to the first and second gates via the gate circuit 6.7. 2 microprocessors 1.2 respectively; Both the second microprocessors 1 and 2 are reset. For example, if a program runs out of control in the first microprocessor 1 due to a defective hardware component, noise, or a software bug, the program runaway can be prevented by the WD.
T4 is detected and an abnormality diagnosis signal is input to the first microprocessor 1 via the gate circuit 6, and the first microprocessor 1 is reset. After the reset is released, only this first microprocessor 1 performs an initial startup operation, and the system continues to operate normally despite its appearance. The same applies when a program runaway occurs in the second microprocessor 2. When an abnormality is diagnosed by the WDT 5, the second microprocessor 2 is reset, and after the reset is released, only this second microprocessor 2 is initially activated. An action is taken.

Therefore, even if a program runaway occurs in one microprocessor and that microprocessor is in the process of being reset or in the initial startup operation after the reset is released, the other microprocessor will be aware of the situation and will continue to operate as usual. Trying to exchange data with the other side. In this case, since there is no response from the partner system that has become abnormal, the connection attempt is repeated several times and an error occurs, resulting in the inconvenience that various operations are stopped during this retry time and timeout time.

(Problem to be Solved by the Invention) In this way, in the conventional technology, abnormalities in other microprocessors cannot be detected, which causes problems in data exchange between microprocessors, resulting in wasted processing time. was occurring.

The present invention was made based on the above circumstances, and its purpose is to provide a multiprocessor that can reliably recognize abnormalities in other microprocessors and control the reset of abnormal microprocessors while eliminating wasted processing time. It attempts to provide a reset method for microprocessor systems.

(Means and Effects for Solving the Problems) In order to solve the above problems and achieve the purpose, the present invention selects any one of the microprocessors, and selects the selected microprocessor. inputs the output signal of the abnormality diagnosis circuit of another microprocessor, determines whether the other microprocessor is abnormal based on this input signal, and controls the reset of the abnormal microprocessor when an abnormality is detected. It is something.

The selected microprocessor inputs the system reset signal and the output signal of its own abnormality diagnosis circuit, and when reset is applied by the system reset signal, controls the reset of all other microprocessors, When a reset is applied by the output signal of its own abnormality diagnosis circuit, it is desirable that only the reset is controlled by itself.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

In FIG. 1, a first microprocessor 11 and a second
It is electrically connected to the microprocessor 12 by a pass line 13, and exchanges data with each other.
We are building a so-called multi-microprocessor system. 1st. The second microprocessors 11 and 12 are each provided with a VDT (watch dog timer) 14 and 15 as an abnormality diagnostic circuit for detecting an abnormal program loop or S run. And WDT1
The output signal of WDT 15 is also input to the first microprocessor 11 via the reset control circuit 17. The reset control circuit 17 is under the control of the first microprocessor 11, and has the function of taking in the output signal from the WDT 15 and providing it to the first microprocessor 11, and the function of receiving the output signal from the WDT 15 and providing it to the first microprocessor 11. It has a function of sending a reset signal to the second microprocessor 12.

On the other hand, a reset detection circuit 20 is connected to the first microprocessor 11 via the gate circuit 16 and generates a reset signal by detecting an on operation of the power switch 18 or a reset switch 19 of the system. There is.

FIG. 2 is a block diagram showing the main components of the first microprocessor 11 and its peripheral circuits related to the present invention. The microprocessor 11 includes a CPU (Central Processing Unit) 21 serving as a main body of the control unit, a memory unit 22 for storing program data, etc., and data transmission/reception between the second microprocessor 12 and the other second microprocessor 12 via a pass line 13. In addition to the transmission controller 23 etc. that controls the
status port 24, second status port 25
and the respective output ports of the command latch port 26 are connected via an internal bus 27.

An abnormality signal processing section 28 of the reset control circuit 17 is connected to the first status port 24 . This abnormal signal processing section 28 takes in the output signal from the WDT 15 of the second microprocessor 12, performs predetermined signal processing, and supplies it to the first microprocessor 11.

Two reset generation circuits that generate a reset signal in response to a reset signal from the reset detection circuit 20 and an abnormality diagnosis output from the WDT 14 are input to the second status port 25 via a gate circuit 30. It has become.

The command latch port 26 is for sending a reset signal to the second microprocessor 12, and is connected to the reset control circuit 31 via the gate circuit 31.
It is connected to the reset signal processing section 32 of. Note that this port 26 is reset by a reset signal from the reset detection circuit 20. On the other hand, a reset signal from the reset detection circuit 20 is also applied to the 'reset signal processing section 32 via a gate circuit 31. The reset signal processing section 32 performs predetermined signal processing on the reset signal taken in through the gate circuit 31 to reset the second microprocessor 12 .

In this embodiment configured in this manner, when a reset signal is output from the reset detection circuit 20 in response to an ON operation of the power switch 18 or an ON operation of one reset switch, this reset signal is outputted via the gate circuit 16. and is input to the first microprocessor 11. 1st
In the microprocessor 11, when the reset signal from the reset detection circuit 20 is applied to the status port 25 via the gate circuit 30, the CPU 21 detects this and performs a reset.

Further, the reset signal from the reset detection circuit 20 is given to the reset signal processing section 32 of the reset control circuit 17 via the gate circuit 31. As a result, the second microprocessor 12 is also reset.

Furthermore, when a program runaway or the like occurs in the first microprocessor 11 and an abnormality diagnosis is made by the WDT 14, the reset generation circuit 2 responds to this abnormality diagnosis output.
A reset signal is generated at 9, and this reset signal is sent to the status port 2 via the gate circuit 30 in the same manner as above.
given to 5. Therefore, the first microprocessor 1
1 will require a reset.

On the other hand, if a program runaway or the like occurs in the second microprocessor 12 and an abnormality diagnosis is made by the WDT 15, this abnormality diagnosis output is sent to the reset control circuit 1.
The signal is given to the abnormal signal processing unit 28 of No. 7. Then, by the action of the abnormality signal processing unit 28, information indicating that an abnormality has occurred is given to the status port 24 of the first microprocessor 11. CPU21 is status port 24
The state of the second microprocessor 12 is constantly monitored via the microprocessor 12, and when it is recognized that an abnormality has occurred, it is determined how best to operate the abnormal microprocessor 12 system-wise. Then, based on the determination result, a reset signal is output from the command latch port 26 to the reset signal processing section 32 of the reset control circuit 17, and the reset to the second microprocessor 12 is controlled. That is, in the case of a redundant system in which the functions of the second microprocessor 12 are backed up by another microprocessor, or in the case of repeated restarts due to abnormality several times in succession, the reset signal is not used. is continuously output to stop the operation of the second microprocessor 12. In addition, if the system function is not backed up and abnormalities do not occur continuously, a reset signal is output for a certain period of time and the second
The microprocessor 12 of the computer is restarted.

As described above, according to this embodiment, the first microprocessor 11 constantly monitors the operating status of the second microprocessor 12, and when an abnormality occurs in the second microprocessor 12, the system takes appropriate action accordingly. Since the reset of the second microprocessor 12 can be controlled, abnormal data exchange between the processors can be prevented. Therefore, it is possible to minimize the effects on the system caused by the failure of the processor.

Although the present invention is applied to a multi-microprocessor system consisting of two microprocessors, the present invention is not limited to this, and the reset control circuit 1 may also be applied to a system consisting of three or more processors.
Of course, the present invention can be applied by adding a microprocessor 7 and providing one of the processors with a function similar to that of the first microprocessor 11 of this embodiment.

Incidentally, in the embodiment described above, the reliability of the first microprocessor 11 is important. That is, if the first microprocessor 11 resets all other processors due to an abnormality in its own program, there is a risk that a serious failure will develop. Next, an embodiment of a reset method will be described in which the first microprocessor 11 does not affect other processors when the first microprocessor 11 has an abnormality. For convenience of explanation, an example will be described in which the present invention is applied to the system shown in FIG. 1 as a multi-microprocessor system.

FIG. 3 is a block diagram showing the main components related to the present invention of the first microprocessor 11 and its peripheral circuits in another embodiment. This embodiment differs from the previous embodiments in that it is provided with a D-type flip-flop 40 whose clock pulse input is the output signal from the WDT 14 and whose D input is the reference power supply VCC. Then, the status port 41 that takes in the Q output of this flip-flop 40 is connected to the C
This point is provided in the internal bus 27 connected to the PU 21.

Since the other parts are the same as those in the previous embodiment, the same parts are given the same reference numerals and detailed explanations will be omitted.

In this embodiment with such a configuration, if a program runaway occurs in the second microprocessor 12, the WDT1
5 outputs an abnormality diagnosis output, the CPU 21 detects this abnormality diagnosis output via the status port 24,
The second microprocessor 12 is appropriately reset via the command latch port 26.

On the other hand, when a program runaway or the like occurs in the first microprocessor 11 and an abnormality diagnosis output is output from the WDT 14, a reset signal generated by the reset generation circuit 29 is input to the status port 25, and the reset signal generated by the reset generation circuit 29 is input to the status port 25. 1
The microprocessor 11 is reset. At this time, the flip-flop 40 is set, so the CPU
By reading the status of the status port 41 after the reset is released, the device 21 can confirm that the current reset is due to an abnormality in itself. Therefore, if the Q output to the status port 41 is set after the reset is released, the CPU 21 determines that the other processors are performing normal operations, and the CPU 21 determines that the other processors are performing normal operations, and the CPU 21 performs its own operation without affecting the other processors. Initiate initial startup behavior. By doing this, even if the first microprocessor 11 goes down, the second microprocessor 12 is not adversely affected and the first microprocessor 11 continues to operate normally. , system reliability can be increased.

On the other hand, when the first microprocessor 11 is reset by the reset signal input from the reset detection circuit 20, the flip-flop 40 remains reset, so the CPU 21 checks the status of the status port 41 after the reset is released. By reading it, you can confirm that this reset is a system-wide reset.

Therefore, if the Q output to the status port 41 is reset after the reset is canceled, the CPU 21 determines that the other processors have also been reset, and starts the initial startup operation including the other processors. This can be controlled by the output from command latch port 26.

[Effects of the Invention] As detailed above, the present invention provides a multi-microprocessor system that can reliably recognize an abnormality in other microprocessors and control the reset of the abnormal microprocessor while eliminating wasted processing time. can provide a reset method.

Further, according to claim 2, it is possible to provide a reset method for a multi-microprocessor system that can appropriately handle resets caused by abnormalities in selected microprocessors and improve system reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of one embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the main parts in the same embodiment, and FIG. 3 is a block diagram showing the main parts in another embodiment of the invention. FIG. 4 is a program diagram showing the overall configuration of a conventional example. 11.12...ml! 2 microprocessor,
14.15...WDT, 17...Reset control circuit, 20...Reset detection circuit, 40...D type flip-flop.

Claims (2)

[Claims] (1) In a multi-microprocessor system in which a plurality of microprocessors each having an abnormality diagnosis circuit are electrically coupled to exchange data between the microprocessors, any one of the microprocessors is selected. The selected microprocessor inputs the output signal of the abnormality diagnosis circuit of the other microprocessor, determines the abnormality of the other microprocessor based on this input signal, and when an abnormality is detected, the abnormal microprocessor A reset method for a multi-microprocessor system characterized by controlling reset for a multi-microprocessor system. (2) The selected microprocessor inputs the system reset signal and the output signal of its own abnormality diagnosis circuit, and when reset is applied by the system reset signal, resets all other microprocessors. 2. The reset system for a multi-microprocessor system according to claim 1, wherein when the reset is applied by the output signal of the own abnormality diagnostic circuit, only the reset is controlled by itself.