JP2815730B2 - Adapters and computer systems - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention multiplexes a system bus.
Used to facilitate fault handling when
And a computer system using the adapter . In order to prevent device control from becoming impossible due to a system bus failure, it is necessary to provide a multiplexed computer system in which a processor and a plurality of adapters are connected by a connection system using a plurality of system buses.

However, if any one system bus fails, various problems occur in the processing on the adapter side. In other words, if the adapter connected to the failed system bus is in the process of controlling the device, the device control cannot be instructed to stop, and the device cannot be used by the normal system adapter. If the adapter of the faulty system does not stop processing, there is a risk of malfunction due to a fault in the system bus. Further, there is a case where the recovery process cannot be appropriately performed because the cause of the stop of the adapter is not known on the processor side at the time of failure recovery. Therefore, there is a demand for a processing method capable of appropriately solving such a problem on the adapter side when a system bus failure occurs.

[0003]

2. Description of the Related Art FIG. 4 shows a configuration example of a conventional general computer system. In the computer system shown in FIG. 4, a single processor (PM) 1 is connected to a single adapter (ADP) 3 through a system bus 2, and a device (such as a magnetic disk) is connected to an input / output bus 5 from the adapter 3. DVC) 4 is connected.

As described above, in a conventional general computer system, the adapter 3 and the device 4 of the processor 1 are not connected by a plurality of connection systems, and the processor 1 is controlled by the adapter 3 and the adapter under a single system bus 2. Of the device 4 is controlled. Therefore, when a system bus failure occurs in the conventional computer system, the processor 1 cannot control the device 4 and the entire computer system is stopped.

[0005] As shown in FIG. 5, a processor 1 and a plurality of adapters 3A and 3B are connected to a plurality of system buses 2A and 2B.
B, a so-called multiplexed computer system in which a plurality of adapters 3A and 3B and a plurality of devices 4 are connected by a plurality of input / output buses 5A and 5B is considered. The processor 1, the plurality of adapters 3A and 3B, and the plurality of devices 4 are connected by a plurality of connection systems.

In a case where such a multiplexed computer system is assumed, for example, a system bus 2
When a failure occurs in A, the processor 1 can control the device 4 by the adapter 3B connected to the system bus 2B, and the failure of one system bus does not stop the entire computer system.

[0007]

However, in a multiplexed computer system, if the adapter 3A connected to the faulty system bus 2A is executing control of the device 4, the processor 1 will be switched to the adapter 3A. Cannot notify that the control of the device 4 has been stopped via the failed system bus 3A. If the control of the device 4 is not stopped in this way, the device 4 cannot be controlled by the adapter 3B connected to the normal system bus 2B, and the device 4 is being controlled by the failed system when a failure occurs. In some cases, the device 4 that has been disabled cannot be used.

Although it is possible to perform recovery processing of the device 4 whose control cannot be stopped by the adapter 3B of the normal system, the processing of the processor 1 becomes complicated because the stop factor must be diffracted, and the device 4 takes time, and the adapter 3B connected to the normal system bus 2B has a problem that extra processing for the recovery processing of the device 4 increases.

If the adapter does not stop all processing upon detection of a system bus failure, there is a problem that the adapter malfunctions due to abnormal operation of the failed system bus. Further, when the system bus failure is recovered, the processor performs recovery processing on the adapter. It is easy to confirm whether the adapter has stopped processing due to the system bus failure or has stopped processing due to the failure of the adapter itself. Since there is no method, there is a problem that an appropriate recovery process cannot be performed.

The present invention has been made in view of such a conventional problem, and in a computer system in which a connection system for connecting an adapter to a processor using a system bus is multiplexed, a failure occurs in the system bus. Adapter and computer system that can easily perform device recovery processing, prevent malfunction of the adapter, and perform appropriate recovery processing by the processor at the time of failure recovery.
The purpose is to provide a stem .

[0011]

FIG. 1 is a diagram illustrating the principle of the present invention. First, the present invention connects to a processor via a bus.
And an adapter to connect the device under
set to target. Bus failures in such adapters
Bus fault detection means for detecting
Is detected by the bus failure detection means during device control.
Command to reconnect to the device and invalidate the instruction
And a failure handling means. In addition,
Ming is connected to the processor via the processor and the bus
And a device shared by the processor under
Computer with multiple adapters for connecting chairs
Target the system. Such a computer system
Bus failure to detect bus failure
Detecting means and controlling the device by the release command
When receiving a failure detection signal from the bus failure detection means,
Fault handling means for invalidating instructions by reconnecting to the
It is characterized by having.

The present invention also relates to a processor
Adapter that connects to devices under
Bus fault detecting means for detecting a bus fault
Device receives a failure detection signal from the bus failure detection means.
Device failure notification to self created and maintained by
Failure handling means for invalidating information.
I do. Further, the present invention provides the above-mentioned
Connected to the processor and under the processor
Multiple adapters to connect more shared devices
In a computer system consisting of
Bus fault detecting means for detecting a bus fault and bus fault detection
When receiving a failure detection signal of the means, it is created and held by the device
Disable device failure notification information for self
And a failure handling means.

According to the present invention, an adapter is provided with
Stores the information indicating the cause of the
Equipped with means for notifying information by instructions from the processor
It is characterized by the following.

The present invention also provides a processor
Information indicates the path failure as the cause of the adapter stop
If an error occurs, restart the adapter
Is provided.

The present invention also provides a processor
The information indicates that the adapter itself is
If you find any harm, recover it according to the adapter log information.
It is characterized by comprising means for performing a burr process.

[0016]

According to the adapter processing method for detecting a bus failure of the present invention having the above-described structure, the following effects can be obtained. First, in order to prevent device control from becoming impossible due to a system bus failure, it is necessary to provide a multiplexed computer system in which a processor and a plurality of adapters are connected by a plurality of connection systems.

In the multiplexed computer system according to the present invention, the adapter that has detected the system bus failure stops all the processes of the devices under the adapter and performs a stop process to release the device resources.
After the device release processing, all processing of the adapter is stopped, thereby preventing malfunction of the adapter. Further, a stop information storage unit for notifying the processor that the adapter has stopped processing upon detection of the system bus failure is provided, and after the recovery of the system bus failure, the processor refers to the stop information stored in the adapter so that the adapter can stop processing. The cause of the processing stop can be checked.

[0018] For this reason, since the recovery process of the device in the event of a failure in the system bus is all performed on the adapter side, the recovery process is easy and short.
The adapter connected to the normal system bus does not require any extra processing for recovery. Further, after the adapter that has detected the system bus failure performs the device release processing, all processing is stopped, thereby preventing malfunction of the adapter. Furthermore, when the system bus failure is recovered, the processor can be notified whether the adapter has stopped due to the system bus failure or the adapter itself, so that the processor knows the cause of the adapter stop and performs appropriate recovery processing of the adapter. Can be.

[0019]

FIG. 2 is a block diagram showing an embodiment of a computer system to which the adapter processing system of the present invention is applied. In FIG. 2, a processor 1 is a central processing unit (CPU) 1
1. A local memory (LSU) 13 in a processor and two bus controllers 12A and 12B, and the bus controllers 12A and 12B are connected to adapters 3A and 3B through system buses 2A and 2B.

The adapters 3A and 3B are a central processing unit (CPU) 21, a data buffer 22 in the adapter, a bus controller 23, an input / output bus controller (device controller) 24.
The device control unit 24 of each adapter 3A, 3B is connected to a plurality of devices 4 via input / output buses 5A, 5B. The device 4 has a plurality of input / output buses 5
A multi-port device that can be connected to A and 5B.
A magnetic storage device such as an SD (direct access device).

Further, bus arbiters 6A and 6B for system bus arbitration are connected to the system buses 2A and 2B, respectively. Normally, the processor 1 issues an I / O command (input / output command) to the adapter 3A or 3B through the bus control unit 12A or 12B to perform device control. Upon receiving the I / O command, the adapters 3A and 3B
Processor 1 according to the parameter storage address of the / O instruction
Fetches parameters from the local memory 13 and controls the device 4 in accordance with the fetch parameters to perform data transfer between the device 4 and the processor 1. When the control of the device 4 is completed, an interrupt is issued to the processor 1 to report the end of the processing of the I / O instruction.

In such a computer system, for example, if a failure occurs in the bus arbiter 6A and its function is stopped, the function of the system bus 2A is stopped and communication between the processor 1 and the adapter 3A becomes impossible. In response to this system bus failure, the adapter processing method of the present invention performs the following processing operation according to the processing flow shown in FIG.

First, the processor 1 and the adapter 3A connected to the system bus 2A are connected to the steps P1 and A1 in FIG.
As shown in (1), the occurrence of a system bus failure is recognized through the bus controllers 12A and 23. The adapter 3A that has detected the system bus failure issues a command to suspend the processing of all devices 4 under the input / output bus 5A through the input / output control unit 24, and performs device release processing. As a result, all processing of the device 4 by the ports of the input / output bus 5A is released. Further, after completion of the release processing of the device 4 as shown in step A2, the adapter 3A stores information indicating that the processing of the adapter has been stopped due to the detection of the system bus failure in the bus control unit 23, and stops all the processing. I do.

On the other hand, the processor 1 receives a system bus failure notification from the bus control unit 12A.
Stop using. The processing of the processor 1 for the device 4 is performed by the adapter 3B through the system bus 12B as shown in Step P2, and does not affect the operation of the entire computer system. The bus arbiter 6A is exchanged to recover from the failure of the system bus 3A.

When the bus arbiter 6A is replaced, step P
As shown in FIG. 3, upon receiving a restoration notification from the bus control unit 12A, the use of the bus control unit 12A is resumed. Subsequently, in step P4, an I / O instruction for knowing the cause of the stop is issued to all the adapters connected to the system bus A. The adapter 3A that has received the I / O instruction from the processor 1 notifies the processor 1 of the information indicating the stop factor stored in step A2 as shown in step A3. At this time, the firmware of the adapter 3A does not operate.

If the stop factor notified by the I / O instruction from the adapter 3A in step P5 is due to a system bus failure, the processor 1 issues an adapter restart I / O instruction, and proceeds to step A4. Adapter 3A
And restart the process. If the cause of the adapter stop is due to a failure of the adapter itself, the log information of the adapter is collected and an appropriate recovery process is performed. Upon completion of the above restoration processing, the flow proceeds to Step P6 and shifts to normal processing.

Here, in the processing flow of FIG. 3, as a release process performed by the adapter when a system bus failure occurs, if the device is being controlled when a system bus failure occurs, control of the device is immediately interrupted. The case in which the control of the device is instructed to stop is taken as an example. In addition, there are the following two release processes. First, when the device recognizes the detection of the system bus failure while instructing the DASD as the device by the push-out type instruction, the device is reconnected and the seek instruction is invalidated.

For example, when SCSI is assumed as the device bus, a connect command is issued from the adapter to the device to be operated, which means a logical connection, and the operation is instructed. At this time, in the case of an instruction requiring a long time for processing such as seeking, the device bus is temporarily released by disconnecting. Upon completion of the instruction execution processing, the device issues a reconnect request, and the adapter continues reconnecting to continue the processing.

Therefore, if the adapter recognizes the detection of a system bus failure while the device is disconnected, the adapter needs to reconnect the device and invalidate the seek instruction. Next, a release process for invalidating the sense information for the own adapter created and held by the device is required. The sense information is fault notification information of the device. When any fault occurs in the device, sense information is generated internally corresponding to each adapter. The sense information of the device is notified to the adapter by issuing a sense information collection command from the adapter.

Therefore, when the detection of the system bus failure is recognized, if the sense information for the own adapter is not invalidated, other adapters connected to the normal system bus must wait until the sense information is collected. There are a number of devices that make a busy response to the start command of the device, and the sense information is invalidated to prevent this. Note that the release processing for the device when the detection of the system bus failure is recognized is not limited to the above-described embodiment, and is appropriately determined according to the device bus processing mode between the adapter and the device.

[0031]

As described above, according to the present invention, recovery processing of a device when a failure occurs in a system bus is facilitated, and the recovery processing time is short, and
Further, there is no need to burden the adapter connected to the normal system bus with unnecessary processing for recovery.

Further, by stopping all the processes after the adapter which has detected the system bus failure performs the device release process, it is possible to prevent the malfunction of the adapter. Furthermore,
When the system bus failure is recovered, the processor is notified that the adapter has stopped due to the system bus failure, so that the adapter can be properly recovered by knowing the cause of the adapter stop.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of a computer system to which the present invention is applied;

FIG. 3 is a processing flowchart showing an adapter processing of the present invention.

FIG. 4 is a configuration diagram of a conventional general computer system.

FIG. 5 is a configuration diagram of a conventional multiplexed computer system.

[Description of Signs] 1: Processor 2, 2A, 2B: System bus 3, 3A, 3B: Adapter (ADP) 4: Device (DVC) 5, 5A, 5B: I / O bus 6A, 6B: Bus arbiter 7: Bus failure Detecting means 8: Failure processing means 9: Stop information storage means 11, 21: Central processing unit (CPU) 12A, 12B, 23: Bus control unit 13: Local memory (LSU) 22: Data buffer 24: Input / output control unit ( Device control section)

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-54-2635 (JP, A) JP-A 64-38856 (JP, A) JP-A-3-51937 (JP, A) JP-A 60-38 204050 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 13/00 G06F 11/20

Claims (7)

(57) [Claims] (1) When connected to a processor via a bus,
An adapter for connecting a device under the bus, a bus failure detection means for detecting a failure of the bus , and said control during the control of the device by a thrust-type command
Upon receiving a failure detection signal from the bus failure detecting means, the device
Failure handling means for reconnecting with the
An adapter comprising: 2. The processor according to claim 2 , wherein said processor is connected to said processor via a bus.
And shared by the processor under its control
Consisting of multiple adapters for connecting devices
In the computer system, the adapter is provided with a bus failure detection for detecting a failure of the bus.
Output means and the bus failure during control of the device by the release command.
Upon receiving a failure detection signal from the harm detection means, the device is re-connected to the device.
Fault handling means for connecting and invalidating the instruction.
A computer system characterized by the following: 3. When connected to a processor via a bus,
An adapter for connecting a device under the bus, the bus failure detecting means detecting the bus failure, and receiving the failure detection signal from the bus failure detection means.
Vice
Failure processing means for invalidating the failure notification information
An adapter, characterized in that: 4. The processor via a processor and a bus.
It is connected with, shared by the processor under
Consisting of multiple adapters to connect devices
In the computer system, the adapter is provided with a bus failure detection for detecting a failure of the bus.
Output means and a failure detection signal from the bus failure detection means.
Vice
Having failure processing means for invalidating the failure notification information
A computer system characterized by the following: 5. The processing of the adapter is stopped by the adapter.
Stores information indicating the cause of the
Means for notifying the above information in accordance with instructions from
5. The method according to claim 2, wherein:
Computer system. 6. The information notified to the processor.
Learned the bus failure as a cause of adapter stoppage
In this case, restart the adapter and issue a recovery
6. A method according to claim 5, further comprising:
Computer system. 7. The information notified to the processor.
The failure of the adapter itself is recognized as the cause of the adapter stop.
Recovery, the recovery according to the log information of the adapter is performed.
6. The apparatus according to claim 5, further comprising means for performing reprocessing.
Computer system.