JPH07104795B2 - Error detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a module constituting an information processing device, that is, a CPU (central processing unit), an IOP (input / output control unit), a MEM (main storage unit), and the like. The present invention relates to an error detection method of each module.

[Conventional technology]

Conventionally, as an error detection method for each module such as CPU, IOP, and MEM that configures an information processing device, the same module is duplicated and one module is designated as a master and the other module is designated as a slave, Generally, a method is adopted in which output information of a designated module and output information of a slave designated module are compared to detect an error.

[Problems to be solved by the invention]

In the error detection method in which the conventional module is duplicated, there is a drawback that the master and slave modules are always tied together and the module mounting is not flexible.

An object of the present invention is to provide an error detection method that overcomes such drawbacks and enables error detection of a duplicated module regardless of the mounting position of the module.

[Means for solving problems]

To achieve the above object, in the present invention, in an information processing device formed by interconnecting the modules, each of which comprises a CPU, an IOP, a MEM, etc., by connecting the modules to each other via a bus connection unit. When the master is designated in the module ID register holding the module ID, the mode display register, and the mode display register, the bus connection unit outputs the output from the own module in response to the bus output request from the own module. A circuit that adds the contents of the module ID register to the information and outputs it to the bus. If a slave is specified in the mode display register, the bus is monitored and the module ID on the bus is monitored.
Is the same as the contents of the own module ID register, and the output information from the own module and the information on the bus do not match,
A circuit that outputs a signal indicating that an error exists in the modules having the same module ID.

[Action]

When the same module ID is assigned to each duplicated module, and the module designated by the master outputs the output information to the bus, the module ID is assigned and output, and the module designated by the slave always monitors the bus and If the module ID of is matched with the self module ID, the information on the bus is compared with the information that the self module was trying to output to the bus, and the module error is detected. This makes it possible to detect an error in a duplicated module regardless of the module mounting position.

〔Example〕

 FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 1, 2 and 3 are modules constituting CPU, IOP, MEM, etc., 4,5 and 6 are bus connection parts respectively, 7 is a mode display register for designating whether the own module is a master or a slave, 8 Is a module ID register, and 9 and 10 are comparison circuits, respectively, and when two inputs match, the output is turned on. 11 is an inverter, 12 and 13 are AND gates, 14 and 1
Reference numerals 5 and 16 are tristate buffers. 17 is an information bus that carries communication information between modules, 18 is a module ID bus that carries a module ID, and 19, 20 and 21 are modules respectively
Signal lines for instructing bus output requests from 1,2,3 to bus connection units 4, 5, 6; 22, 23, 24 are between module 1, 2, 3 and bus connection units 4, 5, 6 respectively. Signal line for exchanging communication information between modules, 25 is an AND gate for contents of mode display register 7
Signal lines 12 and 13 are provided, 26 is a signal line that gives the contents of the module ID register 8 to the comparison circuit 9 and the tri-state buffer 16, 27 is a signal line that gives the output of the inverter 11 to the tri-state buffer 14, and 28 is an AND gate. A signal line for giving the output of 12 to the tri-state buffers 15 and 16, a signal line for giving the output of the comparator circuit 9 to the AND gate 13, a number 30 for a signal line for giving the output of the comparator circuit 10 to the AND gate 13, and 31
Is a signal line that is turned on when an error is detected.

An error detection method as an embodiment of the present invention will be described below with reference to the drawings.

First, the case where the mode display register 7 of the bus connection unit 4 is turned on, that is, the module 1 is used as a master will be described. When the module 1 turns on the signal line 19 and makes a bus output request, the output of the AND gate 12 turns on and the tristate buffers 15 and 16 turn on, and the output of the inverter 11 turns off and the tristate buffer 14 turns off. Becomes Therefore, the inter-module communication information sent from the module 1 to the bus connection unit 4 via the signal line 22 is output to the information bus 17 via the tri-state buffer 15. Further, the module ID set in the module ID register 8 is output to the module ID bus 18 via the signal line 26 and the tri-state buffer 16.

In this way, by designating the mode display register of the bus connection unit added for the module as the master, the output information from the module and the module ID are output to the bus and transmitted to all the modules connected to the bus. To be done.

Next, a case where the mode display register 7 of the bus connection unit 4 is turned off, that is, the module 1 is designated as a slave will be described.

Even if the module 1 turns on the signal line 19 and makes a bus output request, the mode display register 7 is turned off, so that the AND gate 12 is turned off and the tristate buffers 15 and 16 are turned off. Therefore, the communication information between the modules sent from the module 1 to the bus connection unit 4 via the signal line 22 and the module ID set in the module ID register 8 are output to the information bus 17 and the module ID bus 18, respectively. It will not be done. In the bus connection unit 4, the comparison circuit 9 always determines whether or not the contents on the module ID register 8 and the module ID bus 18 match each other, and the comparison circuit 10 causes the bus connection unit from the module 1 via the signal line 22. It is checked whether or not the communication information between the modules given to 4 and the contents on the information bus 17 match, and the output of the comparison circuit 9 is turned on (that is, the contents of the module ID register 7 and the module ID bus 18). And the output of the comparison circuit 10 is on (that is, the communication information between the modules provided from the module 1 to the bus connection unit 4 via the signal line 22 does not match the content on the information bus 17). In this case, since the module display register 7 is off, the AND gate 13 is on and an error is detected.

In the figure, the values set in the mode display register and the module ID register may be determined depending on which modules connected to the information bus and the module ID bus mutually perform error checking. For example, when the module 1 and the module 2 are duplicated and the output thereof is checked to perform error detection, "1" (master) is set in the mode display register 7 of the bus connection unit 4 and Set the mode display register "0" (slave). Also, the same ID (however, this module ID cannot be used in modules other than the module 1 and the module 2) is set in the module ID registers of the bus connection unit 4 and the bus connection unit 5.

〔The invention's effect〕

As described above, according to the present invention, for example, of two CPU modules, one is designated as a master and the other one is designated as a slave, and the module IDs of both CPUs are designated.
By making them the same, it is possible to perform error checking regardless of the positions on the bus where the two CPUs are mounted.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. Explanation of symbols 1,2,3 …… Module, 4,5,6 …… Bus connection part, 7 …… Mode display register, 8 …… Module ID register, 9,10
…… Comparison circuit, 11 …… Inverter, 12,13 …… And gate, 14,15,16 …… Tri-state buffer.

Claims (1)

[Claims] 1. A central processing unit (CPU), an input / output control unit (IO
P), a main memory unit (MEM) and the like, each module is connected to a bus via each bus connection unit, thereby connecting the modules to each other. , A module ID register that holds the module ID for distinguishing the module from other modules, a mode display register that specifies whether the module is a master or a slave, and if the master is specified in the mode display register, In response to a bus output request from the circuit, a circuit that adds the contents of the module ID register to the output information from the own module and outputs to the bus, and if a slave is specified in the mode display register, monitors the bus, The module ID on the bus matches the contents of the own module ID register, and the output from the own module is If information and information mismatch on the bus, the error detection method, characterized by comprising, a circuit for outputting a signal indicating that the assumption that there is an error in the module having the same module ID.