JPH06223046A - Bus tracing execution method - Google Patents

Abstract

PURPOSE:To trace a common bus and local buses in respective processor modules by a multiprocessor system which meets requirements of the maximum connection number of common buses by enabling tracing operation and tracing all the common buses. CONSTITUTION:A trace interface 8 transfers local bus trace data from the respective processor modules 31, 32, and 33 to a trace memory 4. A timer value is set in a trace timer 6 and a trace control part 5 controls the trace timer 6; traces both the data of a common bus 1 and data of a local bus 20 at the same time or traces one optionally selected bus, and stores trace information in a trace memory 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus trace execution method for tracing data flowing on a common bus interconnecting a plurality of processor modules or data flowing on a local bus inside a processor module.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional multiprocessor system. In FIG. 4, 1 is a common bus for connecting processor modules to each other, 21 is a main processor which is one of the processor modules, Two
Reference numerals 2 and 23 are single processors which are processor modules each having an independent function, and 3 is a trace device for tracing bus information. In the trace device 3,
4 is a trace memory for storing the traced data, 5
Is a trace control unit for controlling the trace operation, and 6 is a trace timer for generating time information stored in the trace memory 4 together with the trace data. Reference numeral 2 denotes a man-machine interface for displaying the trace information stored in the trace memory 4 and performing an input operation.

Next, the operation will be described. The main processor 21 notifies the trace control unit 5 of the trace device 3 of the start of the trace operation, and the trace control unit 5 activates the trace timer 6 and the trace memory 4 to trace the data flowing on the common bus 1. Start. Then, the trace data and the timer value output by the trace timer 6 are stored at the same address in the trace memory 4. The stored trace data and the time value can be confirmed on the man-machine interface 2.

[0004]

Generally, the processor modules connectable to the common bus have physical and electrical restrictions, and the maximum number of connections is determined by these restrictions.
Since the conventional multiprocessor system is configured as described above, it is necessary to connect the trace device and the main processor to the common bus, and the trace device cannot be connected in the case of the multiprocessor system which has the maximum number of connections. Further, since the trace device cannot operate unless the activation request is received from the main processor via the common bus, bus trace cannot be performed unless it is premised that the common bus is operating normally. Furthermore, when searching for the cause of problems and adverse effects in the entire multiprocessor system, it is not possible to grasp the relationship between the common bus and the operation inside the processor module connected to the common bus by tracing only the signals on the common bus. However, there was a problem that the cause could not be found easily.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to perform a trace operation even in a multiprocessor system in which the maximum number of common bus connections is satisfied, and the common operation is also possible. An object of the present invention is to provide a bus trace execution method capable of executing all traces including a bus initializing operation and tracing both a common bus and a local bus in each processor module connected to the common bus. .

[0006]

A bus trace executing method according to a first aspect of the present invention is directed to a processor module 31, 32,
The trace interface 8 for storing the trace information of the data flowing in the local bus 20 in the 33 as well as the trace interface 8 simultaneously traces both the data flowing in the common bus 1 and the data flowing in the local bus 20,
Alternatively, a trace timer 6 for setting a timer value for executing one of the arbitrarily selected traces is provided in the trace device 3, and the trace timer 6 is controlled by the trace control unit 5 to execute the trace.

A bus trace executing method according to a second aspect of the present invention includes a trace interface 8 for storing trace information of data flowing on the local bus 20 in the processor modules 31, 32 and 33 in the trace memory 4.
Is provided in the trace device 3, the trace interface 8 is controlled by the processor 11, and the trace of the data flowing to the local bus 20 in any or all of the processor modules is executed.

[0008]

In the invention of claim 1, the trace interface 8 transfers the trace information of the data flowing on the local bus 20 in the processor module 31, 32, 33 to the trace memory 4, whereby the trace memory 4 receives the trace information. Remember. The trace controller 5 simultaneously traces both the data flowing through the common bus 1 and the data flowing through the local bus 20 based on the timer value set in the trace timer 6, or executes one of the arbitrarily selected traces.

In the invention of claim 2, the processor 11
Controls the trace interface 8 to perform a trace of data flowing on the local bus 20 in any or all processor modules.

[0010]

【Example】

Example 1 (corresponding to claims 1 and 2). 1 is a block diagram of a multiprocessor system according to a first embodiment of the present invention. In FIG. 1, 1 is a common bus that interconnects the processor modules 31, 32 and 33 with each other, 3 is a trace device that controls the trace function of the bus, which is a feature of this embodiment, and 34 is a man-machine interface function with an operator. It is the host computer that I had. Each of the processor modules 31, 32, and 33 includes a processor 15 that performs processing related to trace, an independent function 16, a bus interface 17 that performs input / output with the common bus 1, a memory 18 that stores data necessary for processing, and a local. A trace interface 19 for performing input / output with the bus 20 is provided. The trace device 3 includes a trace memory 4 for storing traced data, a trace controller 5 for controlling a bus trace,
Trace timer 6 for generating time information stored in trace memory 4 together with trace data, memory 7 for storing data required for processing, processor modules 31, 3
A trace interface 8 for storing the trace information of the data flowing on the local bus 20 in the reference numerals 2, 33 in the trace memory 4, a common bus data input section 9 for taking in the data on the common bus 1, each processor module 3
The local bus data input unit 10 and the trace control unit 5 for taking in the data of the local bus 20 inside 1, 32, and 33.
A processor 11 for initializing and starting and stopping a trace operation, a host interface 12 for interfacing with a host computer 34 for man-machine interface, and buffer circuits 13, 14 for buffering data from the common bus 1. ing.

Next, the operation will be described. For example, when the maximum number of connections of the common bus 1 is 3, the processor module 33 is used to connect the trace device 3 to the common bus 1.
Is temporarily disconnected from the common bus 1, the trace device 3 is connected to the common bus 1 instead, and the processor module 33 is connected to the trace device 3 as shown in FIG. Since it is connected to the common bus 1, an environment similar to that of the microprocessor system before the trace device 3 is connected to the common bus 1 is realized. Operator to host computer 3
The start information such as the trace condition and the trace start is transmitted to the processor 11 via 4 and the host interface 12. The processor 11 processes the information from the host computer 34 side, and prompts the setting of the trace condition of the trace control unit 5 and the activation of the bus trace. The trace control unit 5 that has received the activation of the bus trace operates the trace timer 6
The data on the common bus 1 fetched from the common bus 1 via the common bus data input unit 9 and the processor modules 31 mutually connected to the common bus 1.
It controls the operation of storing the data on the local bus 20 fetched from the local bus 20 in 32, 33 via the local bus data input unit 10 in the trace memory 4 together with the time information generated by the trace timer 6.

FIG. 2 is a block diagram showing the periphery of the trace memory. In FIG. 2, 9a is a data input signal of the common bus, and 9b is a common bus confirmation signal of the data input signal 9a. Further, 10a is a data input signal of the local bus, and 10b is a local bus confirmation signal of the data input signal 10a. Reference numerals 4a and 4b are trace memory areas in the trace memory 4. Reference numerals 6a and 6b are through latch control type timer data buffer circuits for temporarily holding the timer value from the trace timer 6.

FIG. 3 is a timing chart showing the concept of taking in the trace timer value at the same time as the common bus data and the local bus data, and shows the change of the data when the time elapses from right to left. In FIG. 3, T1 is the trace timer 6 to the timer data buffer circuit 6 of FIG.
It is a timer value sent to a and 6b, and changes in a fixed cycle. T2 is the timer value sent from the timer data buffer circuit 6a of FIG. 2 to the trace memory area 4a, and T3 is the timer value of FIG.
The timer value sent from the timer data buffer circuit 6b to the trace memory area 4b is shown. B1 is a common bus data input signal sent from the common bus data input section 9 of FIG. 2 to the trace memory area 4a, and B2 is common bus data sent from the common bus data input / output section 9 of FIG. 2 to the trace memory area 4a. It is a common bus decision signal indicating that the input signal has been decided. B3 is a data input signal of the local bus sent from the local bus data input unit 10 of FIG. 2 to the trace memory area 4b, and B4 is a data input signal of the local bus sent from the local bus data input unit 10 of FIG. 2 to the trace memory area 4b. It is a local bus confirmation signal indicating that the signal has been confirmed.

Next, the operation will be described. When the common bus data input signal 9a is determined, the common bus determination signal 9b is output from the common bus data input unit 9 to the timer data buffer circuit 6a, and the timer data buffer circuit 6a outputs the timer value sent from the trace timer 6. Hold temporarily. The data input signal 9a of the common bus and the timer value temporarily held in the timer data buffer 6a are written in the trace memory 4a. Since the local bus side operates in the same way, the data of the local bus and the data of the common bus are written to the trace memory together with the common timer value, so the operations of the common bus and the local bus can be analyzed in time series. Is.

Embodiment 2 (corresponding to claim 2). In the first embodiment, each processor module 31, 3
All the local bus trace data from the local buses 8 of 2, 33 are collectively input to the local bus data input unit 10 via the trace interface 8, but the processor 11 controls the trace interface 8. Therefore, only arbitrary local bus data may be input to the local bus data input unit 10. In addition, the trace interface 8 and the local bus data input unit 1
Between 0, an input data selection mechanism such as a multiplexer for local bus data selection may be provided. Furthermore, in the above-described first embodiment, the processor modules 31, 32, and 33 are set to three.
However, this quantity may be plural or singular.

In the multiprocessor system according to the first and second embodiments, the trace device is provided with the cascade mechanism of the common bus, and even the multiprocessor system satisfying the maximum number of connections of the bus is connected to the common bus. Function to realize the same environment as the original multiprocessor system by removing any node from the common bus, connecting the trace device to it, and connecting the node removed from the common bus to the cascade mechanism of the trace device. To do. Further, the tracing device is provided with a processor, and the tracing operation is executed in response to a bus trace activation request from the host interface, whereby the tracing device operates regardless of the state of the common bus. Further, a data input unit for each of the common bus and each of the local buses in the processor module mutually connected to the common bus is provided, and the traces of both buses can be executed in association with each other. Function to communicate to the operator via.

As described above, according to the first and second embodiments,
The trace device can be operated regardless of the maximum number of connections that can be connected to the common bus of the multiprocessor system. In addition, since the trace device is equipped with a processor, the number of connections on the common bus can be reduced, bus trace activation via the common bus is unnecessary, and the trace device can execute bus trace operations independently. All data from the bus power up can be traced and the cause of troubles in the multiprocessor system can be easily investigated. Furthermore, by performing a trace of both the common bus of the multiprocessor system and the local bus in the processor module interconnected to the common bus, the common bus and the processor can be processed in the event of a general multiprocessor system failure. Since it is possible to understand the relationship with the internal operation of the module, the cause of the failure can be easily investigated.

[0018]

As described above, according to the invention of claim 1,
Trace interface for storing the trace information of the data flowing on the local bus in the processor module in the trace memory, and tracing both the data flowing on the common bus and the data flowing on the local bus at the same time, or executing one of the selected traces. A trace timer that sets a timer value for setting the trace value is provided in the trace device, and the trace is executed by controlling the trace timer, so even in a multiprocessor system that satisfies the maximum number of common bus connections, trace operation is possible. All traces including the initialization operation of the common bus can be performed, and the trace of the common bus and / or the local bus in each processor module connected to the common bus becomes possible.
Therefore, there is an effect that the cause of the malfunction of the multiprocessor system can be easily investigated.

According to the second aspect of the present invention, a trace interface for storing the trace information of the data flowing on the local bus in the processor module in the trace memory is provided, and by controlling this interface, any or all processor modules are provided. Since the trace of the data flowing to the local bus in the inside is executed, there is an effect that the cause of the failure of each processor module can be easily found.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiprocessor system showing a first embodiment of the present invention.

FIG. 2 is a block diagram around a trace memory in FIG.

FIG. 3 is a timing chart showing a trace operation of this embodiment.

FIG. 4 is a block diagram of a conventional multiprocessor system.

[Explanation of symbols]

 1 common bus 3 trace device 4 trace memory 5 trace control unit 6 trace timer 7 memory 8 trace interface 9 common bus data input unit 10 local bus data input unit 11 processor 12 host interface 13, 14 buffer circuit 15 processor 16 function 17 bus interface 18 memory 19 trace interface 20 local bus 31, 32, 33 processor module 34 host computer 4a, 4b trace memory area 6a, 6b timer data buffer circuit

Claims (2)

[Claims] 1. A trace device comprising: a trace memory for storing trace information of data flowing on a common bus interconnecting a plurality of processor modules; and a trace controller for controlling the operation of the trace memory. In a multiprocessor system, a trace interface for storing also trace information of data flowing on a local bus in the processor module in the trace memory, and tracing both data flowing on the common bus and data flowing on the local bus at the same time, Alternatively, a bus trace execution method characterized in that a trace timer for setting a timer value for executing one of the arbitrarily selected traces is provided in the trace device, and the trace is executed by controlling the trace timer. 2. A trace device comprising a trace memory for storing trace information of data flowing on a common bus interconnecting a plurality of processor modules, and a trace controller for controlling the operation of the trace memory. In a multiprocessor system, a trace interface for storing the trace information of the data flowing on the local bus in the processor module in the trace memory is provided, and by controlling this interface, any or all of the local buses in the processor module are provided. A method of executing a bus trace, characterized by executing a trace of data flowing through the bus.