JPH05128279A - One-chip microcomputer - Google Patents

Abstract

PURPOSE:To provide a one-chip microcomputer capable of performing a data exchange processing between the internal register of a CPU and a RAM or the peripheral circuit of an I/O buffer, etc., by a one-machine cycle. CONSTITUTION:A data bus is divided into 2 systems of a first bus 61 and a second bus 62, and the bus which an internal register 5 transmits data and the bus which a RAM 7 or an I/O buffer 8 transmits data are made different, respectively. Within the same machine cycle, the internal register 5 and the RAM 7 or the I/O buffer 8 are made to simultaneously transmit respective data on different buses by the same timing, and as data exists on different buses, the internal register 5 and the RAM 7 or the I/O buffer 8 fetch the data on each bus simultaneously by the same timing. Thus, by a certain timing within one-machine cycle, the transmission of data on the buses of the internal register 5 and the RAM 7 or the I/O buffer 8 can be simultaneously performed, and the fetching of data from the buses of the internal register 5 and the RAM 7 or the I/O buffer 8 can be simultaneously performed by other certain timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcomputer, and more specifically, to its internal register and R
The present invention relates to a one-chip microcomputer capable of improving the processing speed when exchanging data with an AM, an I / O buffer or the like.

[0002]

2. Description of the Related Art One-chip microcomputers are often used as control circuits in cameras, household electric appliances and other electronic equipment, and many 4-bit or 8-bit control circuits are made. The internal structure of this type of one-chip microcomputer is slightly different from that of a general-purpose microprocessor. A RAM or the like is built in one chip in a fixed capacity and connected to an internal bus in advance. Sending and receiving signals to and from the external I / O connected to the internal bus
Perform in O buffer. This kind of one-chip microcomputer is designed so that a central processor (or a controller, hereinafter, CPU including them) controls these circuits to exchange data with an external circuit via an I / O buffer. There is. Further, the one-chip microcomputer incorporates various instructions different from those of a general-purpose microprocessor in order to perform control efficiently. One of them is the register in the CPU and the CPU
On the other hand, there is an instruction (data exchange instruction) for exchanging data with an external circuit such as a RAM or an I / O buffer via an internal bus.

There are the following methods for data exchange processing by executing a data exchange instruction of a conventional one-chip microcomputer. In the first method, as shown in FIG. 3A, two types of data 11 (for example, data held in an internal register) and data 12 (for example, RAM or I) to be exchanged within one machine cycle are used. (Data held in the / O buffer) is sequentially transmitted to the data bus in a time division manner and transferred. The second method is to transfer the data 11 and 12 from one to the other in different machine cycles, as shown in FIG.
Since this has two machine cycles, the transfer timing from the CPU (internal register) side to the RAM or I / O buffer and the data transfer timing from these to the CPU side can be assigned to different machine cycles. Therefore,
The data transfer direction can be separated by machine cycle. However, in this case, as shown in the figure, data exchange requires a period of two machine cycles. In addition,
The last period 13 of each machine cycle is a precharge period for the bus.

[0004]

In such a data exchange process, the first method can perform the data exchange process in one machine cycle, but the number of data exchanges is limited within one machine cycle. Since it is necessary to sequentially perform data transfer from one to the other between the RAM or I / O buffer to be data-exchanged and the internal register in accordance with the clock of, the timing of data transmission to the bus is set. There is a drawback that transfer control becomes complicated because it must be controlled by time division. The second method has a drawback that it takes time to execute an instruction because it requires two machine cycles. Moreover, in the one-chip microcomputer, since many data exchange instructions are used, the total processing speed is lowered.
An object of the present invention is to solve the above-mentioned problems of the prior art, and data exchange processing can be performed in one machine cycle between an internal register of a CPU and a peripheral circuit such as a RAM or an I / O buffer. It is to provide a one-chip microcomputer. Another object of the present invention is to provide a one-chip microcomputer capable of simplifying the wiring and circuit of the control system.

[0005]

The feature of the one-chip microcomputer of the present invention that achieves the above object is that the data bus is two systems of the first bus and the second bus, and the internal register outputs data. The bus and the bus to which the RAM or I / O buffer sends data are different from each other. Then, in the same machine cycle, the internal register and the RAM or I / O buffer simultaneously output the respective data on the different buses at the same timing, and since the data exist on the different buses, the data on the respective buses are internally stored. Register and RAM or I / O
The buffer and the buffer simultaneously capture the data at the same timing. As its specific configuration, a CP that is internally connected to a bus including a data bus and has an internal register
U, RAM connected to the bus, and I connected to the bus
/ O buffer, the data bus is divided into two systems, a first bus for sending data to the internal register and a second bus for receiving data from the internal register,
In the data exchange processing, the CPU sends the data of the internal register to the second bus in accordance with the first clock timing of one machine cycle and sends the data of either the RAM or the I / O buffer to the first bus. Take control. Then, in response to the second clock timing after one machine cycle, the data of the first bus is taken into the internal register and the data of the second bus is transferred to the RAM and the I / O.
The control is to take in one of the O buffers.

[0006]

As described above, the data bus is divided into two systems, that is, the first bus for sending data to the internal register and the second bus for receiving data from the internal register. According to the clock timing of, the data of the internal register is sent to the second bus and the data of either the RAM or the I / O buffer is sent to the first bus. The first according to the second clock timing
Of the internal bus and the RAM or the I / O buffer at a certain timing within one machine cycle by controlling the internal bus to take the data of the second bus and the data of the second bus into either the RAM or the I / O buffer. Data can be sent to the bus of the I / O buffer at the same time, and data can be fetched from the bus by the internal register and the RAM or the I / O buffer at another timing.

[0007]

1 is a block diagram of a one-chip microcomputer to which the present invention is applied, and FIG. 2 is a timing chart of processing of a data exchange instruction thereof. Figure 1
In the figure, 10 is a one-chip microcomputer in which the CPU 1 is mutually connected to the RAM 7 and the I / O buffer 8 via the internal bus 6. The CPU 1 includes a ROM 2 (which may be arranged as an external circuit of the CPU 1) in which a microprogram or the like is stored, and a decoder or an arithmetic operation circuit (A
It is composed of a controller 4 having an LU) 3 and the like, and a register group 5 and the like. The register group 5 is connected to the internal bus 6, and data is exchanged with the RAM 7 and the I / O buffer 8 via a register in the register group 5. The register group 5 includes a register for loading the result of the ALU 3 and various other registers.

The internal bus 6 comprises a data bus consisting of a U bus 61 and an L bus 62, an address bus 63 and a control bus 64. If the U-bus 61 performs 8-bit control, 8 U-buses,
If it is a 4-bit control, it is composed of four lines. The U bus 61 is a so-called unload bus exclusively provided for sending data from the CPU 1 to the outside, and is a dedicated bus to which data from a register in the register group 5 is sent to this bus. Is. R
From the viewpoint of the AM 7 and the I / O buffer 8, this is a dedicated bus for receiving data. Similarly, the L bus 62 is composed of 8 lines if it is to control 8 bits and 4 lines if it is to control 4 bits. L bus 62
Is provided exclusively for sending (loading) data from the outside to the CPU 1, contrary to the U bus 61,
This is a so-called load bus, which is a dedicated bus to which the data of the RAM 7 and the I / O buffer 8 are sent.
From the viewpoint of the register group 5, this is a dedicated bus for receiving data.

The data bus constituted by the U bus 61 and the L bus 62 has twice the number of wires of a normal data bus here. By using these two buses, the CPU 1 can exchange data with the RAM 7 and the I / O buffer 8 in one machine cycle in one machine cycle.

Next, the operation will be described with reference to FIG. In addition, in FIG. 2, one machine cycle will be described as having a cycle of six clocks. RAM7 and I
The selection of any one of the / O buffers 8 is performed by an address signal from the CPU 1. This selection is the same as the conventional one and is a general technique, and therefore its explanation is omitted.

First, CPU 1 to RAM 7 or I /
The process of transferring data to the O buffer 8 will be described below.
The CPU 1 controls the control signal 10a on the control bus 64 at the rising edge of the second clock of one machine cycle.
Is set to a HIGH level (hereinafter "H"), and the data 9a of a predetermined register of the register group 5 is sent to the U bus 61. Then, the data for two clocks is held on the U-bus 61, and the control signal 10a is lowered at the rising timing of the fourth clock to be set to the LOW level (hereinafter "L"). The data on the U bus 61 is written in the RAM 7 or the I / O buffer 8 at the timing of "L". That is, the control signal 10a is "L".
R to generate a write signal directly or corresponding to
Write control of the AM 7 or the I / O buffer 8 is performed.
The timing of setting the control signal 10a to "L" is also the timing of stopping the generation of the control signal.

Therefore, the data 9a on the U bus 61 is surely transferred to the RAM 7 or the I / O buffer 8 at the timing of two clocks of the fourth clock and the fifth clock. 6th clock after that (precharge period 13)
Then, the internal bus 6 is precharged, and each line of the internal bus 6 is charged.

Next, the RAM 7 or the I / O buffer 8
The process of transferring data from the CPU 1 to the CPU 1 will be described. This is simultaneously performed at the same timing as above.
However, the bus used at this time is not the U bus 61 but the L bus 62. Therefore, even if the timing is the same, the data on the buses do not overlap. That is,
As shown in FIG. 2, the CPU 1 controls the control bus 64 at the rising edge of the second clock in the same one machine cycle.
Raise the upper control signal 10b to "H", R
Data in the AM7 or I / O buffer 8 is transferred to the L bus 62
Send to. Then, the data 9b for two clocks is held on the L bus 62, and the control signal 10b is lowered to "L" at the rising timing of the fourth clock. Data 9b is written in the selected register of the register group 5 at the timing of "L". The timing of setting the control signal 10b to "L" is also the timing of stopping the generation of the control signal. Similarly to the above, the data on the L bus 62 is reliably transferred to a predetermined register of the register group 5 at the timing of two clocks of the fourth clock and the fifth clock. Then, the internal bus 6 is precharged at the sixth clock.

When there is a data exchange command, data confusion does not occur even if the above control is performed at the same timing within the same one machine cycle, that is, at the rising and falling timings of the control signals 10a and 10b. In other words, the control signals 10a and 10b
Even if both are generated at the same time, since the bus to which the data is transmitted is different from the U bus 61 and the L bus 62, there is no problem of confusing the data. In addition, RAM7 and I / O
When the buffer 8 and the selected register of the register group 5 receive data, the control signal 10
Even if the data is received at the same timing shown as the fall timings of a and 10b, the data is received from different buses, so that the data does not overlap on the bus. Therefore, even if the other party (RAM 7 or I / O buffer 8) to which the register of the register group 5 of the CPU 1 transfers and the other party (RAM 7 or I / O buffer 8) that the register of the register group 5 receives are the same target. Good. This is because the data of these circuits is received from another bus at the timing after sending the data to the data bus.

As described above, by providing two data buses, data can be bidirectionally exchanged between the register group of the CPU 1 and the RAM 7 or the I / O buffer 8 in the same one machine cycle. .. Therefore, CP
The data exchange between the register group 5 of U1 and either the RAM 7 or the I / O buffer 8 can be completed within one machine cycle. Further, the RAM 7 or the I / O buffer 8 is connected to each other via the internal register of the CPU 1, which enables data exchange processing in a short period of 2 machine cycles.

By the way, here, the data bus has two systems, but even if two system bus lines are provided, the control timing for exchanging data is constant and can be performed simultaneously as described above. The system wiring and circuits can be simplified. Therefore, the increase of the bus lines for one system can be offset by the simplification of the circuit, and has almost no effect on the layout of other circuits.

In the embodiment, one machine cycle is 6
Although a clock is used, one machine cycle may be composed of four clocks if it is not necessary to take two clocks for holding data. Further, if one clock for precharging or the like is unnecessary, one machine cycle can be three clocks. Normally, the machine cycle of a one-chip microcomputer is one cycle from 3 clocks to 6 clocks, so the present invention can be applied to such a microcomputer. Needless to say, the same applies to the case where one machine cycle is one cycle with more clocks. Although the CPU of the embodiment is connected to the bus via a certain register selected from the register group, the certain register may be selected by the CPU or may be a specific register. Further, in the present invention, it goes without saying that this register group may be one register. In the embodiment, RA
One M7 or one I / O buffer 8 is provided, but it goes without saying that a plurality of these may be provided.

[0018]

As can be understood from the above description, according to the present invention, data can be simultaneously sent to the internal register and the RAM or I / O buffer bus at a certain timing within one machine cycle, and , It is possible to take in the data from the bus by the internal register and the RAM or I / O buffer at another timing at the same time.
Data exchange processing can be performed within the period of one machine cycle, and the processing speed of the CPU can be improved. In this case, the hardware can be simplified by setting the timing of loading the data on the bus to the same timing within one machine cycle. Therefore, even if the data bus has two systems, the increase in one system is offset by the simplification of the wiring and circuits of the control system, and the layout of other circuits is hardly affected.

[Brief description of drawings]

FIG. 1 is a block diagram of a one-chip microcomputer to which the present invention is applied.

FIG. 2 is a timing chart of the processing of the data exchange instruction.

FIG. 3 is a timing chart of processing of a conventional data exchange instruction.

[Explanation of symbols]

1 ... Central processor (CPU), 2 ... ROM, 3
... Arithmetic operation circuit (ALU), 4 ... Controller, 5 ... Register group, 6 ... Internal bus, 7 ... RAM, 8 ... I / O buffer, 9a, 9b ... Data on bus, 10a, 10b ...
Control signals, 10 ... One-chip microcomputer, 61 ... U bus, 62 ... L bus, 63 ... Address bus, 64 ... Control bus.

Claims (1)

[Claims] 1. A one-chip microcomputer having the following configuration. A processor having a register connected to a bus including a data bus, and an R connected to the data bus
AM and an I / O buffer connected to the data bus, wherein the data bus comprises a first bus for sending data to the register and a second bus for receiving data from the register. In the data exchange process, the processor sends the data of the register to a second bus in response to a first clock timing of one machine cycle and the RAM.
And controlling to send any data in the I / O buffer to the first bus.