JPH02307149A - Direct memory access control system - Google Patents

Abstract

PURPOSE:To transfer data at a high speed by performing the transfer of data in a single machine cycle between a main memory and an input/output memory without latching the data to be transferred. CONSTITUTION:A computer system consists of a main memory 1, a direct mem ory access controller (DMAC) 2, the input/output devices (input/output memories) 3a - 3c, a processor MPU 4 such as microprocessor and an address latch 5. In such a constitution, a 1st address is sent to the memory 1 together with a 2nd address sent to the devices 3a - 3c respectively in a single machine cycle after discrimination of both addresses carried out via the control signal lines 7 and 8. Then the data are transferred in a single machine cycle between the addresses shown by the 1st and 2nd addresses. In such a way, the transfer of data is attained in a single machine cycle and therefore the data transfer speed is increased.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a direct memory access control method.

In particular, the present invention relates to a direct memory access control method in which a common bus is connected between a memory and an input/output device to control data transfer between the memory and the input/output device.

[Conventional technology]

Conventionally, in computer systems, in order to perform high-speed data transfer between input/output devices and memory, direct control devices have been used as control devices that directly control data transfer between storage devices and human output buffer memories without the intervention of processing devices. A memory access control device (hereinafter abbreviated as DMA control device) is used.

This type of DMA control device independently controls data transfer without the intervention of a processing device, and is therefore used in devices that need to process a large amount of data at high speed. The DMA control device transfers data between the memory connected to the common bus (data path, address bus) and the input/output device (human output buffer memory), so in a normal configuration, the data register, transfer source address The transfer source address register specifies the transfer source address, the transfer data is loaded from the transfer source into the data register, the transfer destination address is specified in the transfer destination address register, and the data is transferred. Transfer the transfer data from the register to the transfer destination.

Therefore, it takes one machine cycle to specify the transfer source address in the transfer source address register and import the transfer data from the transfer source into the data register, and also to specify the transfer destination address in the next transfer destination address register. To transfer data from the data register to the transfer destination by specifying the
It takes one machine cycle. Therefore, it takes two machine cycles to transfer data, making it impossible to transfer one word of data in one machine cycle.On the other hand, in order to transfer data even faster, For example, as described in Japanese Patent Application Laid-Open No. 63-103351, an address conversion circuit is provided in the secondary storage device (input/output memory), and the address sent by the DMA control device is
By supplying the address to the main memory, converting the address in an address conversion circuit, and supplying it to the secondary memory, the same address can specify multiple different addresses (transfer source address, transfer destination address). Some machines transfer data between the main memory and the secondary memory using machine cycles.

In addition, examples of devices that perform DMA control using a DMA control device that outputs address data in time series on the same signal line (address bus) include JP-A No. 63-98755.
There is a DMA device described in the above publication. This DMA
In the control device, the address data that the DMA control device outputs in time series on the same signal line is distributed to the first bus and the second bus by the selector, and the data latch circuit is connected between the first bus and the second bus. A first memory connected to the first bus and a second memory connected to the second bus
This is a DMA control device that transfers data to and from memory. According to this DMA control device, the address output by the DMA control device is first output to the first bus using the selector, data from the first memory is once stored in the buffer (data latch circuit), and After switching to D
The MA control device outputs an address to the second bus, writes the data stored in the buffer to the second memory, and performs data transfer between the first memory and the second memory.

[Problem to be solved by the invention]

By the way, the conventional DMA control device described above has the following problems of the fifth order. For example, in the former DMA control device (Japanese Unexamined Patent Publication No. 63-103351), one word of data can be transferred in one machine cycle, but the transfer destination secondary storage device (input/output device; input/output memory ), an address conversion circuit is required, and initial data must be set in the address conversion circuit before data transfer starts. For example, if multiple secondary storage devices (input/output devices) A system with such a configuration has a problem in that the overhead becomes large.

Furthermore, the latter DMA device (Japanese Unexamined Patent Publication No. 63-98755) transfers data between the first memory and the second memory.
Since the systems separated by the first bus system and the second bus system are connected by a data latch circuit, data transfer is performed in two machine cycles, and since a buffer is used in the middle, the transfer time is There are problems in that the DMA control circuit is complicated.

The present invention has been made to solve the above problems.

An object of the present invention is to provide a direct memory access control method that allows data transfer between a memory and an input/output device during one machine cycle.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a direct memory access control method in which a memory and an input/output device are connected to a common data bus, and a data transfer control between the memory and the input/output device is controlled. During the cycle, a first address is sent to the memory side and a second address is sent to the input/output device side, distinguished by a control signal line, and between the address indicated by the first address and the address indicated by the second address. The data transfer is performed during one machine cycle.

[Effect]

According to the above means, the direct memory access control that connects the memory and the input/output device to a common data bus and controls the data transfer between the memory and the input/output device is performed by controlling the control signal during one machine cycle. The first one is on the memory side, distinguished by a line.
At the same time as sending the address, a second address is sent to the input/output device side, and data transfer between the address indicated by the first address and the address indicated by the second address is performed during one machine cycle.

Thereby, data transfer between the memory and the input/output device can be performed in one machine cycle without making any circuit changes to the memory and the input/output device. The direct memory access control device that performs direct memory access control sends first address data to the memory side and sends second address data to the input/output device side, distinguishing them by control signal lines during one machine cycle. do. The signals on the control signal line for distinguishing and transmitting the first address data and the second address data are, for example, a local control signal that controls the memory side and a system control signal that controls the input/output device side, These signals are output separately and the direct memory access controller controls two devices simultaneously (during one machine cycle): memory and input/output device (input/output memory).

A direct memory access control device, for example, sends out first address data and second address data by distinguishing them by a control signal line in order to give two different addresses to a memory and an input/output device during one machine cycle. One of the address data that is sent out first, for example, the first address data, is latched by an address latch and is valid for one machine cycle together with the second address data that is sent out later. Therefore, in order to provide separate addresses to the memory side and the input/output device side, an address latch is provided at a separate location between the memory side and the input/output device side.

For example, an address latch is provided between a local address bus on the memory side and a system address bus on the input/output device side. When extending the local address bus and connecting it to an input/output device, an address latch is provided in the input/output device.

Further, when the input/output device side and the memory side are separated in the direct memory access control device, an address latch is provided in the direct memory access control device.

According to this DMA control system, data transfer can be performed in one machine cycle, so high-speed data transfer can be performed, and processing control of data transfer can also be easily performed.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

Note that throughout the explanation of the embodiments, the same elements are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 1 is a block diagram showing the configuration of a computer system having a direct memory access control device according to an embodiment of the present invention. In FIG. 1, 1 is a main memory, 2 is a direct memory access controller (DMAC), and 3a, 3b.

3c is an input/output device including an input/output memory (output cover memory), and 4 is a processing device such as a microprocessor (MP
U), 5 is an address latch, 6 is a commonly connected data bus, 7 is a local control signal line, 8 is a system control signal line, 9 is a local address bus, and 10 is a system address bus.

Each device that transfers data in the computer system is connected to the data bus 6 in common. That is, a main memory 1, a direct memory access control device (hereinafter referred to as DMAC) 2, and an input/output bag W (hereinafter referred to as IO
3a, 3b, and 3c (referred to as memories) and a processing unit (hereinafter referred to as MPU) 4 are commonly connected to a data bus 6, and data is transferred between each device via the data bus 6. The local control signal line 7 is connected to the main memory 1, M
PU4. and DMAC2, and the system control signal line 8 is connected between DMAC2゜IO memory 3a, I
It is commonly connected between the O memory 3b and the O memory 3c. Local address bus 9 connects main memory 1.
MPU4. A system address bus 10 is commonly connected between the DMAC 2 and the address latch 5. It is commonly connected between the IO memory 3a, the IO memory 3b, and the IO memory 3C. The DMAC 2 controls the address latch 5 with a control signal on an address latch control signal line 11. A through latch type latch circuit is used for the address latch 5, and depending on the control signal, it becomes a through state, and address data passes through in both directions as is.

FIG. 2 is a block diagram showing the configuration of main parts of the direct memory access control device. Direct memory access controller (
In the DMAC) 2, 14 is a DMAC control circuit. The DMAC control circuit 14 includes a data bus 6, a local control signal line 7. and receives control data for data transfer from the system control signal line 8 to control the first address update circuit 13a, the second address update circuit 13b, the first address register 12a, and the second address register 12b, and A control signal is sent to the address latch control line 11. Address data from the first address register 12a or the first address register 12b is selected by the selector 15 and output to the local address bus 9. The first address register 12a is supplied with the output from the first address update circuit 13a, and the second address register 12b is supplied with the output from the second address update circuit 13a.
The output from b is supplied.

A local control signal line 7 and a system control signal line 8 are connected to the DMAC control circuit 14, and the DMAC control circuit 14 receives the address sent from the selector 15 via the local control signal line 7 or the system control signal line 8. Sends control signals that distinguish data.

Further, while the control signal on the address latch control signal line 11 sent from the DMAC control circuit 14 is asserted, the selector 15 selects the output from the first address register 12a, and the control signal on the address latch control signal line 11 is asserted. During negation, the selector 15 selects the second address register 12b.
Select the output of As mentioned above, the address latch 5 is a through-latch type latch circuit, and while the control signal of the address latch control signal line 11 is asserted, the contents of the local address bus 9 are passed through to the system address bus 10. At the moment when the control signal of the address latch control signal line 11 is asserted and then negated, the output of the local address bus 9 is fixed and continues to be output to the system address bus 10.

3a, 3b, and 3c are time charts illustrating data transfer by direct memory access control.

First, the case of transferring data from the main memory 1 to the main memory 3a will be described with reference to FIG. 3a. In this case, first, the MPU 4 uses the data bus 6 and the local control signal line 7 to register the first address register 12a.
sets the address (transfer destination address) to which data is to be written in the input/output memory 3a, and sets it in the second address register 12b.

Set the address (transfer source address) from which you want to read data from the main memory 1, and further set the direction of data transfer and the number of bytes to be transferred in the DMAC control circuit 14.
Start 2.

In the DMAC 24, the DMAC control circuit 14 outputs the control signal ADLACH- of the address latch control signal line 11.
By asserting N and controlling selector 15.

The contents of the first address register 12a are output as the address signal MAD-P to the local address bus 9.

Next, when the control signal on the address latch control signal line 11 is negated, the address signal on the local address bus 9 at this time is fixed in the address latch 5. Therefore, from this point on, the address signal AD-P of the system address bus 10 has the fixed contents of the first address register 12a. Further, the address signal MAD-P sent to the local address bus 9 is selected as the content of the second address register 12b under the control of the selector 15 at this time, and the subsequent local address bus 9
The contents of the second address register 12b are output as the address signal MAD-P to the second address register 12b.

Next, on the local control signal line 7, a signal MMEMR-N on the line 7a is asserted, which instructs to output the data at the address indicated by the local address bus 9 to the data bus 6. As a result, the main memory 1 transfers the data at the address indicated by the second address register 12b to the signal DT on the data bus 6.
- Appears as P. Waiting for the data to be output from the main memory 1, the DMAC control circuit 14 transfers the value of the data bus 6 to the address of the memory 3a to 3c indicated by the system address bus 1o on the system control signal line 8. The signal MEMW-N on line 8a which instructs writing is asserted. As a result, the system address bus 10 has the first address register 1 fixed by the address latch 5.
Since the contents of the data bus 2a have been output, a write operation to the data transfer destination is performed based on the contents of the first address register 12a (the contents indicating the address in the IO memory 3a), and after a certain period of time, the contents of the data bus 6 are , are written into the IO memory 3a. After the data has been written to the memory 3a,
1i7a signal MMEMR-N and line 8a signal ME
MW-N is negated to complete a series of data transfer controls, and data transfer control is performed within one machine cycle.

In this way, the data at the address (transfer source) of the main memory 1 indicated by the second address register 12b is written to the address (transfer destination) of the IO memory 3a indicated by the first address register 12a.

FIG. 3b is a diagram showing a time chart when data is transferred from the IO memory 3a to the main memory 1. In this case as well, the DMAC 2 controls the address signals sent to the local address bus 9 and the system address bus 10, determines the address signals output to both address buses, and controls data transfer. . As a result, data from the work memory 3a is transferred to the main memory 1. In this case, data transfer control is
As shown in the time chart of FIG. 3b, the IO memory 3
After setting and confirming the address from a (transfer source) and the address to main memory 1 (transfer destination) in their respective address registers, an instruction to output the contents of the address indicated by this system address bus 10 to the data bus 6. Data transfer is controlled using a control signal MEMR-N on a line 8b for performing the same operation, and a control signal MMEW-N on a line 7b for instructing writing of the contents of the data bus 6 to the address indicated by the local address bus 9. Control of the other series of data transfers is similar to that in the above case.

Further, FIG. 3c is a time chart when the MPU 4 calls data from the main memory 1 or the memory memories 3a to 3c. In the operation of the MPU 4 in this case, as shown in FIG.
The signal is output as is to the system control signal line 8, and the address latch 5 is in a through state. Therefore, by simply changing the addresses output to the local address bus 9 and the system address bus 10, the MPU 4 can also output data from the main memory 1 to the memory 3a to
Data can also be read from 3c using the same procedure. Also, from the MPU 4, the main memory 1. or labor 0
Data writing to the memory 3a=c can be performed in the same manner.

Next, an example of another system configuration of the embodiment according to the present invention will be explained.

FIG. 4 is a block diagram showing the configuration of a computer system according to a second embodiment of the present invention.

In the system configuration shown in Figure 4, the main memory is 1゜MP.
The input/output memories 17a, 17b, and 17c, which are input/output devices connected to U4 and the data bus 6, have address latches 18a, 18b, and 18c, respectively.
is provided. Each of these address latches 18a,
18b.

18c corresponds to the address latch 5 in the system configuration shown in FIG. In order to control each of these address latches 18a, 18b, 18c, the address latch control line 11 is connected to the attendance memory 17a, 18b, 17b, respectively. 17c and commonly supplied with control signals. In this system configuration, these address latches 18a, 18b
, 18c serves as a local address bus 9. Therefore, the system address bus is not used, and each input/output memory 17a.

17b, 17c address latch latch 18a, 1
8b.

A local address bus 9 is connected to 18c. The DMAC 2 has a configuration similar to that shown in FIG. 1 (FIG. 2). In such a system configuration,
In particular, since the address bus does not have to be configured separately into the local address bus 9 and the system address bus 10, the address latches 18a, 18b, 1
8c does not require the use of a through-latch type latch circuit, so it may be advantageous in terms of system configuration.

FIG. 5 is a block diagram showing the configuration of a computer system according to a third embodiment of the present invention.

In FIG. 5, main memory 1. MPU4. The input/output memories 3a, 3b, and 3c are the same as those shown in FIG. 1, respectively. Data bus 6, local control signal line 7.
System control signal line8. Local address bus9. The connection relationship with the system address bus 10 is also the same as the system configuration shown in FIG. In the system configuration shown in FIG. 5, the address latch is included in the DMAC 20. That is, in the first embodiment (FIG. 1), except for the address latch 5, the DMAC 20 outputs an address signal directly to the system address bus 10. FIG. 6 shows a block diagram of the DMAC 20.

FIG. 6 is a block diagram of the main parts showing another example of the configuration of the direct memory access control device. (DMAC) 20, DMAC control circuit 1
4. First address update circuit 13a.

Second address update circuit 13b, first address register 1
2a and the second address register 12b are similar to those in FIG. Here, selector (1
51 (FIG. 2), the second address register 12b is connected directly to the local address bus 9, and the first address register 12a is connected directly to the system address bus 10.

7 and 8 are time charts illustrating data transfer by direct memory access control in the system configuration of FIG. 5.

FIG. 7 is a time chart when data is transferred from the main memory 1 to the IO input/output memory 3a, and
FIG. 8 is a time chart for transferring 18 data from the main memory 18 from the IO input/output memory 3a. The control operations for data transfer in each of these cases are described in Section 3a.
The operation is similar to that in the case shown in FIG. 3 and FIG. 3b, and detailed explanation will be omitted. The DMAC 20 is configured such that the signal lines for the local address bus 9 and the system address bus 10 are separated, and the control of the DMAC control circuit 14 is simplified.

The main points of this embodiment described above can be summarized as follows. That is, (1) main memory, one or more input/output memories, and D
This is data transfer using direct memory access control used in a computer system consisting of a MAC.

(2) Main memory and input/output memory are connected via a data bus, input/output memory and DMAC are connected by system control signals, input/output memory and DMAC are connected by system control signals, and main memory and DMAC are connected by local control signals. The main memory and DMAC are connected by a local address bus, and the input/output memory and DMAC are connected by a system address bus.

(3) During one machine cycle, the DMAC outputs the first address to the system address bus, outputs the second address to the local address bus, and sends the second address to the system address bus through the data bus between the main memory and the factory input/output memory. Data transfer between the address indicated by the first address and the address indicated by the second address is performed within one machine cycle.

(4) The method of outputting an address from the DMAC during one machine cycle is to output the first address directly from the DMAC to the system address bus, and also output the second address to the local address bus (Figure 5). In this case, the number of signal lines (address bus signal lines) connected to the DMAC increases, but the circuit configuration and control circuit of the DMAC are simplified and reliability is improved.

(5) Also, the method of outputting an address from the DMAC during one machine cycle is to separate the local address bus and system address bus and connect them using a through-latch type.

The DMAC sequentially sends out the first address and the second address (Fig. 1). In this case, the number of signal lines connected to the DMAC does not particularly increase, and the increased signal lines are The number of address latch control signal lines increases by only one. For example, constructing a DMAC using an LSI does not require a significant increase in the number of pins, which is highly economical.

(6) If data transfer is not performed using DMA control,
By setting the address latch in a through state and outputting the local control signal to the system control signal by passing it through the DMAC, the MPU connected to the local address bus, local control signal, and data bus can access the main memory. and input/output memory can be accessed in the same way. In this case, there is no need to make any changes to the main memory and input/output memory, and the main memory and input/output memory of the normal configuration can be used as they are.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, in data transfer by direct memory access control, data is transferred between the main memory and the input/output memory during one machine cycle without latching the data to be transferred. Transfer can be performed at high speed. In addition, main memory
There is no need to add special functions to the input/output memory, and the system can be configured using the normally configured main memory and input/output memory, resulting in low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a computer system having a direct memory access control device according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of main parts of the direct memory access control device. 3a, 3b, and 3c are timing charts illustrating data transfer by direct memory access control. FIG. 4 is a block diagram showing the configuration of a computer system according to a second embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of a computer system according to a third embodiment of the present invention. FIG. 6 is a block diagram of main parts showing another example of the configuration of the direct memory access control device. 7 and 8 are timing charts illustrating data transfer by direct memory access control in the system configuration of FIG. 5. 1... Main memory, 2... Direct memory access control device (DMAC), 3 a, 3 b, 3
c- input/output device (input/output memory), 4... processing unit (MPU) such as a microprocessor, 5... address latch, 6... data bus, 7... local control signal line, 8...・System control signal line, 9... Local address bus, 10... System address bus, 11.
...address latch control signal line, 12a...first address register, 12b...second address register, 1
3a... First address update circuit, 13b... Second address update circuit, 14... DMAC control circuit, 15-
...Selector, 17a, 17b, 17c...
・I/O device (input/output memory), 18a, 18b
, 18C... address latch, 20... direct memory access control device (DMAC).

Claims (1)

[Claims] 1. In a direct memory access control method that connects memory and an input/output device to a common data bus and controls data transfer between the memory and the input/output device, , a first address is sent to the memory side, and a second address is sent to the input/output device side, separated by a control signal line, and data transfer between the address indicated by the first address and the address indicated by the second address is performed. A direct memory access control method that is characterized by being performed during one machine cycle. 2. A memory, an input/output device, a data bus that commonly connects the memory and the input/output device, a first address bus that supplies address data to the memory side, and a second address bus that supplies address data to the input/output device side. An address bus, an address latch connected between the first address bus and the second address bus, and an input/output device that sends the first address data to the memory side by distinguishing it by a control signal line during one machine cycle. and a direct memory access control device that sends out second address data on the side, and latches the second address data of the transfer source or the transfer destination given to the input/output device by the control signal line in the address latch. data transfer control between the address indicated by the first address data and the address indicated by the second address data during one machine cycle between the memory and the input/output device. Direct memory access control method. 3. A memory, an input/output device, a data bus that commonly connects the memory and the input/output device, a first address bus that supplies address data to the memory side, and a second address bus that supplies address data to the input/output device side. It is connected to an address bus, a first address bus, and a second address bus, and during one machine cycle, the first address data is sent to the first address bus while being distinguished by a control signal line, and the first address data is sent to the second address bus. and a direct memory access control device that sends out second address data, and between the address indicated by the first address data and the address indicated by the second address data, between the memory and the input/output device during one machine cycle. A direct memory access control method characterized by controlling data transfer. 4. A memory, an input/output device, a data bus that commonly connects the memory and the input/output device, a first address bus that supplies address data to the memory side, and a common bus that supplies address data to the memory and the input/output device. address bus and
An address latch is provided in each input/output device connected to the address bus to latch address data, and an address latch is provided in each input/output device connected to the address bus, and the first address data is sent to the memory side by a control signal line during one machine cycle, and the input/output The device side is equipped with a direct memory access control device that sends out second address data, and the second address data of the transfer source or transfer destination given to the input/output device is latched by the address latch via the control signal line, and each input/output device is It is characterized in that it is supplied to an output device to control data transfer between an address indicated by the first address data and an address indicated by the second address data during one machine cycle between the memory and the input/output device. direct memory access control method. 5. The above-mentioned claim 1, wherein one or more input/output devices are provided and are connected to a common data bus and include an input/output memory commonly connected to an address bus on the input/output device side. A direct memory access control method according to claim 4.