JPH02187854A - Dual port memory - Google Patents

Abstract

PURPOSE:To stably perform an operation with a few number of signal lines by constituting a data monitoring circuit in such a way that a serial address is converted to a parallel address by a S/P conversion circuit, and parallel data is converted to serial data by a P/S conversion circuit. CONSTITUTION:The S/P conversion circuit 8 in the data monitoring circuit 9 converts the serial address outputted from an external monitoring tool to the parallel address, and supplies it to a memory array 1. The P/S conversion circuit 7 reads out data stored in an address designated by the circuit 8, and converts it to the serial data, and outputs it to the external monitoring tool. Thereby, it is possible to easily monitor the data by only connecting the monitoring tool without stopping the operation of a processor or without drawing out a large number of signal lines from the processor to the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to data transfer between two processors, and particularly to a dual port memory used for data transfer.

(Prior Art) Conventionally, this type of dual-port memory consists of a memory array for storing data and an arbitration logic for arbitrating memory array access requests from two processors. ing.

(Problems to be Solved by the Invention) The conventional dual port memory described above has a data monitor circuit composed of an S/P conversion circuit and a P/S conversion circuit for monitoring data stored in the memory array. Not provided.

Therefore, when dual port memory is used to exchange data between two processors, in order to monitor the data being exchanged between the two processors, it is necessary to use one of the two processors. The first method is to connect and monitor a debug tool such as an emulator, and the second method is to pull out all the data lines, address lines, and control lines of the processor to the outside and connect a monitor tool there for monitoring. The disadvantage of the latter is that it is necessary to temporarily stop the operation of the processor each time it is monitored, and the latter requires a huge number of signal lines to be drawn out (approximately 40 for a 16-bit processor). Also, there are disadvantages such as an increased possibility of malfunction of the processor due to noise.

An object of the present invention is to convert a serial address into a parallel address using an S/P conversion circuit, and convert parallel data into serial data using a P/S conversion circuit in a dual port memory used for exchanging data between two processors. It is an object of the present invention to provide a dual port memory which eliminates the above-mentioned drawbacks by converting the data into a data monitor circuit, and which is configured to operate stably without increasing the number of signal lines.

(Means for Solving the Problems) A dual port memory according to the present invention includes a memory array,
It includes an arbitration logic, a pair of data buffers, a pair of address buffers, and a data monitor circuit, and is used for data exchange between two processors.

The memory array is for storing data, and the arbitration logic is the T-component that controls the reading of the contents of the memory array.

The pair of data buffers are for respectively transmitting and receiving data to and from two externally provided processors.

The pair of address buffers are for sending and receiving address information to and from the two processors.

The data monitor circuit inputs address information from an external monitor tool and outputs data from the memory array to the monitor tool. The data monitor circuit is an S/
It is a T-sized device that is equipped with a P conversion circuit and a P/S conversion circuit for converting parallel data into serial data.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a dual port memory according to the present invention.

In FIG. 1, 1 is a memory array, 2 is an arbitration logic, 3.5 is a data buffer, and 4 is a data buffer.
．． 6 is an address buffer, 7 is a P/S conversion circuit, 8 is an S/P conversion circuit, and 9 is a data monitor circuit.

When the memory array 1 receives a data convolution request from an external processor, it operates under the control of the arbitration logic 2, and passes through the address buffer (L) 4 or the address buffer (R) 6 to the external processor. Data input from an external processor through data buffer (L) 3 or data buffer (R) 5 is stored at an address specified by . Furthermore, when there is a request for continuous data output from an external processor, the memory array 1 operates under the control of the arbitration logic 2, and the address buffer (L) 4,
Alternatively, data stored at an address specified through the address buffer (几) 6 is outputted to an external processor through the data buffer (L) 3 or the data buffer (R) 5.

The data monitor circuit 9 includes an S/P conversion circuit 8 and a P/S conversion circuit 7. The S/P conversion circuit 8 is
This is for converting the serial address output from an external monitoring tool into a parallel address and supplying it to the memory array 1. The P/S conversion circuit 7 reads out the data stored in the address specified by the S/P conversion circuit 8 from among the data stored in the memory array 1, converts it into serial data, and outputs it to an external monitoring tool. It is for the purpose of

DATA (1-n) LIO and DA'l'A (1-
n) R17 is n data signal lines used for exchanging data with an external processor.

ADR(1~m)Ll 1 and ADR(1~m)R1
Reference numeral 8 denotes m address signal lines for inputting addresses designated from an external processor.

INTL 12 and IN'l' 19 allow an external processor to process data 1. When reading and writing are completed,
This is an interrupt signal line for notifying the other party's processor.

BUSYLI 3 and BUSYR20 are busy signal lines indicating that the other processor is accessing the memory array 1. CELl 4 and CER21 are
This is a chip enable signal line on which a chip enable signal is output when an external processor accesses the contents of the dual port memory according to the present invention. 0EL15
and OE 22 are output enable signal lines for enabling the data buffer (L) 3 or data buffer (R) 5 when an external processor reads data. R/WL16 and R/WR2
A read/write signal line 3 carries a read/write signal output when an external processor performs reading and writing.

READ8TA T24 has external monitor tool P/
This is a read start signal line for activating the S conversion circuit 7. 8DATA25 is a signal line for serial data that the P/S conversion circuit 7 outputs to an external monitor tool.

R, EADEND 26 is a read end signal line indicating the end of the operation of the P/S conversion circuit 7. CLOCK27 is a clock signal line that carries a clock supplied from the monitor tool to the P/S conversion circuit 7 and the 8/P conversion circuit 8. 8ADR28 is a serial address signal line carrying a serial address output from an external monitor tool.

ADR8ET2 old, S/P conversion circuit 8 activation signal line,
BU8Y30 is a busy signal indicating that an external processor is accessing memory array l.

FIG. 2 is a timing chart showing the operating status of each reference signal on the signal sets 24 to 30 of each reference signal connected to an external monitoring tool.

CL on signal line 27 by ADR8BT on signal line 29
When inputting SAD on signal line 28 and inputting EADSTA on signal line 24 in synchronization with OCK, signal 1
8AD11 on 28. Data 5DATA corresponding to the address specified by is output onto the signal line 25 in synchronization with CLOCK on the signal line 27. Subsequently, READEND indicating the end of the output of 5DATA is output on the signal line 26. When REAI) S'l'ART is output on signal &24, if BUI9Y is on signal line 30, output of S I) A T A on signal line 25 is temporarily awaited. Further, since the address of the 87P conversion circuit 8 is incremented by the RE A I) EN D on the signal line 26, data at one address can be continuously read by repeatedly outputting the READSTAR signal.

FIG. 3 is a block diagram showing an embodiment in which a dual port memory with a data monitor circuit according to the invention is used in a digital signal processing device.

In Figure 3, 31 is an A/D converter, 32.34
．． 36 are first to third digital signal processing processors, 33 and 35 are first and second dual port memories, respectively, 37 is a D/A converter, 38 is a monitor tool, and 39 is a host processor.

By connecting the monitor tool 38 to the first and second dual port memories 33, it is possible to monitor the signal processing results of the first and second digital signal processing processors 32j34.

(Effects of the Invention) As explained above, the present invention provides a dual port memory used for exchanging data between two processors.
By converting the serial address into a parallel address using the S/P conversion circuit and converting the parallel data into serial data using the P/S conversion circuit to form a data monitor circuit, the data can be processed without stopping the operation of the processor. This has the advantage that data can be easily monitored simply by connecting a monitor tool to the dual-port memory without drawing out a huge number of signal lines from the processor to the outside.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a dual port memory according to the present invention. FIG. 2 is a timing chart showing the operation of the data monitor circuit shown in FIG. FIG. 3 is a block diagram showing an example of application of the dual port memory according to the present invention to a digital signal processing device. 1...Memory array 2...Arbitration logic 3.5...Data buffer 4.6...Address buffer 7...P/S conversion circuit 8...S/P conversion circuit 9... Data monitor circuits 10 to 30...Signal line 31...A/D converter 32.34.36...Digital signal processing processor 3
3.35...Dual port memory 37...D/A
Converter 38...Monitor tool 39...Host processor Patent applicant NEC Corporation

Claims (1)

[Claims] A memory array for storing data, an arbitration logic for controlling reading of the contents of the memory array, and a pair of data for transmitting and receiving data to and from two externally provided processors, respectively. a buffer, a pair of address buffers for respectively sending and receiving address information to and from the two processors, and data for inputting address information from an external monitor tool and outputting data from the memory array to the monitor tool. a monitor circuit, and the data monitor circuit includes an S/P conversion circuit for converting a serial address into a parallel address, and a P/S conversion circuit for converting parallel data into serial data. Dual port memory characterized by its configuration.