JPS61217858A - Data transmitting device - Google Patents

Data transmitting device

Info

Publication number
JPS61217858A
JPS61217858A JP5848185A JP5848185A JPS61217858A JP S61217858 A JPS61217858 A JP S61217858A JP 5848185 A JP5848185 A JP 5848185A JP 5848185 A JP5848185 A JP 5848185A JP S61217858 A JPS61217858 A JP S61217858A
Authority
JP
Japan
Prior art keywords
data
buffer memory
transmission
memories
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5848185A
Other languages
Japanese (ja)
Inventor
Takeshi Hiroki
広木　武
Mitsuru Kudo
満 工藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5848185A priority Critical patent/JPS61217858A/en
Publication of JPS61217858A publication Critical patent/JPS61217858A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

Abstract

PURPOSE:To read and write data independently and in parallel with each other by providing plural buffer memories within a data transmitting device to use one of both buffer memories for writing in a read mode of the other memory and switching these memories alternately. CONSTITUTION:The data given from a CPU 100 are sent to a transmission line 120 via a buffer memory 130 and a transmission control circuit 140 and then received in a reverse procedure. Then these data are stored temporarily in a bus buffer memory 290 and then written to one of two transmission buffer memories 200 and 201 under the control of memory access control circuits 260 and 270. Here the data on the circuit 140 are stored in the other buffer memory. Both control circuits 260 and 270 are actuated by a flip-flop 261 when the writing action is through. Then the memories 200 and 201 are switched to the opposite side respectively.

Description

【発明の詳細な説明】 、　　〔発明の利用分野〕 本発明は、複数のデータ処理装置間、データ処理装置と
入出力装置間のデータ交換を行なうに際し、％に、バッ
ファメモリを介して、特定単位数のデータをサイクリッ
クに交換するようなシステムに好適な、データ伝送装置
に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a method for exchanging data between a plurality of data processing devices or between a data processing device and an input/output device. The present invention relates to a data transmission device suitable for a system that cyclically exchanges units of data.

〔発明の背景〕[Background of the invention]

複数の処理装置間で、特定単位数のデータ交換を行う従
来例として、複数の処理装置の間に、いずれの処理装置
からもアクセス可能なバッファメモリを設けて行う方式
が知られている。2. Description of the Related Art As a conventional example of exchanging a specific number of units of data between a plurality of processing devices, a method is known in which a buffer memory that can be accessed from any of the processing devices is provided between the plurality of processing devices.

このバッファメモリへのアクセス制御方式として、特開
昭５９−１１４６５９号公報、特開昭５８−２９０６０
号公報に示されるように、複数の処理装置からのアクセ
ス要求を競合制御して、一方の処理装置がバッファメモ
リをアクセス中は他方は待機するという方式がとられて
いる。As an access control method to this buffer memory, Japanese Patent Laid-Open No. 59-114659 and Japanese Patent Laid-Open No. 58-29060
As shown in the publication, a method is adopted in which access requests from a plurality of processing devices are competitively controlled, and while one processing device is accessing a buffer memory, the other processing device is on standby.

このような方式は、簡単な回路で、バッファメモリを介
し九データ交換を実現できるが、待ち時間が発生する禽
め、全体として処理時間が長くなるという問題がある。Although such a method can realize data exchange through a buffer memory with a simple circuit, there is a problem that waiting time occurs and the overall processing time becomes longer.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、複数のデータ処理装置間、デ−タ処理
装置と入出力装置間のデータ交換を、高速に行うことが
可能な、データ伝送装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmission device capable of exchanging data between a plurality of data processing devices and between a data processing device and an input/output device at high speed.

〔発明の概要〕[Summary of the invention]

本発明は、複数のデータ処理装置間又はデータ処理装置
と入出力装置間のデータ交換を行うデータ伝送装置にお
いて、その内部に、複数のバッファメモリを設け、一方
は、データ伝送制御部に、他一方・ば、データをアクセ
スする処理装置側に占有させることにより、それぞれの
読み出し、書き込みを独立して並行に行わせることで、
処理時間の短縮を計るものである。The present invention provides a data transmission device that exchanges data between a plurality of data processing devices or between a data processing device and an input/output device. On the other hand, by making the processing device that accesses the data exclusive, each read and write operation can be performed independently and in parallel.
This is intended to shorten processing time.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第１図は、本発明を適用するシステムの構成の一例であ
る。図において、Ｚｏｏ、１０１は、データ処理装置（
以下、ＣＰＵ）、１０２は、入出力装置（以下、工１０
）である。１１０，１１３は、本発明に係るデータ伝送
装置、１２０，１２１は伝送路、１３０〜１３３は、本
発明のポイントとなるデータ記憶部（以下バッファメモ
リ）、１４０〜１４３は伝送制御回路である。＃ｃ１図
において、ＣＰＵ１００とＣＰＵｌ０Ｉの間のデータ交
換の流れを説明すると以下のようになる。FIG. 1 shows an example of the configuration of a system to which the present invention is applied. In the figure, Zoo 101 is a data processing device (
102 is an input/output device (hereinafter referred to as CPU), and 102 is an input/output device (hereinafter referred to as
). 110 and 113 are data transmission devices according to the present invention, 120 and 121 are transmission lines, 130 to 133 are data storage units (hereinafter referred to as buffer memories) which are the key points of the present invention, and 140 to 143 are transmission control circuits. In FIG. #c1, the flow of data exchange between the CPU 100 and CPUl0I will be explained as follows.

まず、ＣＰＵ１００は、ＣＰＵ１０１に報告すべきデー
タを、バッファメモリ１３０に書き込む。First, the CPU 100 writes data to be reported to the CPU 101 into the buffer memory 130.

伝送制御回路１４０は、バッファメモＩＪ　１３０に書
き込まれたデータを、一定周期で、サイクリックに、デ
ータ伝送装置１１１に対し送信する。データ伝送装置１
１１内では、同１１０から送られてくるデータをバッフ
ァメモリ１３２に格納する。The transmission control circuit 140 cyclically transmits the data written in the buffer memory IJ 130 to the data transmission device 111 at regular intervals. Data transmission device 1
11 stores data sent from the same 110 in a buffer memory 132.

ＣＰＵＩ　Ｑｌは、バッファメモリ１３２の内容を読み
出すことにより、ＣＰＵ１００からのデータを受ける。CPUI Ql receives data from CPU 100 by reading the contents of buffer memory 132.

を次、ＣＰＵＩ　Ｏ１からＣＰＵＩ　ＯＯに対してデー
タを送る場合は、バッフアメモリ１３２伝送制御回路１
４２，１４０、バッファメモ１７１３０を介して、上記
と同様にデータが流れ、ＣＰＵｌ０ＩからＣＰＵ１００
へとデータが報告される。概ね、以上のようにして、Ｃ
ＰＵ１００と１０１のデータ交換がなされる。Next, when sending data from CPUI O1 to CPUI OO, buffer memory 132 transmission control circuit 1
42, 140, the data flows through the buffer memo 17130 in the same way as above, and is transferred from CPU10I to CPU100.
Data is reported to. Generally, as described above, C
Data is exchanged between the PUs 100 and 101.

第２図は本発明になるデータ転送方式の一例であシ、２
００，２０１は伝送バッファメモリ２１０〜２１３はア
ドレスバスバッファ、２２０〜２２３はデータバスバッ
ファ、２３０，２３１はアドレスバス、２４０，２４１
はデータバス、２５０゜２５１はメモリコントロールバ
ス、２６０，２７０はメモリアクセスコントロール回路
、２６１ａ、状態切替及び保持回路、２９０はパスバッ
ファメモリである。第１図において説明しｔデータの授
受を第２図によシ、詳細に説明する。Figure 2 is an example of the data transfer method according to the present invention.
00, 201 are transmission buffer memories 210-213 are address bus buffers, 220-223 are data bus buffers, 230, 231 are address buses, 240, 241
is a data bus, 250.degree. 251 is a memory control bus, 260 and 270 are memory access control circuits, 261a is a state switching and holding circuit, and 290 is a path buffer memory. The transmission and reception of t data, which will be explained with reference to FIG. 1, will be explained in detail with reference to FIG.

ＣＰＵＩ　００からＣＰＵ１０１に送られるデータは、
パスバッファメモリ２９０に書きこまれる。The data sent from CPU 00 to CPU 101 is
The data is written to the path buffer memory 290.

２６１は、伝送バッファメモリ２００，２０１を、ＣＰ
ＵＩ　ＯＯ側、伝送制御回路１４０側に交互に占有させ
る之めの状態切替、保持回路（以下Ｆ／Ｆ）である。261 connects the transmission buffer memories 200 and 201 to the CP
This is a state switching and holding circuit (hereinafter referred to as F/F) that is alternately occupied by the UI OO side and the transmission control circuit 140 side.

いま、Ｆ’／Ｆ２６１によシ、ＣＰＵ１００側は伝送バ
ッファメモ替２００を占有、伝送制御回路１４０側は、
バッファメモリ２０１を占有するよ／ＩＭ給９くれで論
ふ芝　←Ｐバスバッフ丁丁子モリ２９０．ＣＰＵＩＧＯ
から書き込まれたデータは、伝送バッファメモ１７２０
０に転送される。この時、同２０１には、ＣＰＵ１０１
から送られてくるデータが書き込まれている。Now, for F'/F261, the CPU 100 side occupies the transmission buffer memory change 200, and the transmission control circuit 140 side:
It occupies the buffer memory 201/Image 9 gives me a discussion ←P bus buffer 290. CPUIGO
The data written from the transmission buffer memory 1720
Transferred to 0. At this time, the CPU 101 is
The data sent from is written.

次に、ＣＰＵ１０１から、送られてくるデータが、伝送
バッファメモリ２０１に書き込み完了すると、Ｆ／Ｆ２
６１は、伝送バッファメモリ２０１をＣＰＵ１００側に
占有、同２００を、伝送制御回路１４０に占有させるよ
うに切替える。Next, when the data sent from the CPU 101 is completely written into the transmission buffer memory 201, the F/F 2
61 switches so that the transmission buffer memory 201 is occupied by the CPU 100 and the transmission buffer memory 200 is occupied by the transmission control circuit 140.

この時点で、先に、ＣＰＵ１００から、パスバッファメ
モリ２９Ｇを介して伝送バッファメモリ２００に書き込
まれたデータは、伝送制御回路１４０を介して、ＣＰＵ
１０１に送信される。当該データの送信が完了すると、
伝送制御回路１４０は、今度は、伝送バッファメモリ２
００に対して、ＣＰＵ　１０１から送られてくるデータ
を書き込む。At this point, the data previously written from the CPU 100 to the transmission buffer memory 200 via the path buffer memory 29G is transferred to the transmission buffer memory 200 via the transmission control circuit 140.
101. Once the data has been sent,
The transmission control circuit 140 now controls the transmission buffer memory 2.
The data sent from the CPU 101 is written to 00.

上記の処理と並行して、ＣＰＵ１００は、先にＣＰＵｌ
０Ｉよシ送られてき次データを、パスバッファメモリ２
００を介して、伝送バッファメモリ２０１から読み出す
と同時に、再度ＣＰＵＩＯＩに対する送信データを、バ
スバッファメモリ２９０から、伝送バッファメモＩ７２
０１に書き込む。In parallel with the above processing, the CPU 100 first
The next data sent from 0I is stored in the path buffer memory 2.
00 from the transmission buffer memory 201, and at the same time, the transmission data for the CPUIOI is read again from the bus buffer memory 290 to the transmission buffer memory I72.
Write to 01.

以上のようにして、ＣＰＵ１００側は、伝送バッファメ
モ！Ｊ２００　（２０１）を介し、伝送バッファメモリ
切替前の、ＣＰＵｌ０Ｉからの受信データを読み出し、
切替後に、ＣＰＵｌ０Ｉに送信すべきデータを伝送バッ
ファメモリ２００　（２０１）に書き込む。As described above, the CPU 100 side stores the transmission buffer memo! Read the received data from CPU10I before switching the transmission buffer memory via J200 (201),
After switching, data to be transmitted to CPUl0I is written into transmission buffer memory 200 (201).

これを交互に繰シ返すことによって、ＣＰＵ１００と、
ＣＰＵ１０１のデータ交換がなされる訳である。By repeating this alternately, the CPU 100 and
This means that data is exchanged between the CPUs 101.

以上において、バッファメモｌ７２００，２０１は、常
時、伝送制御回路１４０側、あるいはＣＰＵ１００側に
占有され、並列処理を行うことができる。In the above, the buffer memories 17200 and 201 are always occupied on the transmission control circuit 140 side or the CPU 100 side and can perform parallel processing.

以上の処理を時系列に示したものが第３図である。FIG. 3 shows the above processing in chronological order.

第４図は、第２図に示し次データ伝送装置に、伝送デー
タ異常検出回路４００を設けたものでらる。ｉ、４０１
は切替停止信号である。ＨＤＬＣのような、パケット交
換伝送において、一旦伝送パツファメモリ２００（２０
１）に書き込んだデータが誤シで６つ次場合、伝送デー
タ異常検出回路４００は、伝送バッファメモリの切替停
止信号４１０を、メモリアクセスコントロール回路２６
１に与える。これによって、！ｌデータの入っ友伝送バ
ッファメモリは、ＣＰＵ側に接続されな込友め、ＣＰＵ
側は、誤データを取り込むことがなくなる訳である。FIG. 4 shows the next data transmission device shown in FIG. 2 provided with a transmission data abnormality detection circuit 400. i, 401
is a switching stop signal. In packet switching transmission such as HDLC, the transmission buffer memory 200 (20
1) If the data written in the 6th column is incorrect, the transmission data abnormality detection circuit 400 transmits the transmission buffer memory switching stop signal 410 to the memory access control circuit 26.
Give to 1. by this,! lThe data transfer buffer memory is not connected to the CPU side.
This means that there will be no need to import erroneous data.

第５図に正常時のデータ移動と、異常時のデータ移動の
様子を示す。図中、■は伝送バッファメモリ２００、■
は伝送バッファメモリ２０１を表わしている。FIG. 5 shows data movement during normal times and data movement during abnormal times. In the figure, ■ indicates the transmission buffer memory 200, ■
represents the transmission buffer memory 201.

正常時は、ＴＯ〜Ｔ６で伝送バッファメモリ■。During normal operation, the transmission buffer memory ■ is used from TO to T6.

■に格納され元データは、Ｔ１〜Ｔ６で、ＣＰＵ側に転
送される。The original data stored in (2) is transferred to the CPU side at T1 to T6.

異常時の図は、Ｔ３で伝送バッファメモリに格納され次
データが誤ってい九場合、Ｔ４では、ＣＰＵに対しては
、Ｔ２０時点での正常データが、再度アクセスされ、Ｔ
４にて正常に復帰すると、再び、交互切替によシ、デー
タの更新がされることを示している。The diagram at the time of an abnormality shows that if the next data stored in the transmission buffer memory at T3 is incorrect, then at T4, the normal data at T20 is accessed again to the CPU, and
4 indicates that the data will be updated again by alternating switching when it returns to normal.

冑、本発明は、データ処理装置間のみならず、データ処
理装置を入出力装置間のデータ交換にも適用できる。Furthermore, the present invention can be applied not only to data exchange between data processing devices, but also to data exchange between data processing devices and input/output devices.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、データ処理装置間、データ処理装置と
入出力装置間のデータ交換を、バッファメモリに対する
競合制御による待ち時間なしで実現できる友め、伝送処
理の高速化の効果がある。According to the present invention, data exchange between data processing devices and between a data processing device and an input/output device can be realized without waiting time due to contention control for buffer memories, and there is an effect of speeding up transmission processing.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明を適用し九システムの一例を示す図、第
２図は本発明に係るデータ伝送装置の構成例を示す図、
第３図は本発明のメモリ状態切替の時系列を示す図、第
４図は本発明の変形例を示す図、第５図は第４図におけ
る変形例の動作説明図である。 １００〜１０１・・・データ処理装置（ＣＰＵ）、１１
０〜１１３・・・データ伝送装置、１３０〜１３３・・
・バッファメモリ、１４０〜１４３・・・伝送制御回路
、２００，２０１・・・伝送バッファメモリ。　　　、
ｆ。FIG. 1 is a diagram showing an example of a nine-system system to which the present invention is applied, and FIG. 2 is a diagram showing an example of the configuration of a data transmission device according to the present invention.
FIG. 3 is a diagram showing a time series of memory state switching according to the invention, FIG. 4 is a diagram showing a modification of the invention, and FIG. 5 is an explanatory diagram of the operation of the modification of FIG. 4. 100-101...Data processing unit (CPU), 11
0-113...Data transmission device, 130-133...
- Buffer memory, 140-143...Transmission control circuit, 200, 201...Transmission buffer memory. ,
f.

Claims (1)

【特許請求の範囲】 １、複数のデータ処理装置間又はデータ処理装置と入出
力装置間のデータ交換を行なうデータ伝送装置において
、該データ伝送装置内に複数のバッファメモリを設け、
該複数のバッファメモリのうち一方を読み出しに用いる
場合には、他方を書き込みに用い、前記複数のバッファ
メモリのうち一方を書き込みに用いる場合には他方を読
み出しに用い、バッファメモリを交互に切換えて、デー
タの読み出し及び書き込みを独立して並行に行なうこと
を特徴とするデータ伝送装置。 ２、特許請求の範囲第１項において、前記複数のバッフ
ァメモリはデュアルポートメモリから構成することを特
徴とするデータ伝送装置。[Claims] 1. In a data transmission device that exchanges data between a plurality of data processing devices or between a data processing device and an input/output device, a plurality of buffer memories are provided in the data transmission device,
When one of the plurality of buffer memories is used for reading, the other is used for writing, and when one of the plurality of buffer memories is used for writing, the other is used for reading, and the buffer memories are alternately switched. A data transmission device characterized in that data reading and writing are performed independently and in parallel. 2. The data transmission device according to claim 1, wherein the plurality of buffer memories are comprised of dual port memories.
JP5848185A 1985-03-25 1985-03-25 Data transmitting device Pending JPS61217858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5848185A JPS61217858A (en) 1985-03-25 1985-03-25 Data transmitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5848185A JPS61217858A (en) 1985-03-25 1985-03-25 Data transmitting device

Publications (1)

Publication Number Publication Date
JPS61217858A true JPS61217858A (en) 1986-09-27

Family

ID=13085620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5848185A Pending JPS61217858A (en) 1985-03-25 1985-03-25 Data transmitting device

Country Status (1)

Country Link
JP (1) JPS61217858A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63206855A (en) * 1987-02-23 1988-08-26 Mitsubishi Electric Corp Data transmission equipment
JPS6484942A (en) * 1987-09-25 1989-03-30 Nec Corp Packet buffer control system
JPH0421053A (en) * 1990-05-14 1992-01-24 Komatsu Ltd Asynchronous data transmission device
JPH06259320A (en) * 1993-03-04 1994-09-16 Hitachi Ltd Nonvolatile memory device
JP2006092225A (en) * 2004-09-24 2006-04-06 Fuji Xerox Co Ltd Controller, data transfer controller and data transfer control method
JP2008204623A (en) * 2008-04-07 2008-09-04 Renesas Technology Corp Nonvolatile memory device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63206855A (en) * 1987-02-23 1988-08-26 Mitsubishi Electric Corp Data transmission equipment
JPS6484942A (en) * 1987-09-25 1989-03-30 Nec Corp Packet buffer control system
JPH0421053A (en) * 1990-05-14 1992-01-24 Komatsu Ltd Asynchronous data transmission device
JPH06259320A (en) * 1993-03-04 1994-09-16 Hitachi Ltd Nonvolatile memory device
JP2006092225A (en) * 2004-09-24 2006-04-06 Fuji Xerox Co Ltd Controller, data transfer controller and data transfer control method
JP2008204623A (en) * 2008-04-07 2008-09-04 Renesas Technology Corp Nonvolatile memory device

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