JPH01260562A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To simplify a processing by counting a write signal by DMA transfer from a first microprocessor to a FIFO type memory at the time of writing, and reading out a count value by the I/O input of a second microprocessor at the time of reading. CONSTITUTION:The first (sub) and second (main) microprocessors 3 and 1 and a first-in and first-out (FIFO) type memory 2 are provided, and it is constituted so that the completion of write on the FIFO type memory 2 can be sent from the sub microprocessor 3 to the main microprocessor 1 by an interruption signal. And at the time of writing, the write signal is counted by the DMA transfer from the sub microprocessor 3 to the FIFO type memory 2, and at the time of reading, the count value is read out by the I/O input of the main microprocessor 1. In such a way, the processing can be simplified.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention is of a first-in, first-out type (hereinafter referred to as
It is abbreviated as FIFO. ,) relates to a method for transferring data between information processing devices using memory.

(Prior Art) Conventionally, when performing various types of processing using a microprocessor while performing data communication at high speed, a plurality of microprocessors are used and the processing is distributed to support a high-speed processing system.

(Problems to be Solved by the Invention) In the method of executing processing using a plurality of microprocessors according to the prior art described above, in order to make each microprocessor operate organically, it is necessary to It is necessary for the cabinets to transfer memory data to each other.

Conventionally, the first method for data transfer is to transfer data by DMA using a memory having a shared address space.
and bidirectional parallel in/out type FI
A second method is known in which data is written/read using DMA using an FO type memory.

In the first method, since data is directly transferred between memories without going through the microprocessor, there is a drawback that both microprocessors are temporarily unable to use their respective paths.

In the second method, data is transferred between the FIFO memory and each microprocessor by DMA.
Since the data is transferred using S, the path usage is not similarly restricted. However, it has the disadvantage that the processing is complicated, as the amount of data to be transferred is transferred in advance to the other microprocessor in a fixed format, and then the data is transferred by DMA.

The object of the present invention is to provide first and second microprocessors,
and a FIFO type memory, so that the end of writing to the FIFO type memory can be sent from the first microprocessor to the second microprocessor by an interrupt signal. The first write is counted by DMA transfer to the T10 of the second microprocessor during reading.
It is an object of the present invention to provide a data transfer circuit configured to eliminate the above-mentioned drawbacks and simplify processing by reading a count value from an input.

(Means for Solving the Problems) A data circuit according to the present invention includes first and second microprocessors, FIFO memories, and first and second I/O
10 control circuits and a counter.

The FIFO type memory is located between the first and second microprocessors and is used to exchange data.

The first I10 control circuit transmits the FI signal from the first microprocessor to the second microprocessor by an interrupt signal.
This is used to send out the completion of writing to the FO type memory.

The purpose of this counter is to count the write signal as a clock input when writing by DMA transfer from the first microprocessor to the F'1FO type memory.

The second T10 circuit is for reading the count value of the counter by the T10 input of the second microprocessor.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a data transfer circuit according to the present invention.

In Figure 1, 1 is the main microprocessor, 2 is the F
3 is a sub-microprocessor, 4 is a counter, and 5 and 6 are I10 suppression circuits.

The I10 control circuit 5 is the I10 of the main microprocessor 1.
The I10 control circuit 6 is the I10 control circuit of the sub-microprocessor 3.

Further, 71 and 72 are data buses, respectively, 81 and 82 are address buses, 9 is a signal line carrying the write + signal in the DMA transfer example of the sub microprocessor 3, and 10 is a read signal in the DMA transfer of the main microprocessor 1. It is a signal line that carries

In FIG. 1, it is assumed that, for example, the microprocessor 3 writes data to the FIFO memory 112 and transfers it from the FIFO memory 2 to the main microprocessor 1. As a result, the sub microprocessor 3
Data is written to the FIFO type memory 2 using the A transfer method. At this time, the write signal WR to the FIFO type memory 2 is input as a clock to the counter 4. Therefore, FI
The number of data written to the FO memory 2 is counted by a counter 4. , the DMA transfer is completed and the data is P
When writing to the IF'0 type memory 2 is completed, the sub microprocessor 3 sends an interrupt signal to the main microprocessor 1 from the I10 control circuit 6 to notify the end of DMA.

DMA from sub microprocessor 3 by interrupt signal
Upon detecting the end of the transfer, the main microprocessor 1 reads the count value of the counter 4 from the I10 control circuit 5, inputs the amount of data sent out by the sub microgrocer 3, and stores the data of the number of input values in the FIFO memory. 2 using the DMA transfer method.

(Effects of the Invention) As explained above, the present invention provides the first and second microprocessors, the entire F'IFO type memory, and the first microprocessor.
The first microprocessor is configured to be able to send the completion of writing to the FIFO type memory to the second microprocessor using an interrupt signal, and when writing, the first microprocessor performs the writing by DMA transfer from the first microprocessor to the FIFO type memory. By counting signals and reading the count value using the I/O input of the second microprocessor, data can be easily transferred with a simple configuration, resulting in high reliability and low cost due to simplified processing. This has the effect of making it possible to realize

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a data transfer circuit according to the present invention. 1... Own microprocessor 2... FIFO type memory 4... Counter 5.6... I10 control circuit? 1.72.81.82@-bus 9.10...signal line

Claims (1)

[Claims] a first microprocessor and a second microprocessor; a first-in first-out memory for exchanging data between the first and second microprocessors; a first I/O control circuit for transmitting the completion of writing to the first-in, first-out type memory by an interrupt signal from the first microprocessor to the second microprocessor; - A counter for counting the write signal as a clock input when writing by DMA transfer to the first-out memory, and an I/O of the second microprocessor.
A data transfer circuit comprising: a second I/O control circuit for reading out the count value of the counter in response to an input.