JPS6048566A - Memory bus access system - Google Patents

Abstract

PURPOSE:To shorten a bus occupancy time, and to improve a processing capacity by providing address and data use registers between a data transfer device of an information processing device having a function for executing an access directly to a memory, and a memory bus. CONSTITUTION:An address register AREG3 and a data use register DREG4 are provided between a processor 1 and a transfer device 5 for executing an access to a memory 2. For instance, when the transfer device 5 receives a data from the memory 2, if the transfer device 5 outputs address information A(D) and an address strobe AD(D), the AREG3 accumulates the address information A(D), outputs a bus occupancy request BR to the processor 1, and receives a use permission BG. The AREG3 sends out the information A and the strobe AS to the memory 2, the memory 2 sends out a data D and an approval signal DTACK, stores the data D in the DREG 4, releases a bus connected to the AREG3, and thereafter, the transfer device 5 reads the DREG4. In this way, a bus occupancy time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information processing device, and more particularly to a memo 11 bus access method suitable for a data transfer device that directly transmits and receives data to and from a memory.

[Background of the invention]

In conventional data transfer equipment that directly sends and receives data to and from memory, the control circuit for sending and receiving data to and from memory usually includes a direct memory control LSI (DMAC).
It is common to use LSI. DMAC, LSI
Normally, the timing is controlled by a clock, so even if a completion report is received from the memory side, the bus is monopolized until the processing within the DMACLSI is completed, and if the above clock is slow, the processing speed of the memory cannot be used effectively. There was a drawback.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memo 11-bus access method that eliminates the drawbacks of the prior art described above and shortens the time that a data transfer device that directly sends and receives data to and from a memo 11-occupies a memory bus. It is in.

[Summary of the invention]

A register for storing address and data information is provided between the data transfer device and the memo 1j-bus, for example! For example, when reading memory data, address information from the data transfer device is stored in a register, and then a request to use the memory bus is output, and when all permissions to use the memory bus are received from the bus management device, the address information stored in the register is stored in the register. By outputting address information and an address strobe, and receiving data output and a data acknowledge signal from the memory, the data is stored in the data register, and the memo 11 bus is immediately released. It has been made possible to shorten the exclusive time of the memory bus to almost the access time of the memo 11- without being affected by the processing speed.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In the figure, 1 is a processor that has bus management authority.

2 is a memory, 3 is an address register having a bus management function, 4 is a data register, and 5 is a data transfer device. Rejection As an example of this embodiment, an operation in which the data transfer device 5 reads data from the memory 2 will be described. When the data transfer device 5 reads data from the memory 2,
Data transfer device 5 outputs address information A (D) and address strobe A S (D). The address register 3 stores address information A (D) and the processor 1
The bus request signal BR is output to the bus request signal BR. Processor 1 returns a bus use permission signal BG to address register B when the bus becomes empty. Address register 3 is memo 11
Address information A and address strobe ASf are sent to -2, and at the same time bus in-use indication BGA is sent to processor 1.
Send CK. The memo 112 sends out data D and a data acknowledge signal DTACK when the data corresponding to the second address can be output. The data is stored in the data register 4 by the DTACK signal, and the address register 6 stores address information A and address strobe A.
S is stopped, the sending of BGACK indicating that the bus is in use is stopped, and the monopoly of the bus is released. The data transfer device 5 starts reading the data stored in the data register 4 in response to the DTACK signal, and completes the data reading in accordance with internal processing timing. As explained above, according to this embodiment, the time the data transfer device 5 uses the memory bus is almost equal to the memory access time, and the data transfer device 5 includes a data transfer device having a direct memory access function. This has an effect on the throughput of the information processing device.

〔Effect of the invention〕

According to the present invention, the bus exclusive time of a data transfer device that directly transmits and receives data to and from a memory can be reduced, which is effective in improving the processing performance of an information processing device including the data transfer device.

[Brief explanation of drawings]

The figure is a configuration diagram of an embodiment of the present invention. 1...processor, 2...Memory, 3...address register, 4...Data resis, 5...Data transfer device. Representative Patent Attorney Akio Takahashi

Claims (1)

[Claims] 1. An information processing device including a random access memory and a data transfer device having a memory access function capable of directly accessing the memory, characterized in that address and data registers are provided between the data transfer device and a memory bus. +1 bus access method.