JPS60140451A - Memory bus system - Google Patents

Abstract

PURPOSE:To improve the performance of the entire titled system by storing an address and a data from a processor to a memory buffer, and releasing the common bus before the start of a memory operation to improve the utilizing efficiency of a common bus. CONSTITUTION:The processor receiving a reception signal 13 transmits an address to a common address bus 5. If it is a write request, a write data is outputted to a common data bus 4 at the same time, a write command is transmitted to a command line 16. These commands are fed to a bus control section 11 to inhibit the succeeding reception signal (13) transmission. The command controls a buffer control section 10 that the data and address on the common buses 4, 5 are fetched in a register of a memory buffer 6 in the clock timing 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory bus system for an information processing system in which a plurality of processors share memory via a common bus.

[Background of the invention]

In the above type of information processing system, when each processor (processing unit, input/output control unit, etc.) accesses the memory, it waits until the bus and memory become free, and then uses the bus. , the address to be accessed is transferred to the memory together with the write data in the case of a write. Then, in the case of writing, the memory is caused to perform a write operation, and in the case of reading, the bus and memory are released after waiting for data to be transferred from the memory. Communication requests to memory are randomly generated from multiple processors, so we detect the free state of the bus and
The allocation of bus control rights is adjusted in response to the various requests. This is known as a bus arbiter.

In the conventional method, once a processor starts accessing the memory, the bus is not freed until the memory operation is completed, so the bus occupation time for one time is the sum of the bus transfer time and the memory operation time. Hiroshi:As a result, the processing power of the system was limited. In particular, if the memory cycle time is large compared to the processor and bus cycle times, the negative effects are significant.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to increase the efficiency of the use of the common bus and memory in a system of the type mentioned above, thereby increasing the throughput of the entire system.

[Summary of the invention]

In the present invention, a buffer device for storing addresses and write data is provided between a common bus and a memory, and memory access requests from each processor are temporarily stored here. . Therefore, when an access request from a processor is transferred to this buffer device via the common bus, the common bus can be released at that point and used by other processors. However, in this case, although this is sufficient for writing, in the case of reading, there is a risk that the return of the read data will be delayed until the common bus is no longer occupied by other processors. Therefore, a means for reserving a common bus for read data at the start of a memory read operation is provided.
Prepare the read data so that it is immediately output to the common bus.

[Embodiments of the invention]

FIG. 1 shows one embodiment of the invention. Each of the plurality of processors 1-3 communicates with other processors or memory 7 via a common data bus 4 and address bus 5. However, communication with the memory 7 is via the memory buffer 6. Each processor issues a bus request 12 to the bus control unit 11 when a need for memory access arises.

Details of the bus control section 11 are shown in FIG.

Bus requests 12 from each processor are sequentially accepted by a priority circuit 31 according to a predetermined order. When neither the read command 161 nor the write command 162 has arrived from any processor, that is, if the common bus is in an empty state, the output of the NOT circuit 362 connected to the output of the OR gate 35 that receives both command signals is 1''. Therefore, when the clock timing signal 33 is generated, the AND gate 342
The response circuit 32 is activated by the output of , and the reception signal 13 is sent back to the corresponding processor. At this time, it is assumed that the signal 17 is "0", that is, does not exist, but the details of the signal 17 will be described later.

Returning to FIG. 1, the processor that receives the reception signal 13 sends the address to the common address bus 5, and at the same time, if it is a write request, outputs the write data to the common data bus 4 and also outputs the write command (second 162) to the command line 16, and if it is a read request, the read command (second
161) to the command line 16. These directives are
It is sent to the bus control unit 11, and the OR gate 35 in FIG.
The response circuit 32 is suppressed via the NOT circuit 362 and the AND gate 342, and the transmission of the signal 13 is prohibited for subsequent reception. The command also instructs the buffer control unit 10 to control the buffer controller 10 to load the data and address on the common bus 4.5 into the register in the memory buffer 6 at clock timing 15.

When this acquisition is completed, the use of the bus by the processor in question ends, and the common bus is released for use by other processors.

The memory buffer 6 generates a memory request signal 14 based on the address taken in as described above, and the buffer control unit 10 that receives this signal extracts the address from the memory buffer 6 according to the priority order of the buffered memory requests. 9 and in the case of writing, the data 8 is sent to the memory 7 and the memory operation is started at the 1 memory control timing 18.

In the case of a read operation, when the memory read operation starts, the buffer control section 10 sends a bus reservation signal 17 to the bus control section 11 before data is read from the memory 7. This bus reservation signal 17 is generated in accordance with appropriate memory control timing so that the common bus can be used sufficiently earlier than the time when read data is output from the memory 7.

As shown in FIG. 2, the bus reservation signal 17 passes through the NOT circuit 361, turns off the AND gate 341, and suppresses the output of the priority circuit 31. Therefore, when the memory read operation starts, the reception to each processor is signal 1.
3 is prevented from sending out common bus 4 by each processor.
, 5, the bus reservation signal 17 is used until the bus reservation signal 17 disappears. In other words, the common bus is free for read data.

Eventually, the data read from the memory 7 is transferred to the memory data line 8.
When the read data is output to the common bus 4, the memory buffer 6 immediately outputs this read data to the common bus 4 because the common bus is in a usable state as described above. The waiting requesting processor captures this read data via the appropriate read data strobe signal.

By increasing the number of buffer stages in the memory buffer 6, the efficiency of use of the memory and memory can be further increased. In this case, it is more effective to prioritize read requests over write requests.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, addresses and data from a processor are stored in a memory buffer, and the common bus is released before starting a memory operation, thereby increasing the efficiency of use of the common bus. Moreover, since the common bus is reserved for the read data, there is no risk that the transfer of the read data to the read requesting processor will be delayed due to blockage of the common bus. Therefore, improvement in the performance of the entire system is promised.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a bus control section in FIG. 1. 1 to 3...processor, 4...common data bus, 5
...Common address bus, 6...Memory buffer, 7
...Memory, 10 River buffer control unit, 11...Bus control unit, 12...Bus request signal line, 13...Bus request reception signal line, 16 (161, 162)...Reading and writing Command line, 17...Bus reservation signal line, 31...
Priority circuit, 32...response circuit. Agent: Patent attorney Mamoru Nohagi (and 1 other person)

Claims (1)

[Claims] 1. A common bus for transferring addresses and data between a memory and a plurality of processors that share this memory, and a buffer for addresses and write data provided between this common bus and the memory. A memory bus system comprising a device and means for reserving said common bus for read data upon initiation of a memory read operation.