JP2885640B2 - Data bus transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer between bus control modules connected to a system bus. The present invention relates to a data bus transfer method which enables the data bus transfer.

[0002]

2. Description of the Related Art With the recent enlargement of an information network, a local bus to which a terminal module is connected is connected to a system bus, so that the local bus is not limited to exchanging information in the local bus. A data bus transfer method that enables communication of the above information is becoming widespread. FIG. 12 is a block diagram showing an example of a conventional data bus transfer method.
In the figure, 1a, 1b, 1c, 1d,... 1n are bus control modules, 3 is a system bus connecting these bus control modules 1a to 1n, and 5 is connected to the bus control module 1b to manage the entire system. CP
U and 6 are memories connected to the bus control module 1c,
Reference numeral 4 denotes a local bus connected to the bus control module 1a, and reference numerals 2a, 2b... 2n denote I / O modules of terminal modules typified by SCSI, LAN, etc. connected to the local bus 4.

Reference numeral 10 denotes a system bus control unit which receives a data transfer request from a bus control module which has issued another data transfer request via the system bus 3 and transmits data requested by the local bus control unit 11 to the system bus 3. Transfer to A local bus controller 11 receives a data transfer request from the I / O modules 2a to 2n or the like via the local bus 4, and transfers data to the local bus 4 requested by the system bus controller 10. . The system bus controller 10 and the local bus controller 11 are connected by an internal bus 15.

Reference numeral 12 denotes a local bus arbitration unit. This means that each of the I / O modules 2a to 2
2n output external local bus request signals 20a-20
n and the internal local bus request signal 16 output from the system bus control unit, and arbitrates the acquisition of the local bus 4. The local bus arbitration unit 12 sends external local bus permission signals 21a to 21a to the requesting I / O module.
21n or an internal local bus permission signal 17 to the system bus control unit 10. The local bus arbitration unit 12 permits a new use request of the local bus 4 only when the local bus 4 is not used by all data transfer request sources. This configuration applies to all bus control modules 1
Common to a to 1n.

Next, the operation will be described. The system bus 3 and the local bus 4 are independent of each other, and data transfer on the bus operates without being influenced by each other. However, each bus is used by the arbitration operation of the bus control modules 1a to 1n. For example, the I / O module 2a sends an external local bus permission signal 2 from the local bus arbitration unit 12.
1a, the local bus 4 is used. In the meantime, even if another I / O module 2b requests the use of the local bus 4 and outputs the external local bus request signal 20b, the external local bus permission signal 21b for permitting the use is not issued and the local bus 4 is not issued. I can't get bus 4.

[0006] This arbitration operation is similar to the arbitration entry operation from a certain bus control module on the system bus 3. One bus control module accesses an I / O module connected to another bus control module. In this case, first, the bus control module that has requested the data transfer sends a transfer request to the bus control module to which the local bus 4 that has requested the data transfer is connected. Upon receiving the request, the bus control module of the data transfer request destination sends the request to the local bus 4
It arbitrates with the above I / O modules 2a to 2n. Thereafter, the I / O module of the data transfer request destination and the bus control module of the data transfer request source are connected.

For example, any one of the I / O modules on the local bus 4 connected to the bus control module 1a,
For example, when the I / O module 2a is performing data transfer to the I / O module 2b, one of the bus control modules of the other data transfer source on the system bus 3, for example, the 2n via the local bus 4 of the control module 1a.
When an attempt is made to access any of the I / O modules, the bus control module 1a requests the bus control module 1b of the data transfer request source on the system bus 3 to re-execute. This request is made by outputting a busy signal using a wired or signal line 7 called a busy line.

For example, when the bus control module 1a and the I / O module 2a are performing bus transfer via the local bus 4, the bus control module 1b via the system bus 3 , The system bus control unit 10 of the bus control module 1a operates to transfer the internal local bus request signal 1
6 is output. However, since local bus 4 is already in use, internal local bus permission signal 17 is not issued.

The system bus control unit 10, which has detected that the internal local bus permission signal 17 is not issued, outputs a busy signal 7 and requests the bus control module 1b, which is the transfer request source, to retransmit data to the local bus 4. By outputting a busy signal 7. Upon receiving the busy signal 7, the bus control module 1b once cancels the request to the bus control module 1a, further releases the system bus 3, re-arbitrates for obtaining the right to use the system bus 3, and re-executes the bus control. The same transfer as described above is performed to the control module 1a. At this time, if the local bus 4 of the bus control module 1a is not released, the bus control module 1a of the data transfer request destination outputs the busy signal 7 again. If the local bus 4 is released, the bus control module 1b and the I / O module 2b are connected,
Data transfer can be performed.

[0010]

Since the conventional data bus transfer method operates as described above, the following problems occur when the transfer of the local bus 4 and the request from the system bus 3 occur simultaneously. I do.

In a normal system, the local bus 4 to which the I / O module is connected has a higher priority than the system bus 3 so as not to impair the I / O data. When the module 2a and the I / O module 2b alternately occupy the local bus 4, the other bus control modules 1a to 1b of the system bus 3 side
A period occurs in which a request from In cannot be accepted. This is because even if the priority from the system bus 3 is raised, if the timing of issuing the re-request is later than the request of the I / O modules 2a to 2n, the request on the system bus 3 will be accepted as a result. And waiting time for bus acquisition occurs.

For example, when a data transfer request is issued from the CPU 5 to the I / O modules 2a to 2n connected to the local bus 4 of the DMA type, the performance of the CPU 5 is reduced due to the occurrence of the above-mentioned waiting time. There was a problem.

According to the present invention, it is possible to efficiently access the I / O modules connected to the local bus 4 from the system bus 3 without being affected by the configuration of the modules connected to the local bus 4 and the transfer capability. It is an object of the present invention to realize a data bus transfer method that can perform the data bus transfer and reduce the waiting time for acquiring the bus.

[0014]

According to a first aspect of the present invention, there is provided a data bus transfer method, comprising a system bus, a system bus controller connected to the system bus, a local bus controller, and a local bus arbitrator. 12 and a local bus 4 connected to the local bus control unit 11, and one of the bus control modules 1a to 1n that is a data transfer request source.
Requests data transfer to the other bus control modules 1a to 1n via the system bus 3.

Therefore, the other bus control modules 1a to 1
When the terminal modules 2a to 2n such as I / Os on the local bus 4 connected to the local bus 1n cannot be acquired, a busy signal 7 for requesting re-execution of acquisition is sent to the bus control modules 1a to 1b requesting the data transfer. 1n.

Such a function is provided by each bus control module 1
In the data bus transfer method Ru formed is set to a~1n,
Prohibiting means for prohibiting the local terminal modules 2a to 2n from newly acquiring the local bus 4 is provided for a set period from the time when the busy signal 7 is returned, so that the bus for the data transfer request source is temporarily provided. Control module 1a
-1n to the local bus 4 is prioritized.

In the data bus transfer method according to the second aspect of the present invention, the bus control modules 1a to 1n requesting the data transfer are provided.
The system bus 3 priority period setting register 22 is provided which enables the setting period for giving priority to access from the system bus 3 to be changed according to the system contents or the processing execution contents.

According to a third aspect of the present invention, in the data bus transfer method, the bus control modules 1a to 1n of the data transfer request source are set within the set period set by the system bus 3 priority period.
If the re-execution of the data transfer performed via the system bus 3 from the server is successful, the prohibiting means is released even within the set period, and the local bus 4 is promptly released to the terminal modules 2a to 2n. It is something to do.

According to a fourth aspect of the present invention, there is provided a data bus transfer method, comprising a plurality of systems including a system bus, a system bus controller connected to the system bus, a local bus controller, and a local bus arbitrator. It includes a bus control module 1a to 1n and a local bus 4 connected to the local bus control unit 11. Other data transfer via the system bus 3 is performed by one of the bus control modules 1a to 1n that has requested data transfer. When data transfer is requested from the requested bus control modules 1a to 1n and terminal modules 2a to 2n such as I / O on the local bus 4 connected to the other bus control modules 1a to 1n cannot be obtained, A busy signal 7 for requesting re-execution of the acquisition is returned to the bus control modules 1a to 1n of the data transfer request source.

Such a function is provided by each bus control module 1
In the data bus transfer method Ru formed is set to a~1n,
The bus control modules 1a to 1n of the data transfer request source
A function to store the addresses of the bus control modules 1a to 1n to which the data transfer is requested is provided, and the bus control modules 1a to 1n to which the data transfer is requested are stored in the terminal module 2a.
2 to 2n are provided with a function of outputting a "retry OK" signal to the bus control modules 1a to 1n that have requested data transfer.

[0021]

[0022]

[0023]

According to a fifth aspect of the present invention, there is provided a data bus transfer method comprising a plurality of systems including a system bus, and a system bus controller, a local bus controller, and a local bus arbitrator connected to the system bus. It includes a bus control module 1a to 1n and a local bus 4 connected to the local bus control unit 11. Other data transfer via the system bus 3 is performed by one of the bus control modules 1a to 1n that has requested data transfer. Requests data transfer to the requested bus control modules 1a to 1n.

Therefore, the other bus control modules 1a to 1
When the terminal modules 2a to 2n such as I / Os on the local bus 4 connected to the local bus 1n cannot be acquired, a busy signal 7 for requesting re-execution of acquisition is sent to the bus control modules 1a to 1b requesting the data transfer. 1n.

Such a function is provided by each bus control module 1
In the data bus transfer method Ru formed is set to a~1n,
An access information storage register 61 for storing access request information of the bus control module 1a to 1n of the data transfer source to which the busy signal 7 is returned is built in, and after the busy state ends, the bus control module of the data transfer source 1a
Before access by retry from ~ 1n occurs,
The data of the terminal modules 2a to 2n is read based on the access request information in the access information storage register 61, and the data is taken into a separately provided prefetch data buffer 62.

After that, the value of the prefetch data buffer 62 is returned at the time of retry access from the data transfer source bus control modules 1a to 1n.
This is to reduce the time required for data transfer.

According to a sixth aspect of the present invention, there is provided a data bus transfer method comprising a plurality of systems including a system bus, and a system bus controller, a local bus controller, and a local bus arbitrator connected to the system bus. It includes a bus control module 1a to 1n and a local bus 4 connected to the local bus control unit 11. Other data transfer via the system bus 3 is performed by one of the bus control modules 1a to 1n that has requested data transfer. Requests data transfer to the requested bus control modules 1a to 1n.

Therefore, the other bus control modules 1a to 1
When the terminal modules 2a to 2n such as I / Os on the local bus 4 connected to the local bus 1n cannot be acquired, a busy signal 7 for requesting re-execution of acquisition is sent to the bus control modules 1a to 1b requesting the data transfer. 1n.

Such a function is provided by each bus control module 1
In the data bus transfer method Ru formed is set to a~1n,
An access information storage register 61 for storing access request information of the bus control module 1a to 1n of the data transfer source to which the busy signal 7 is returned is built in, and the bus control of the data transfer request source to which the busy signal 7 is returned is provided. After the modules 1a to 1n are in the data waiting state, and the bus control modules 1a to 1n that have returned the busy signal 7 have completed the busy state, the bus control modules 1a to 1n read data based on the access information, and provided a separately provided prefetch. The data is taken into the data buffer 62.

Thereafter, the value of the prefetch data buffer 62 is returned to the bus control modules 1a to 1n that have issued the data transfer request, thereby making the retry operation unnecessary.

[0032]

According to the first aspect of the present invention, the bus control modules 1a to 1n, which are the data transfer request sources, request data transfer to other data transfer request destination bus control modules 1a to 1n via the system bus 3. When the terminal modules 2a to 2n such as I / O on the local bus 4 connected to the bus control module of the data transfer request destination cannot be acquired, the busy signal 7 for requesting re-execution of the acquisition Bus control module 1a to 1n of transfer request source
Return to.

In such a case, a prohibition flag 19 for prohibiting the local terminal modules 2a to 2n from newly acquiring the local bus 4 for a certain period set by the counter from the time when the busy signal 7 is returned. Is issued by the prohibition flag generation unit 14, and while the prohibition flag 19 is significant, priority is given to the access to the local bus 4 from the bus control modules 1a to 1n that are the data transfer request sources.

According to the second aspect of the present invention, the setting period for giving priority to the access from the bus control module 1a to 1n that is the data transfer request source is provided with the setting register 22 and the comparator 23, so that the setting period can be appropriately set.

According to the third aspect of the present invention, during the priority period of the system bus 3, while the inhibition flag 19 is significant, the data transfer request is made via the system bus 3 from the bus control module 1a to 1n which has requested the data transfer. When the re-execution of the data transfer succeeds, the prohibition flag 19 is ignored even within the set period, and the local bus 4 is promptly released to the terminal modules 2a to 2n.

According to the fourth aspect of the present invention, the addresses of the bus control modules 1a to 1n of the data transfer request destinations are stored in the transfer source information storage unit 43 in the data transfer request source bus control modules 1a to 1n. When the bus control modules 1a to 1n finish processing of the terminal modules 2a to 2n, the bus control module 1
The retry OK output unit 45 outputs a "retry OK" signal 42 for a to 1n based on the contents of the transfer source information storage unit 43.

[0037]

According to the fifth aspect of the present invention, any one of the bus control modules 1a to 1n of the data transfer request source requests data transfer to other bus transfer modules 1a to 1n of the other data transfer request destination via the system bus 3. A terminal module 2 such as an I / O on the local bus 4 connected to the bus control modules 1a to 1n to which the data transfer is requested.
When a to 2n cannot be acquired, a busy signal 7 for requesting re-execution of the acquisition is returned to the bus control modules 1a to 1n that have issued the data transfer request.

At this time, the access request information of the bus control module 1a to 1n of the data transfer source to which the busy signal 7 is returned is stored in the access information storage register 61, and after the busy state ends, the bus control of the data transfer source is completed. Before the access by the retry from the modules 1a to 1n occurs, the data of the terminal modules 2a to 2n is read based on the access request information in the register 61, and the data is taken into the prefetch data buffer 62 provided separately. , The data transfer source bus control modules 1a to 1
At the time of retry access from 1n, the value of the data buffer 62 is returned.

According to the sixth aspect of the present invention, any one of the bus control modules 1a to 1n of a data transfer request source requests data transfer to another bus transfer module 1a to 1n of another data transfer request destination via the system bus 3. When the terminal modules 2a to 2n such as I / O on the local bus 4 connected to the data transfer request destination bus control module cannot be acquired, a busy signal 7 for requesting re-execution of acquisition is sent to the data transfer module. The transfer request is returned to the bus control modules 1a to 1n.

The access request information of the bus control module 1a to 1n of the data transfer source to which the busy signal 7 has been returned is stored in the access information storage register 61, and the bus control module of the data transfer request source to which the busy signal 7 has been returned. 1a to 1n are put into a data waiting state by the data reception control unit 72, and the bus control modules 1a to 1n of the data transfer destinations that have returned the busy signal 7 read data based on the access information after the busy state ends. ,
By retrieving the data into the separately provided prefetch data buffer 62 and returning the value of the data buffer 62 to the bus control modules 1a to 1n that have requested the data transfer, the retry operation is not required.

[0042]

[Embodiment 1 ] Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as those in FIG. 12 are denoted by the same reference numerals. 1 in FIG.
Is a system bus control unit that receives data transfer requests from the other bus control modules 1a to 1n via the system bus 3 and performs data transfer to the system bus 3 requested by the local bus control unit 11. Govern. Reference numeral 11 denotes a local bus control unit which controls the I
And a mechanism for receiving a data transfer request from the terminal modules 2a to 2n such as / O, and governs data transfer to the local bus 4 requested by the system bus control unit 10.

The system bus controller 10 and the local bus controller 11 are connected by an internal bus 15. Reference numeral 12 denotes a local bus arbitration unit, which outputs external local bus request signals 20a to 20n output from terminal modules 2a to 2n such as I / Os connected to the local bus 4 and an internal output from the system bus control unit 10. A local bus request signal 16 is input or arbitrated, and an external local bus permission signal 21a to 21n or an internal local bus permission signal 17 is output to the bus control module that has requested the data transfer.

The local bus arbitration unit 12 employs an arbitration method in which a request for using the local bus 4 is newly permitted only when all the request sources are not using the local bus 4.

Reference numeral 13 denotes a counter which counts up the time when the inhibition flag 19 is significant. The counter is activated by the busy signal 7 output to the system bus 3, and when a predetermined count value is reached, the count-up signal 18 is activated. Is output. Reference numeral 14 denotes a prohibition flag generator which receives the busy signal 7 and the count UP signal 18 and generates a prohibition flag 19. The prohibition flag 19 is made significant by the busy signal 7 and made insignificant by the count UP signal 18.

Next, the operation will be described with reference to the timing charts of FIGS. In FIG. 1, for example, a terminal module 2a such as an I / O connected to a local bus 4 of a bus control module 1a receives an external local bus permission signal 21a from a local bus arbitration unit 12,
The local bus 4 is used for a certain period. Even if another terminal module 2b for I / O or the like similarly outputs the external local bus request signal 20b during the use period of the local bus 4, the external local bus permission signal 21b for the terminal module 2b for I / O or the like is The terminal module 2b, such as an I / O, is not issued and waits for use of the local bus 4.

Similarly, the other bus control modules 1b to 1n
For example, in response to a data transfer request to the local bus 4 of the bus control module 1a issued from the bus control module 1b, the system bus control unit 10 operates to change the internal local bus request signal 16 as shown in FIG. , But the internal local bus permission signal 17 is not issued. The system bus control unit 10 that has detected that the internal local bus permission signal 17 is not issued outputs the busy signal 7 in FIG.
b, a request for data retransfer to the local bus 4 is requested.

At this time, in accordance with the busy signal 7 issued by the system bus control unit 10 constituting the bus control module 1a, the inhibition flag generation unit 14 sends the inhibition flag 19 to the local bus arbitration unit 12 in FIG. Significant at c, the counter 13 is activated at the same time.

The local bus arbitration unit 12 having received the significant output of the prohibition flag 19 outputs the internal local bus request signal 16 issued by a request from another bus control module.
Regardless of the presence or absence of
External local permission signals 21a to 21n for external local bus request signals 20a to 20n, which are new requests from terminal modules such as I / O, are not issued. However, the currently issued external local bus permission signal 21a
Is held until the ongoing data transfer ends and the external local bus request signal 20a becomes insignificant.

Next, when the terminal module 2a uses the local bus 4 and temporarily negates the external local bus request signal 20a, the terminal module 2a negates the external local bus permission signal. As a result, the external local bus request signal 20 issued by the terminal module 2b which has been requested previously is issued.
The external local bus permission signal 21b for b should be issued, but no new permission signal is issued because the prohibition flag 19 is significant at c. Similarly, an external local bus permission signal 21a for an external local bus request signal 20a issued again by the terminal module 2a.
Is not issued.

The other bus control modules 1b to 1 responded with the busy signal 7 while the prohibition flag 19 was significant.
When a retransfer request is issued from n, since no external local bus permission signals 20a to 20n have been issued, the internal local bus permission signal 17 corresponding to d of the internal local bus request signal 16 can be issued. The local bus 4 can be used for data transfer from the bus 3 side.

The counter 13 issues a count-up signal 18 to the prohibition flag generator 14 after counting for a certain period of time, whereby the prohibition flag 19 becomes insignificant at the point e and the counter 13 If the internal local bus permission signal 17 is insignificant, any of the external local bus permission signals 21a to 21n corresponding to the significant external local bus request signals 20a to 20n can be issued as shown by f.

According to the above-described embodiment, the effect that the re-data transfer from the system bus 3 is prioritized can be obtained.

Embodiment 2 FIG . Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing another embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In FIG. 3, reference numeral 22 denotes a setting register for setting and storing a significant period of the prohibition flag 19 described in the first embodiment. Writing to the register 22 is performed, for example, by the CPU via the system bus 3.
5 and so on. A comparator 23 compares the contents of the setting register 22 with the count value 24 output from the counter 13, and if they match, the count UP signal 1
8 is output.

Next, the operation will be described. Since the bus control module 1a receives a transfer request from the system bus 3 and the local bus 4 is in use, the other bus control modules 1a
When the busy signal 7 is output for b to 1n and a retransfer request is responded, the internal local bus request signal 16 from the system bus control unit 10 is changed to the external local bus request signal 20a to 20n by the prohibition flag 19. Implement a mechanism that treats with higher priority.

External local bus request signals 20a-20n
In order to set the significant period of the prohibition flag 19, the counter value 24 output from the counter 13 that is counted at the same time when the busy signal 7 is issued and the CPU 5
The comparator compares the set count value 25 set by the above with a comparator, and when they match, outputs a count UP signal 18 to the prohibition flag generator 14 and makes the prohibition flag 19 insignificant.

Thus, the period in which the retransfer request from the system bus 3 is prioritized can be freely changed.

Embodiment 3 FIG . Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention.
3 are denoted by the same reference numerals. In the figure,
Reference numeral 30 denotes an OR (logical sum) element, which is a system bus access completion signal 31 output from the system bus control unit 10.
And a logical sum of the count UP signal 18 output from the comparator 23 described in the second embodiment to generate a prohibition flag reset signal 32.

Next, the operation will be described with reference to the timing chart of FIG. There is a transfer request from the system bus 3 side to the bus control module 1a, and an internal local bus request signal 16 is issued at a, but the local bus 4 is being used by the terminal module 2a such as an I / O at b. When the busy signal 7 is output at c to the bus control modules 1b to 1n, and the retransmission request
9 is made significant by d, and a mechanism for preferentially handling the internal local bus request signal 16 from the system bus control unit 10 over the external local bus request signals 20a to 20n is realized. The system bus control unit 10 that has detected that the retransfer from the other bus control modules 1b to 1n has succeeded at e, outputs a system bus access completion signal 31 to the counter 13 and the OR element 30. The signal 31 causes the count value 2 of the counter 13 to change.
4 is reset and the prohibition flag reset signal 3
2 is output. Upon receiving this, the prohibition flag generating unit 14
The prohibition flag 19 during continuous output to the local bus arbitration unit 12 is rendered insignificant at f.

During the period in which the internal local bus request signal 16 is preferentially handled, the other bus control modules 1b to 1n
If no re-transfer request is issued from the
A prohibition flag reset signal 32 is generated by the count UP signal 18 output from the control unit 3 and the prohibition flag 19 is made insignificant in the same manner as in the second embodiment.

As a result, the extra priority period of the system bus 3 can be deleted, and the local bus 4 can be quickly released to the terminal modules 2a to 2n such as I / O at g.

Embodiment 4 FIG . Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram showing the configuration of another embodiment of the present invention.
1 are denoted by the same reference numerals. Reference numeral 40 denotes a busy detection unit that detects the busy signal 7 output from the system bus control unit 10. 43 is a bus control module 1a
A transfer source information storage unit 44 for storing information of the transfer request source bus control modules 1a to 1n for making access requests to .about.1n, and a selector 44 for determining an output destination of the retry OK signal 42. Reference numeral 45 denotes a retry OK output unit that receives any external local bus permission signal 21 output from the local bus arbitration unit 12 and outputs a retry OK signal 42 to the selector 44. Reference numeral 41 denotes a retry OK detection unit that receives the retry OK signal output from the selector 44.

Next, the operation will be described with reference to the timing charts of FIGS. For example, if a data transfer request from the system bus 3 to the local bus 4 occurs while the terminal module 2a such as one I / O acquires the local bus 4 at a, a data transfer request is made. The bus control module 1a sends a busy signal 7 to the bus control module 1b that has issued the data transfer request.
Output at The bus control module 1b, which is the transfer request source, detects the busy signal 7 by the busy detection unit 40,
A busy detection signal 47 is output to the local bus control unit 11 to temporarily give up acquisition of the system bus.

Terminal modules 2a to 2n for I / O etc.
When the local bus 4 is released as shown by d, the local bus arbitration unit 12 outputs the external local bus permission signal 21 to the retry OK output unit 45. Upon receiving the external local bus permission signal 21, the retry OK output section 45 outputs a retry OK signal 42 to the selector 44, and outputs the transfer source information signal 4 output from the transfer source information storage section 43.
6, the output destination of the retry OK signal 42 is determined, and then the retry OK signal 42 is output to the bus control module 1b which has issued the data transfer request in e. The retry OK signal 42 is detected by the retry OK detection unit 41 in the data transfer request source bus control module 1b, and the retry OK detection unit 41 informs the local bus control unit 11 in the bus control module 1b. .

The local bus control unit 11 of the bus control module 1b sends a retry OK
When the detection signal 45 is output, a retry is performed on the system bus 3 and the terminal module 2b such as an I / O connected to the local bus 4 of the bus control module 1a, which is the transfer request destination, can be accessed.

As described above, the number of retries of the bus control module 1b that makes a data transfer request can be reduced, and the efficiency of the system bus 3 can be increased.

Embodiment 5 FIG . Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a block diagram showing the configuration of another embodiment of the present invention.
1 are denoted by the same reference numerals. Reference numeral 50 denotes a local bus arbitration unit 12 in each of the bus control modules 1a to 1n.
Module identification / operation determination signal output from the
Reference numeral 51 denotes a module identification / operation determination unit that receives the module identification / operation determination signal 50.

Next, the operation will be described with reference to FIGS. For example, the bus control module 1a performs data transfer with the terminal module 2a such as an I / O via the local bus 4. This is because the terminal module 2a requests the external local bus request signal 20 to request the use of the local bus 4.
a to the local bus arbitration unit 12, and upon receiving the signal 20a, the local bus arbitration unit 12 outputs an external local bus permission signal 21a to the terminal module 2a as indicated by a.

At this time, the local bus arbitration unit 12 outputs the module identification / operation determination signal 50a to all the other bus control modules, here, 1b to 1n, as indicated by b. The module identification / operation determination signal 50 is received by the module identification / operation determination unit 51 in each of the bus control modules 1a to 1n. When issuing an access to another bus control module 1a, the bus control module 1b first checks information in the module identification / operation determination unit 51b.

Here, the module identification / operation determination signal 50
If a is significant, no data transfer request to the system bus 3 is issued, and after the module identification / operation determination signal 50a becomes insignificant at c, the bus control module 1a, which is the transfer destination, is not sent. Access to the connected terminal module 2b such as I / O is started.

As described above, unnecessary access to the system bus 3 can be prevented beforehand, efficient use of the system bus 3 can be achieved, and unnecessary access to the system bus 3 for the bus control modules 1a to 1n can be achieved. Therefore, the processing of the bus control module can be made more efficient.

Embodiment 6 FIG . Embodiment 6 will be described with reference to the drawings. FIG. 10 is a block diagram showing the configuration of another embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In the figure, 61 is an access information register for storing access request information from other bus control modules 1b, 1c... 1n, and 62 is a terminal module 2a, 2b such as an I / O connected to the local bus 4.
.., A prefetch data buffer for storing data read from 2n; 63 stores data in the terminal modules 2a to 2n such as I / O connected to the local bus 4 in the prefetch data buffer 62 according to the information in the access information storage register 61. This is a prefetch control circuit that controls storage.

Next, the operation will be described. For example, while the local bus 4 of the bus control module 1a is in use, a read request is issued from another bus control module 1b to data held by the terminal module 2b such as an I / O connected to the bus control module 1a. In this case, the busy signal 7 is issued in the same manner as in the above embodiments, but the access information such as the address and the transfer mode such as the single transfer and the burst transfer at the time of the data read request is stored in the access information storage register 61. .

Next, the local bus arbitration unit 12, which recognizes that the local bus 4 has been released, outputs a prefetch control activation signal 64, and upon receiving this, the prefetch control circuit 63 stores the signal in the access information register 61. The prefetch control signal 65 is output to the local bus control unit 11 based on the access information thus obtained, regardless of the presence or absence of a retransfer request from the bus control module 1b that is the transfer request source,
Upon receiving the signal 65, the local bus control unit 11 reads the data of the terminal module 2b, stores the data in the prefetch data buffer 62, and, when there is a re-request from the bus control module 1b, the prefetch data buffer The contents of 62 are transferred to the bus control module 1b.

By such a prefetch operation, the bus control module 1b can receive the busy signal 7 and shorten the access period from the re-request for transfer to the acquisition of necessary data.

Embodiment 7 FIG . In the embodiment shown in FIG. 10, a re-request is made by the bus control module 1 b. However, the bus control module 1 b that has received the busy signal 7 enters a data receiving state, and the bus control module 1 a By reading the data on the basis of the data and transferring the necessary data from the bus control module 1a to the bus control module 1b, the same effect as the embodiment shown in FIG. 10 can be obtained.

This operation will be described with reference to the drawings. FIG.
1 is a block diagram showing the configuration of another embodiment of the present invention, and the same parts as those in FIG. 10 are denoted by the same reference numerals. In the figure,
Reference numeral 71 denotes a data return control unit for transmitting prefetched data to the request source; 72, a data reception control unit for entering a data waiting state from the request destination when the bus acquisition request returns the busy signal 7; From the access information storage register 61 to the system bus controller 10
Access information to be output to

Next, the operation will be described. The bus control module 1a sends a busy signal 7 to the bus control module 1b.
Embodiment 6 until the prefetch operation is further performed.
Is the same as However, the access information storage register 61 also stores the address information of the bus control module 1b that has issued the data transfer request.

Here, the system bus control unit 10 of the bus control module 1b of the data transfer request source that has returned the busy signal 7 outputs the data reception control signal 73, and the data reception control unit 72 receiving this signal activates. And enters a sleep state waiting for data. Further, the bus control module 1a which has returned the busy signal 7 releases the local bus 4 and recognizes that the busy state has ended. The local bus arbitration unit 12 outputs a prefetch control activation signal 64 and receives the prefetch control circuit 64. 63 outputs a prefetch control signal 65 to the local bus control unit 11 based on the access information stored in the access information register 61 irrespective of the presence or absence of a retransfer request from the bus control module 1b that is the transfer request source. Upon receiving the signal 65, the local bus control unit 11 reads data from the terminal modules 2a to 2n such as the I / O of the data transfer request destination, stores the data in the prefetch data buffer 62, and completes the data prefetch. After that, the local bus control unit 11
Outputs a data return request signal 74 to the data return control unit 71.

The data return control section 71 having received the signal 74 outputs a data return signal 75 to the system bus control section 10. Upon receiving the signal, the system bus control unit 10 receives the access information 76 output from the access information storage register 61, refers to the address information of the requesting bus control module 1b, and stores the contents of the prefetch data buffer 62 into the system bus. Via 3,
Data transfer is performed to the bus control module 1b. The data reception control unit 72 of the bus control module 1b that has received the data performs necessary processing on the received data and releases the sleep state.

[0081]

As described above, according to the present invention, the following effects can be obtained.

According to the first aspect of the present invention, when a busy signal is returned to the bus control module that has requested data transfer, a terminal module such as an I / O on the local bus is set for a set period from the time of return of the busy signal. Has established a prohibition means to prohibit the acquisition of a new local bus,
Since access to the local bus side from the bus control module of the data transfer request source is temporarily given priority, the waiting time for bus acquisition is reduced to reduce the number of data transfer requests. effective.

According to the second aspect of the present invention, the system bus priority period is set so that the setting period for giving priority to the access from the bus control module requesting the data transfer can be changed according to the system contents or the processing execution contents. Since the setting register is provided, there is an effect that the ineffective priority period is reduced and data transfer can be performed efficiently.

According to the third aspect of the present invention, when the data transfer is successfully re-executed, the prohibiting means is released even within the set period, and the local bus is immediately released to the terminal module. Therefore, the data transfer suppression period can be minimized, the local bus can be used effectively, and the waiting time for acquiring the bus can be reduced.

According to the present invention, the bus control module of the data transfer request source is provided with a function of storing the address of the bus control module of the data transfer request destination, and the bus control module of the data transfer request destination is provided with the function of storing the address. When the module has completed the processing of the terminal module, it has a function of outputting a "retry OK" signal to the bus control module of the data transfer request source, so that the bus control module of the data transfer request source accesses the system bus. This has the effect of reducing the number of times and reducing the waiting time for acquiring the bus.

[0086]

According to the fifth aspect of the present invention, one of the bus control modules requesting data transfer requests the bus control module of another data transfer request destination via the system bus to request data transfer. When a terminal module such as an I / O on the local bus connected to the bus control module cannot be acquired, a busy signal for requesting re-execution of the acquisition is returned to the bus control module that has requested the data transfer.

An access information storage register for storing the access request information of the bus control module of the data transfer source to which the busy signal has been returned is built in, and after the busy state ends, the bus control module of the data transfer source returns. Before the access by the retry occurs, the data of the terminal module such as I / O is read based on the access request information in the register, and the data is fetched into a separately provided prefetch data buffer. Since the value of the data buffer is returned at the time of retry access from the bus control module, access to the terminal module such as I / O can be efficiently performed, and the time required for data transfer can be reduced.

According to the sixth aspect of the present invention, one of the bus control modules requesting data transfer requests a data transfer request to the bus control module of another data transfer request destination via the system bus. When a terminal module such as an I / O on the local bus connected to the bus control module cannot be acquired, a busy signal for requesting re-execution of the acquisition is returned to the bus control module that has requested the data transfer.

An access information storage register for storing the access request information of the bus control module of the data transfer source to which the busy signal has been returned is built in, and the bus control module of the data transfer request source to which the busy signal has been returned is stored in the data. After the busy state is completed, the bus control module of the data transfer destination that has returned to the wait state and has read the busy signal reads the data based on the access information, captures the data into a separately provided prefetch data buffer, and performs the data transfer. Since the value of the data buffer is returned to the requesting bus control module, the retry operation becomes unnecessary, and the waiting time for acquiring the bus is reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 3 is a configuration diagram showing a second embodiment of the present invention.

FIG. 4 is a configuration diagram showing a third embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the third embodiment of the present invention.

FIG. 6 is a configuration diagram showing a fourth embodiment of the present invention.

FIG. 7 is a timing chart showing the operation of the fourth embodiment of the present invention.

FIG. 8 is a configuration diagram showing a fifth embodiment of the present invention.

FIG. 9 is a timing chart showing the operation of the fifth embodiment of the present invention.

FIG. 10 is a configuration diagram showing a sixth embodiment of the present invention.

FIG. 11 is a configuration diagram showing a seventh embodiment of the present invention.

FIG. 12 is a configuration diagram of one embodiment of a conventional invention.

[Explanation of symbols]

1a-1n bus control module, 2a-2n I / O
Terminal module, 3 system bus, 4 local bus, 5 CPU, 6 memory, 7 busy signal, 10
System bus controller, 11 local bus controller, 1
2 Local bus arbitration unit, 13 counter, 14 inhibit flag generation unit, 15 internal bus, 16 internal local bus request signal, 17 internal local bus enable signal, 18
Count UP signal, 19 prohibition flag, 20a to 20n
External local bus request signal, 21a-21n External local bus permission signal, 22 setting register, 23 comparator, 24 count value, 25 set count value, 30
OR element, 31 system bus access completion signal, 32
Prohibition flag reset signal, 40 busy detector, 4
1 Retry OK detector, 42 Retry OK signal, 4
3 transfer source information storage unit, 44 selector, 45 retry OK output unit, 46 transfer source information signal, 47 busy detection signal, 48 retry OK detection signal, 50a to 50n
Module identification / operation determination signal, 51a to 51n module identification / operation determination unit, 61 access information storage register, 62 prefetch data buffer, 63 prefetch control circuit, 64 prefetch control start signal, 65 prefetch control signal, 71 data return control unit, 72 data reception control unit,
73 data reception control signal, 74 data return request signal, 75 data return signal, 76 access information.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-161951 (JP, A) JP-A-4-199253 (JP, A) JP-A-4-137165 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) G06F 13/36 G06F 13/362

Claims (6)

(57) [Claims] A plurality of bus control modules each including a system bus, a system bus control unit, a local bus control unit, and a local bus arbitration unit connected to the system bus;
A local bus connected to the local bus control unit, wherein one of the data transfer requesting bus control modules requests data transfer to another data transfer request destination bus control module via the system bus. I / O on local bus connected to other bus control modules
When it can not acquire the terminal module etc., acquisition of the data bus transfer method functions Ru formed by setting each bus control module returning a busy signal for requesting the re-execution in the data transfer request source of the bus control module In the case where the busy signal is returned, the prohibition means for prohibiting the local-side terminal module from acquiring a new local bus for a set period from the time of return of the busy signal is temporarily provided. A data bus transfer method, wherein access to the local bus side from the bus control module that has requested the data transfer is prioritized. 2. A system bus priority period setting register which enables the setting period for giving priority to access from a bus control module of a data transfer request source to be changed according to system contents or processing execution contents. Item 2. The data bus transfer method according to Item 1. 3. When the re-execution of the data transfer performed via the system bus from the bus control module requesting the data transfer is successful within the set period set by the system bus priority period, 3. The data bus transfer method according to claim 2, wherein said prohibiting means is released even in said case, and the local bus is immediately released to said terminal module. 4. A plurality of bus control modules each having a system bus and a system bus control unit, a local bus control unit, and a local bus arbitration unit connected to the system bus,
A local bus connected to the local bus control unit, wherein one of the data transfer requesting bus control modules requests data transfer to another data transfer request destination bus control module via the system bus. I / O on local bus connected to other bus control modules
When it can not acquire the terminal module etc., acquisition of the data bus transfer method functions Ru formed by setting each bus control module returning a busy signal for requesting the re-execution in the data transfer request source of the bus control module The data transfer request source bus control module has a function of storing the address of the data transfer request destination bus control module, and when the data transfer request destination bus control module completes the processing of the terminal module, It features and to Lud bus are placed transfer method that have a function of outputting the "retry OK" signal to the transfer request source of the bus control module. 5. A plurality of bus control modules each having a system bus and a system bus controller, a local bus controller, and a local bus arbitrator connected to the system bus.
A local bus connected to the local bus control unit, wherein one of the data transfer requesting bus control modules requests data transfer to another data transfer request destination bus control module via the system bus. I / O on local bus connected to other bus control modules
When it can not acquire the terminal module etc., acquisition of the data bus transfer method functions Ru formed by setting each bus control module returning a busy signal for requesting the re-execution in the data transfer request source of the bus control module A built-in register for storing the access request information of the bus control module of the data transfer source to which the busy signal has been returned, and after the busy state ends, access by retry from the bus control module of the data transfer source is prevented. Before the occurrence, the data of the terminal module is read based on the access request information in the register, and the data is fetched into a separately provided data buffer. Returning the value of the data buffer reduces the time required for data transfer. Data bus transfer method according to claim. 6. A plurality of bus control modules each having a system bus, a system bus control unit connected to the system bus, a local bus control unit, and a local bus arbitration unit.
A local bus connected to the local bus control unit, wherein one of the data transfer requesting bus control modules requests data transfer to another data transfer request destination bus control module via the system bus. I / O on local bus connected to other bus control modules
When it can not acquire the terminal module etc., acquisition of the data bus transfer method functions Ru formed by setting each bus control module returning a busy signal for requesting the re-execution in the data transfer request source of the bus control module A built-in register for storing the access request information of the bus control module of the data transfer source to which the busy signal has been returned, and setting the bus control module of the data transfer request source to which the busy signal has been returned in a data waiting state; After the busy state is completed, the bus control module of the data transfer destination that has returned the busy signal reads the data based on the access information, takes in the data into a separately provided data buffer,
For the bus control module of the data transfer request source,
A data bus transfer method characterized by eliminating a retry operation by returning a value of a data buffer.