JP3011044B2 - I / O controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device, and more particularly to an input / output control device having first-in first-out storage means for receiving a request.

[0002]

2. Description of the Related Art An input / output control device serving as an interface between a system bus for connecting a processing device or a memory and an input / output bus for connecting an input / output device or the like receives a transfer request from one bus. The transfer right is acquired by acquiring the right to use the other bus. Requests are sequentially input to this input / output control device from a plurality of devices (generally also called “agents”) connected to the same bus. For this reason, if it is determined that the processing of a certain request must be completed before the subsequent request is accepted, the subsequent request is kept waiting in a state occupying the bus, and if only the transfer performance between buses is reduced, The use efficiency of the bus itself also decreases.

On the other hand, in the prior art, a first-in first-out storage means (hereinafter, referred to as a "queue") for receiving a request in an input / output control device is provided so that the processing of a subsequent request is completed before the processing of the preceding request is completed. Requests can be accepted.

For example, Japanese Patent Application Laid-Open No. 51-5910 discloses a technology of a line concentrator having a hardware queue for receiving and accumulating requests from a processing device.

[0005]

However, in the above-mentioned prior art, the following inconvenience occurs when an input / output cache memory is provided in the input / output control device. That is, when an input / output cache memory is accessed for a certain request, there is a possibility that a request for the same address exists in the queue, so that the request may be overtaken. On the other hand, even if there is a mishit in the input / output cache memory at the time of queue registration, there is a possibility that the corresponding entry exists at the time of issuing a request, but nevertheless there is a risk that memory access will be wasted unnecessarily. is there.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem and to provide an input / output control device for controlling an overtaking between requests relating to the same address so as not to occur.

Another object of the present invention is to provide an input / output control device for controlling not to issue a useless memory access.

[0008]

In order to solve the above problems, an input / output control device according to the present invention comprises a first bus connecting a memory and a second bus connecting a request generating means for generating a request to the memory. An input / output control device that is connected to a bus of the I / O device and includes a queue that holds a request from the request generation unit until the request is issued to the memory, and a cache memory that holds a part of the memory. And a request reception control circuit for controlling whether the request from the request generation unit is accessed from the cache memory or held in the queue.

In another input / output control device according to the present invention, the queue attempts to issue requests to the memory in the order in which the requests are held in the queue.

In another input / output control device according to the present invention, the request reception control circuit is configured such that, with respect to a request from the request generation means, a request having the same address as an access destination does not exist in the queue, and
When data of the same address exists in the cache memory with respect to the request from the request generation unit, the cache memory is accessed, and a request having the same address as the access destination with respect to the request from the request generation unit is stored in the queue. Exists,
Alternatively, when there is no data at the same address in the cache memory with respect to the request from the request generation unit, the request is held in the queue.

Further, another input / output control device of the present invention is connected between a first bus connecting a memory and a second bus connecting request generating means for generating a request to the memory, In an input / output control device including a queue for holding a request from the request generation unit until the request is issued to the memory and a cache memory for holding a part of the memory, the request from the request generation unit is A request reception control circuit that controls whether to access from the cache memory or to hold the request in the queue; and a request to control whether to access the cache memory before issuing the request held in the queue to the memory. Issue control circuit.

In another input / output control device according to the present invention, the request reception control circuit is configured such that, with respect to a request from the request generation means, a request having the same address as an access destination does not exist in the queue, and
When the data at the same address exists in the cache memory with respect to the request from the request generation unit, the cache memory is accessed, and the request having the same address as the access destination with respect to the request from the request generation unit is stored in the queue. Exists,
Alternatively, when the data at the same address does not exist in the cache memory with respect to the request from the request generation unit, the request is held in the queue, and the request issuance control circuit sets the same with respect to the request held in the queue. If the data at the address exists in the cache memory, the cache memory is accessed, and if the data at the same address does not exist in the cache memory with respect to the request held in the queue, the request of the request is stored in the memory. Attempt to issue.

[0013]

Next, a first embodiment of the input / output control device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an input / output control device 100 according to a first embodiment of the present invention includes a system bus 400 for connecting a processing device 210 and a memory 220, disk control devices 301 and 302, and a printer 311. And an input / output bus 500 for connecting the same.

The input / output control device 100 includes an input / output bus 50
0, a queue 120 for holding a request from, for example, the disk controller 301, a cache memory 110 for holding a part of the contents of the memory 220, and a request reception control circuit for receiving a request from the input / output bus 500 side. 130.

The queue 120 is a first-in first-out buffer (generally also called FIFO (First-In First-Out)) capable of holding a plurality of requests from the input / output bus 500, and stores a request for each request held in the queue 120. The address can be read by the signal line 121.

The cache memory 110 has a memory 220
And has a role of a cache memory of the memory 220 with respect to the input / output bus 500. That is, if an address related to a request from the input / output bus 500 hits the cache memory 110, the memory 220
The data in the cache memory 110 is supplied to the input / output bus 500 without accessing the memory, and in the case of a mishit, the memory 220 is accessed via the system bus 400 and the value is held in the cache memory 110. And supplies the value to the input / output bus 500. The address of each data held in the cache memory on the memory 220 can be read from the signal line 111.

The request reception control circuit 130 determines how to process a request from the input / output bus 500 via the signal line 501. Referring to FIG. 2, the request reception control circuit 130 includes a signal line 501.
The comparator 131 determines whether data having the same address as the request from the input / output bus 500 side is stored in the cache memory 110. Further, the request reception control circuit 130 uses the comparator 132 to determine whether a request having the same address as the request from the input / output bus 500 via the signal line 501 is held in the queue 120. Then, based on these results, the AND circuit 133 causes the cache memory 11
0 to be accessed (signal line 138) and queue 1
A signal indicating whether the signal should be registered in signal line 20 (signal line 139) is generated.

Referring to FIG. 3, the above-mentioned judgment in the request reception control circuit 130 indicates that the address related to the request from the input / output bus 500 does not match the address related to the request in the queue 120 (step 601), and When the address related to the request from the input / output bus 500 matches the address related to each data held in the cache memory 110 (step 602), control is performed to access the cache memory 110 (step 603). , No request is registered in the queue 120. On the other hand, the above does not apply (step 60)
1, 602), the request is registered in the queue 120 without accessing the cache memory 110 (step 604).

When the request is held in the queue 120, the input / output control device 100 attempts to acquire the right to use the system bus 400. When the usage right is acquired, the request at the head of the queue 120 is issued to the system bus 400.

Next, the operation of the input / output control device according to the first embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1 and FIG. 4, assuming that neither cache memory 110 nor queue 120 holds any data in the initial state, request A issued to input / output bus 500 at time T1 is , At the time T2. The request A acquires the right to use the system bus 400 at time T3, and is issued to the system bus 400 at time T5.

Assuming that the request B issued to the input / output bus 500 at the time T3 is for an address different from that of the request A, the queue 12
0, and held at the second stage of the system bus 400 at time T6.
Is issued to the system bus 400 at time T7.

At time T4, the input / output bus 500
Is assumed to be for an address different from both the request A and the request B, the request C is held in the second stage of the queue 120 at time T5,
At time T9, the right to use the system bus 400 is acquired, and at time T10, it is issued to the system bus 400 side.

Assuming that request D issued to input / output bus 500 at time T7 is for the same address as request A, read data for request A returns from memory 220 at time 7; Request D hits cache memory 110, and the data is obtained at time T8. Read data for request B and request C arrive from memory 220 at times T9 and T12, respectively. Here, the request D overtakes the request B and the request C, but since these are for different addresses, the result is logically guaranteed.

In the above example, request A and request D
Are related to the same address, and the other requests B and C are assumed to be related to addresses different from the other requests. However, as another example, the request C is further identical to the requests A and D. Consider the case of an address. Then, at the timing of FIG.
Overtakes request C, for example, request C
Is a write to the memory 220, there is a possibility that logical inconsistency may occur. In the present invention, in such a case, since the operation is performed as shown in FIG. 5 described below, no contradiction occurs.

Referring to FIGS. 1, 3 and 5, when request D is issued to input / output bus 500 at time T7, request C for the same address is held in queue 120 (step 601). , Request D is registered in the queue 120 (step 60).
4). Therefore, the request C and the request D are accessed to the memory 220 in this order, and there is no logical inconsistency.

As described above, according to the input / output control device according to the first embodiment of the present invention, the request acceptance control circuit 13
By providing 0, in the input / output control device 100 having the queue 120 and the cache memory 110, it is possible to perform control so as not to cause overtaking between requests related to the same address and to cause logical inconsistency between requests. it can.

Next, a second embodiment of the input / output control device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 6, an input / output control device 100 according to a second embodiment of the present invention includes a request for issuing a request to the system bus 400 side in addition to the first embodiment of FIG. An issuance control circuit 140 is further provided. This request issuance control circuit 140
A comparison is made between the address relating to the request at the beginning of 0 and the address relating to each data in the cache memory 110.

Referring to FIG. 7, the request issuance control circuit 140 compares the address of the first request in the queue 120 with the address of each data in the cache memory 110 (step 701). If not, the request is issued to the memory 220 (step 702). If the request is a read request, the return data is registered in the cache memory 110 (step 70).
3). As a result, data can be supplied by the cache memory 110 for the subsequent request for the same address. On the other hand, if the result of the comparison indicates that there is a match in the cache memory 110, the cache memory 110 is accessed (step 704), and the memory 220
Do not issue requests to.

Next, the operation of the input / output control device according to the second embodiment of the present invention will be described with reference to the drawings. Here, regarding the example described with reference to FIG. 4 for the first embodiment, it is shown that the performance is improved by the second embodiment. That is, a case where the request A, the request C, and the request D relate to the same address and only the request B relates to a different address will be described.

Referring to FIG. 3 and FIGS. 6 to 8, the cache memory 110 and the queue 12
Assuming that nothing is held at 0, the request A issued to the input / output bus 500 at time T1 is held at the head of the queue 120 at time T2, as in the first embodiment. The request A acquires the right to use the system bus 400 at time T3, and is issued to the system bus 400 at time T5.

At time T3, the input / output bus 500
Is issued in the same manner as in the first embodiment,
Assuming that the request is for an address different from the request A, the request A is held in the second stage of the queue 120 at time T4,
At time T6, the right to use the system bus 400 is acquired, and the system bus 400 is issued to the system bus 400 at time T7.

At time T4, the input / output bus 500
Is issued to the same address as the request A,
Since the data has not been registered yet, the time T
5 is held in the second stage of the queue 120. At time 7, the request is issued by the request issuance control circuit 140 because it has become the head of the queue 120. However, since the data for the request A related to the same address comes from the memory 220, the cache memory 110
(Steps 701 and 704), and the data is obtained at time T8.

Subsequently, when the request D is issued to the input / output bus 500 at the time T7, the request C is held in the queue 120 because the request C related to the same address is held in the queue 120 (step 601). (Step 604). Then, at the time T8, the data becomes the head of the queue 120, and since the data related to the same address is held in the cache memory 110 (step 701), the cache memory 110 is accessed at the time T9 (step 704). Is obtained.

As can be seen from the comparison between FIG. 5 according to the first embodiment and FIG. 8 according to the second embodiment, according to the input / output control device according to the second embodiment of the present invention, the request issuance control circuit By providing 140, even if a request does not hit the cache memory 110 at the time of registration in the queue 120, access to the cache memory 110 is attempted again immediately before issuing the memory so that unnecessary memory access is not issued. Can be controlled.

In each of the embodiments, for simplicity of explanation, the disk controller 30 on the input / output bus 500
Although the processing of the request from 1 to the memory 220 has been described, it goes without saying that the subject of the present invention is not limited to this.

[0039]

As is apparent from the above description, according to the present invention, in the input / output control device having the queue and the cache memory, the requests related to the same address do not pass each other, and the logical inconsistency between the requests does not occur. Can be controlled so as not to occur. In addition, even if a request does not hit the cache memory at the time of registration in the queue, access to the cache memory can be attempted again immediately before the memory is issued, so that unnecessary memory access can be controlled.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an input / output control device of the present invention.

FIG. 2 is a block diagram showing a configuration of a request acceptance control circuit in the input / output control device according to one embodiment of the present invention.

FIG. 3 is a diagram illustrating an operation of a request receiving process in the input / output control device according to the embodiment of the present invention.

FIG. 4 is a diagram showing operation timings in the input / output control device according to one embodiment of the present invention.

FIG. 5 is a diagram showing another operation timing in the input / output control device according to the embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a second embodiment of the input / output control device of the present invention.

FIG. 7 is a diagram illustrating an operation of a request issuing process in the input / output control device according to the second embodiment of this invention.

FIG. 8 is a diagram showing operation timing in the input / output control device according to the second embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 input / output control device 110 cache memory 120 queue 130 request reception control circuit 140 request issuance control circuit 210 processing device 220 memory 301, 302 disk control device 311 printer 400 system bus 500 input / output bus

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/08-12/12 G06F 13/28 G06F 13/36 G06F 13/38

Claims (3)

(57) [Claims] A first bus that connects a memory and a second bus that connects a request generation unit that generates a request to the memory, and that transfers a request from the request generation unit to the memory; A first-in first-out storage unit that holds the contents in sequence until issued, a cache memory that holds a part of the memory, and a request from the request generation unit that is accessed from the cache memory or stored in the first-in first-out storage unit. and a request reception control circuit for controlling whether said first-in first-out memory means, attempts to issue a respective request to the memory in the order in which they are held in the first-in first-out memory means, the request reception control circuit, said request generating means The same address as the access destination for the request from If the request does not exist in the first-in first-out storage means and the data at the same address exists in the cache memory with respect to the request from the request generation means, the cache memory is accessed, and If a request having the same address as an access destination for the request exists in the first-in-first-out storage unit, or if data of the same address does not exist in the cache memory for the request from the request generation unit, the request is stored in the first-in-first-out storage unit. An input / output control device for holding a request. A second bus connecting a first bus connecting a memory and a second bus connecting a request generating unit for generating a request to the memory, and transmitting a request from the request generating unit to the memory; In an input / output control device including a first-in first-out storage unit that holds the contents in order until issued, and a cache memory that holds a part of the memory, a request from the request generation unit is accessed from the cache memory, A request reception control circuit for controlling whether to hold the request in the first-in first-out storage means; and a request-issuance control circuit for controlling whether to access the cache memory before issuing the request held in the first-in, first-out storage means to the memory. An input / output control device comprising: 3. The request reception control circuit according to claim 1, wherein the request having the same address as the access destination with respect to the request from the request generation unit does not exist in the first-in first-out storage unit, and the same address with respect to the request from the request generation unit. Is present in the cache memory, the cache memory is accessed, and a request having the same address as a request from the request generation means is present in the first-in first-out storage means; When data at the same address does not exist in the cache memory for a request from the means, the request is stored in the first-in first-out storage means, and the request issuance control circuit stores the request in the first-in first-out storage means. If data at the same address exists in the cache memory for the requested request, access is made to the cache memory.If data at the same address does not exist in the cache memory for the request held in the first-in first-out storage means, 3. The input / output control device according to claim 2, wherein an attempt is made to issue the request to the memory.