JP5571327B2 - Latency reduction system, latency reduction method, and latency reduction program - Google Patents

Description

  The present invention relates to a latency shortening system, a latency shortening method, and a latency shortening program, and more particularly, to a latency shortening system, a latency shortening method, and a latency shortening program capable of reducing traffic.

  In general, as a cache control method, the cache of another processor is invalidated based on the Invalidate request so that only its own cache holds valid data, and the cache of the other processor is based on the Shared request. And sharing valid data with a plurality of caches is known.

  The Invalidate request is a request to invalidate the cache of a processor other than itself and retain valid data only in its own cache, so Invalidate or Shared for the same address from another processor received during Invalidate request processing Do not process requests together. This is because if they are processed together, different data exists in each of the plurality of processors as being valid, resulting in a coherency violation.

  To avoid this, while processing an Invalidate request, issue a retry instruction to the issuer of the request for the Invalidate and Shared requests sent from another processor and send the request to the issuer. Processing is performed one by one by encouraging re-loading.

Next, the Invalidate request process will be described in more detail with reference to FIG. (Patent Document 1 also discloses a system in which multiple multiprocessor nodes including a shared memory are connected to each other via a crossbar switch.)
The system shown in FIG. 5 includes a large number of multiprocessor nodes (hereinafter referred to as nodes) 100, 200, 300 including a shared memory. In the following description, the shared memory is simply called a memory.

  The nodes 100, 200, and 300 are connected via global switch / directory control units 150, 250, and 350. Each node 100, 200, 300 includes processors 101, 102, 201, 202, 301, 302, local switches 110, 210, 310, memory directory controllers 120, 220, 320, memories 140, 240, 340, directories 130, 160, 230, 260, 330, 360, and global switch directory controllers 150, 250, 350.

  When a request of the same address is issued to the memory 140 of the node 100 from the processors 201, 202, 301 of the nodes 200, 300, the request is sent to the global switch / directory control unit 150 via the global switch / directory control units 250, 350. The global switch / directory control unit 150 receives and processes the first request received from the CPU 201 among the three requests, and the remaining requests from the CPUs 202 and 301 are global until the processing of the first request is completed. Retries continue between the switch directory control unit 150 and the global switch directory control units 250 and 350.

  On the other hand, a shared request is a request that can have valid data in caches of multiple processors, so if a shared request for the same address is received from another processor during shared request processing, they are processed together. Are not coherency violations, so they are processed simultaneously. However, since an invalidate request from another processor is a coherency violation, in this case, a request reissue process is also performed.

  As described above, if a shared request for the same address from another processor is received during shared request processing, it is possible to process requests simultaneously, but in fact, invalidate and shared requests from multiple processors. Are issued one after another at irregular timing, so the control is also very complicated.

  Therefore, in general, in order to simplify the control, without distinguishing between Invalidate and Shared requests, it is possible to issue a retry instruction to a request related to the same address during request processing and reissue the request to the issuer. The method of processing in order one by one was taken.

JP 2003-150573 A

  However, since the number of issuers has increased in recent years due to the multi-core configuration, the frequency of address conflicts between requests has increased, and the above-described request processing method has led to a significant decrease in performance.

  An object of the present invention is to provide a latency shortening system, a latency shortening method, and a latency shortening program that solve the above-described problems.

  The latency shortening system of the present invention is a latency shortening system including a plurality of nodes. When a node issues a request simultaneously to the same address of the shared memory from the shared memory, the storage unit, and the plurality of issuers. , A registration unit that registers in the storage unit control information that identifies the issuer that issued the request, and returns data to the issuer of the request in response to the request issued first among the requests issued at the same time And transmitting means for determining the issuer based on the control information.

  The latency shortening method of the present invention is a latency shortening system including a plurality of nodes each having a shared memory and a storage means, and requests are issued when requests are issued simultaneously to the same address of the shared memory from a plurality of issuers. A registration step for registering in the storage means control information that identifies the issuer that issued the request, and among the requests issued at the same time, when the data is returned to the issuer of the request for the first issued request, And a first transmission step of determining an issuer based on the control information.

  The latency shortening program of the present invention causes the first computer to execute a determination process for determining the type of request, and in the determination process, a shared request indicating that the request is shared with a cache of another node and holds valid data. In the registration process, the control information for identifying the other node as the request issuer is registered in the storage means, and in the determination process, it is determined that the request is other than the Shared request. In this case, in the registration process, the control information that identifies the other node as the issuer of the request is not registered in the storage unit, and the remaining request is processed until the process of the first issued request is completed. The request is retried between the issuers of the remaining requests.

  The node of the present invention stores shared memory, storage means, and control information that identifies the issuer that issued the request when multiple requests are issued simultaneously to the same address in the shared memory. A registration means for registering with the means, and a transmission means for determining the issuer based on the control information when returning data to the issuer of the request for the first issued request among the simultaneously issued requests And.

  The present invention has an effect of reducing traffic by reducing latency and retry by simultaneously processing shared requests from a plurality of processors.

1 is an overall view of a latency shortening system according to an embodiment of the present invention. It is a block diagram of a global switch directory control unit. It is a flowchart which shows operation | movement at the time of receiving a request in the global switch directory control part of the node in which the memory of an object address exists. It is a flowchart which shows operation | movement at the time of receiving a request in the global switch directory control part of the node in which the memory of an object address exists. It is a flowchart which shows operation | movement at the time of receiving snoop in the global switch directory control part of the node where the memory of an object address does not exist. It is a whole view of the latency shortening system in related technology.

  Next, a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows an overall view of a latency shortening system 10 according to the first embodiment of the present invention.

  The overall view of the latency shortening system 10 of this embodiment differs from the system of FIG. 5 described above only in the configuration of the global switch / directory control unit (150, 250, 350).

  Similar to the system of FIG. 5, the latency shortening system 10 includes a large number of multiprocessor nodes (hereinafter referred to as nodes) 100, 200, and 300 including a shared memory. In the following description, the shared memory is simply called a memory.

  The nodes 100, 200, and 300 are connected to each other via global switch / directory control units 150, 250, and 350, respectively.

  The node 100 includes processors 101 and 102, a local switch 110, a memory / directory control unit 120, a memory 140, directories 130 and 160, and a global switch / directory control unit 150. The node 200 includes processors 201 and 202, a local switch 210, and a memory directory. The control unit 220, the memory 240, the directories 230 and 260, and the global switch / directory control unit 250, and the node 300 includes the processors 301 and 302, the local switch 310, the memory / directory control unit 320, the memory 340, the directories 330 and 360, and the global switch directory. And a control unit 350.

  Before describing each component of the latency shortening system 10 in the present embodiment, the basic concept of the present invention will be described in comparison with a commonly used technique.

  First, a detailed description will be given of request processing of a latency shortening system using a commonly used technique.

  When a shared request for the same address is issued from the processors 201, 202 and 301, the request is sent from the local switches 210 and 310 via the global switch directory control units 250 and 350 to the global directory control unit 150 of the node 100 where the memory exists. Sent to. Here, it is assumed that the arrival order of requests to the global directory control unit 150 is the order from the processor 201, from the processor 202, and from the processor 301.

  When the global directory control unit 150 receives a request from the processor 201, the global directory control unit 150 issues a request to the memory 140, indexes the directory 160, and holds data in the cache with M (Modified) or E (Exclusive) (MESI protocol). If there is a processor, issue a snoop. (If the cache is SI (Shared Invalid), data is not transferred from the cache even if a snoop is issued, so the data is read from the memory without issuing a snoop.) This case is when there is no valid cache and the snoop is Not issued.

  The global directory control unit 150 continues to retry without accepting subsequent requests from the processor 202 and the processor 301 until the request processing from the processor 201 is completed. Then, when the processing for the request from the processor 201 is completed and the global directory control unit 150 returns the reply data to the processor 201, the global directory control unit 150 responds to the subsequent requests from the processor 202 and the processor 301. The one that arrives earlier is received and processed, and when the processing is completed, the last request is received and processed.

  As can be seen from the above description, in this system, the same data is read three times in the memory.

  On the other hand, the request processing is performed as follows in the latency shortening system 10 of the present embodiment.

  When a shared request is issued from the processors 201, 202, and 301 to the same address, the request is sent from the local switch 210 and 310 via the global switch directory control unit 250 and 350 to the global address of the node 100 where the memory exists. Sent to the directory control unit 150. Here, it is assumed that the arrival order of requests to the global directory control unit 150 is the order from the processor 201, the order from the processor 202, and the order from the processor 301.

  If the global directory control unit 150 receives subsequent requests from the processor 202 and the processor 301 by the time the request from the processor 201 is completed, the global directory control unit 150 does not retry and issues the request issuer information (processors 201, 202, 301). ) And when the reply data for the request is received from the memory, the reply data is broadcast to the issuer processor of the request in the issuer information.

  As described above, in the system shown in FIG. 5 described above, the memory is read up to three times for three requests, but in this embodiment, only one read is required and the latency can be shortened. .

  In the present embodiment, the request processing when a snoop is issued is as follows.

  The cache of the processor 301 holds data in EM (Exclusive Modified). When a shared request for data at the same address is issued from the processors 201 and 202, the request is sent from the local switch 210 to the global switch directory control. The data is sent to the global directory control unit 150 of the node 100 where the memory exists via the unit 250. Here, it is assumed that the arrival order of the requests to the global directory control unit 150 is the order from the processor 201 and the order from the processor 202.

  When receiving the request from the processor 201, the global directory control unit 150 issues a request to the memory 140, indexes the directory (160), and issues a snoop.

  When a request from the subsequent processor 202 is received after the request from the processor 201 is received until it is read from the message storage buffer, the processor 202 is registered in the issuer information (processors 201 and 202) and Carry out publisher information with Snoop. When data is transferred from the cache of the CPU 301, the global switch / directory control unit 350 broadcasts data to the processors 201 and 202 registered in the issuer information.

  As described above, in the system of FIG. 5, the request from the processor 202 is not processed until the processing of the processor 201 is completed, but in the present embodiment, the processing is performed simultaneously, so that the latency can be shortened.

  Next, each component of the latency shortening system 10 of this embodiment is explained in full detail.

  Since all of the nodes 100, 200, and 300 have the same configuration, each part of the node 100 will be described.

  The local switch 110 is connected to the processors 101 and 102, the memory / directory control unit 120, and the global switch / directory control unit 150. The local switch 110 routes the issued request, snoop, response to the snoop (hereinafter referred to as response), and response to the request (hereinafter referred to as reply) based on the destination.

  The memory / directory control unit 120 receives all requests for access to the memory 140, performs access to the memory 140, indexes the directory 130, and if there is a valid cache, A snoop process is performed on it. Then, the memory / directory control unit 120 returns it to the request issuing source as a reply when the response and the data from the memory are prepared.

  Directories 130 and 160 manage the cache state of the processor. The management targets of the directory 130 connected to the memory / directory control unit 120 are the processors 101 and 102 in the node 100 and the global switch / directory control unit 150 indicating other processors. The management targets of the directory 160 connected to the global switch / directory control unit 150 are the processors 201, 202, 301, and 302 of the other nodes 200 and 300.

  The global switch / directory control unit 150 is connected to the global switch / directory control units 250 and 350 of the other nodes 200 and 300, and routes requests, snoops, responses, and replies according to the destinations. When the requests from the other nodes 200 and 300 and the snoop from the local switch 110 are received, the global switch / directory control unit 150 indexes the directory 160, and if there is a cache having valid data, the global switch The directory control unit 150 performs a snoop process for the processor.

  Next, the control in which the global switch / directory control units 150, 250, and 350 register and process a Shared request with an address conflict will be described in detail.

  As shown in FIG. 2, each of the global switch / directory control units 150, 250, and 350 includes an area 1 that functions when a memory at a target address exists and an area 2 that functions when a memory at a target address does not exist. The

  Area 1 of the global switch / directory control unit 150 includes an arbitration circuit 150-1, an address matching circuit 150-2, a registration determination circuit 150-3, a control register 1150-4, a message storage buffer 150-5, and an acceptability determination register 150. -6, issuer registration register 150-7, issuer registration register 150-8, retry buffer 150-9, message issue / generation circuit 150-10, arbitration circuit 150-11, and message broadcast circuit 150-12 .

  The area 2 of the global switch / directory control unit 150 includes an arbitration circuit 350-1, a control register 350-2, a message storage buffer 350-3, an issuer information registration register 350-4, and a message issue / generation circuit 350-5. And a message broadcast circuit 350-5.

  First, the operation of the region 1 that functions when the memory of the target address exists in the node will be described.

  The arbitration circuit 150-1 arbitrates messages from the local switch 110 and messages from the other nodes 200 and 300 transmitted in random order, and determines which message is to be processed.

  The address matching circuit 150-2 compares the address of the message selected by the arbitration circuit 150-1 with the address of a valid request or snoop registered in the message storage buffer 150-5. If they match, the match result and the value in the acceptability determination register 150-6 of the matched entry are read and notified to the registration determination circuit 150-3.

  The registration determination circuit 150-3 determines whether or not registration is possible based on the address match result and acceptability determination information notified from the address match circuit 150-2 for the request. The acceptance determination information is stored in the acceptance determination register 150-6. The acceptability determination information will be described in detail below.

  If there is no address match, the registration determination circuit 150-3 registers the request in the message storage buffer 150-5, and registers the issuer information in the issuer registration registers 150-7 and 150-8. On the other hand, if there is an address match, if the acceptability flag in the acceptability determination information is 1 (acceptable) and the request type is a Shared request, the registration determination circuit 150-3 registers the issuer information as the issuer It is additionally registered in the register 150-7 or the issuer registration register 150-8.

  Whether the issuer information is registered in the issuer registration register 150-7 or the issuer registration register 150-8 is determined according to the issuer registration register instruction flag in the acceptance determination information. All other cases are stored in the retry buffer 150-9 and retried.

  In the control register 150-4, control flags necessary for processing each request or snoop stored in the message storage buffer 150-5 are prepared for the number of entries. That is, the control register 150-4 stores control information such as an entry valid flag, issue request flag, response reception flag, reply data reception flag, reply issued flag, writeback reception flag, and data transfer flag as the control flag. Has been.

  All flags are cleared when the entry Valid becomes 0.

  The message storage buffer 150-5 is a buffer that stores requests, snoops, response data, and reply data.

  The acceptance determination register 150-6 stores acceptance determination information. The acceptability determination information includes four types of an acceptability flag, a shared request flag, a registration period flag, and an issuer registration register instruction flag.

  The acceptance flag indicates whether or not subsequent shared requests can be accepted. The acceptance flag is 1 when the Shared request flag is 1 and the registration period flag is 1.

  The Shared request flag is a flag indicating whether the request is a Shared request. The Shared request flag is 1 if it is a Shared request as a result of the type confirmation at the time of request registration.

  The registration period flag indicates a period during which a subsequent request can be accepted. It is 1 during the period from the reception of the request until the reception of the response with transfer data, the write-back data, or the reply data.

  The issuer registration register instruction flag is information indicating whether issuer information is registered in the issuer registration register 150-7 or the issuer registration register 150-8. The issuer registration register instruction flag becomes 1 when a snoop is issued for the request, and indicates registration in the issuer registration register 150-8. On the other hand, when the issuer registration register instruction flag is 0, registration in the issuer registration register 150-7 is performed.

  The issuer registration register 150-7 and the issuer registration register 150-8 register a request issuer. The issuer registration register 150-7 and the issuer registration register 150-8 have a plurality of 1-bit storage units, and these 1-bit storage units have a one-to-one correspondence with a plurality of processors in the system and receive a request. The content of the 1-bit storage unit corresponding to the processor indicated by the issuer information in the message is 1.

  Note that the register to be registered is determined based on the value of the issuer registration register instruction flag of the acceptance determination register 150-6, but there is no difference in the registration method.

  Both the issuer registration register 150-7 and the issuer registration register 150-8 are cleared when the entry Valid becomes 0.

  The retry buffer 150-9 stores a request when the result of the registration determination circuit 150-3 is a retry, and issues a retry instruction to the issuer at this time.

  The message issuance generation circuit 150-10 determines an entry to be issued from the issuance request flag in the control register 150-4. Then, the message issuance generation circuit 150-10 reads the information of the control register 150-4, the message storage buffer 150-5, the issuer registration register 150-7, and the issuer registration register 150-8 of the selected entry, From the index and update of the directory 160 and the information in the control register 150-4, it is specified and generated whether the message to be issued is a request, a snoop, a response, or a reply.

  The arbitration circuit 150-11 arbitrates the normal message sent to the other nodes 200 and 300 from the message issuing / generating circuit sent in random order and the retry message from the retry buffer 150-9, and processes either message. Is to decide.

  The message / broadcast circuit 150-12 is selected based on the message generated by the message issuing / generating circuit 150-10 and the issuer information (information of the issuer registration register 150-7 and the issuer registration register 150-8). ), Broadcast the reply or reply data to all the registered processors with reference to the issuer information at the time of reply or reply data.

  Next, the operation of the area 2 that functions when the memory of the target address does not exist in the node will be described.

  The arbitration circuit 350-1 arbitrates the message from the local switch 310 and the message from the other nodes 100 and 200 sent in random order, and determines which message is to be processed.

  In the control register 350-2, there are prepared as many control flags as the number of entries necessary for processing the snoop stored in the message storage buffer 350-3. Control information such as an entry valid flag, an issue request flag, a response reception flag, and a data transfer flag is stored in the control register 350-2 as control flags.

  The message storage buffer 350-3 is a buffer that stores snoop and response data.

  The issuer registration register 350-4 registers the issuer of the request, and registers issuer information brought along with the snoop.

  The message issue / generation circuit 350-5 determines an entry to be issued based on the issue request flag of the control register 350-2. The message issuance / generation circuit 350-5 reads the information in the control register 350-2, message storage buffer 350-3, and issuer registration register 350-4 of the selected entry, and determines whether the issued message is a snoop. Identify and generate a response.

  The message broadcast circuit 350-6 refers to the issuer information at the time of data transfer based on the message generated by the message issue / generate circuit 350-5 and the issuer information (value of the issuer registration register 350-4). Then, the data is broadcast to all registered processors.

  Since the processors 101, 102, 201, 202, 301, 302, the local switches 110, 210, 310, the memory / directory control units 120, 220, 320, the memories 140, 240, 340, and the directories 130, 160, 230.260, 330, 360 in FIG. 1 are well known, a detailed description thereof will be omitted.

  Next, the operation of this embodiment will be described with reference to the drawings.

  The operation of the global switch / directory control unit 150, 250, 350 of FIG. 1 will be described with reference to the flowcharts of FIGS.

  FIGS. 3A and 3B are operations when a request is received by the global switch / directory control unit 150 of the node where the memory of the target address exists.

  When receiving a request from the other nodes 200 and 300, the arbitration circuit 150-1 refers to the type and determines whether it is an Invalidate request or a Shared request (S0 in FIG. 3A).

  In the case of an Invalidate request, address comparison is performed by the address matching circuit 150-2, as in the system of FIG. If there is no match, the registration determination circuit 150-3 registers the request in the message storage buffer 150-5 and performs processing. If there is a match, the registration determination circuit 150-3 registers the request in the retry buffer 150-9 and performs a retry. (S26 in FIG. 3-A).

  In the case of a Shared request (S1 in FIG. 3-A), the address matching circuit 150-2 performs address comparison (S2 in FIG. 3-A). If there is no match, the registration determination circuit 150-3 registers the request in the message storage buffer 150-5, sets the content of the 1-bit storage unit corresponding to the issuer of the issuer registration register 150-7 to 1, and performs control. The entry valid flag and issue request flag of the register 150-4 are set to 1 (S3 in FIG. 3A).

  The message issuance / generation circuit 150-10 determines an entry to be issued from the entries whose issue request flag is 1, and registers the control register 150-4, the message storage buffer 150-5, and the issuer for the entry. The values stored in the register 150-7 and the issuer registration register 150-8 are read, and when the reading is completed, the issue request flag of the control register 150-4 is set to 0.

  The message generation / issuance circuit 150-10 generates a request from the read information, issues it to the memory, and indexes the directory 160 (S4 in FIG. 3A). The message generation / issue circuit 150-10 determines whether there is a valid cache from the index result of the directory 160 (S5 in FIG. 3-A).

  If there is no valid cache, the message generation / issuance circuit 150-10 waits for reply data from the memory (S6 in FIG. 3A). When the reply data is received, the reply data is sent to the message storage buffer 150-5. And the reply data reception flag and issue request flag of the control register 150-4 are set to 1.

  The message issuance / generation circuit 150-10 determines an entry to be issued from the entries whose issue request flag is 1, and registers the control register 150-4, the message storage buffer 150-5, and the issuer for the entry. The values stored in the register 150-7 and the issuer registration register 150-8 are read, and when the reading is completed, the issue request flag of the control register 150-4 is set to 0.

  The message generation / issuance circuit 150-10 generates reply data from the read information, and notifies the message broadcast circuit 150-12 of the value of the issuer registration register 150-7 as issuer information, and the control register 150- Set the entry valid flag of 4 to 0.

  The message broadcast circuit 150-12 that has received the reply data and the issuer information from the message issue / generate circuit 150-10 broadcasts the reply data to all the processors registered in the issuer information (S7 in FIG. 3-A). .

  If there is a valid cache from the index result of the directory 160 (S8 in FIG. 3A), the message issuing / generating circuit 150-10 generates a snoop and issues it to the effective cache. At that time, the value of the issuer registration register 150-7 is carried around together (S8 in FIG. 3-A).

  When a snoop is issued, a response from the cache is waited (S9 in FIG. 3-A). When a response is received, the response reception flag of the control register 150-4 is set to 1, and further, data is transferred from the cache according to the response type. (S10 in FIG. 3-B).

  If there is no data transfer from the response determination result, it waits for reply data from the memory (S11 in FIG. 3-B), and when reply data is received, it registers the reply data in the message storage buffer 150-5 and controls the control register. Set the reply data reception flag and issue request flag of 150-4 to 1.

  The message issuance / generation circuit 150-10 determines an entry to be issued from the entries whose issue request flag is 1, and controls the control register 150-4, the message storage buffer 150-5, and the issuer registration register of the entry The values stored in 150-7 and issuer registration register 150-8 are read. Then, the message issuing / generating circuit 150-10 sets the issue request flag of the control register 150-4 to 0 when the reading is completed.

  The message generation / issuance circuit 150-10 generates reply data from the read information, and in each 1-bit storage section corresponding to the issuer registration register 150-7 and the issuer registration register 150-8 as issuer information Is obtained by notifying the message broadcast circuit 150-12 of the logical sum of the two values, and the entry valid flag of the control register 150-4 is set to 0.

  The message broadcast circuit 150-12 that has received reply data and issuer information from the message issue / generate circuit 150-10 broadcasts reply data to all the processors registered in the issuer information (S12 in FIG. 3-B). .

  If it is determined from the response determination result that there has been data transfer (S10 in FIG. 3-B), the issue request flag and the data transfer flag in the control register 150-4 are set to 1, and there is also write-back data. In this case, set the write-back reception flag to 1.

  If reply data is received from the memory before receiving a response to the snoop, the data is registered in the reply data reception flag of the control register 150-4 and the message storage buffer 150-5.

  The message issuance / generation circuit 150-10 determines an entry to be issued from the entries whose issue request flag is 1, and controls the control register 150-4, the message storage buffer 150-5, and the issuer registration register of the entry 150-7 and the issuer registration register 150-8 are read, and when the reading is completed, the issue request flag is set to 0.

  The message generation / issuance circuit 150-10 refers to the write-back reception flag (S13 in FIG. 4) and the reply-data reception flag (S14 in FIG. 4) from the read information. When the flag is 0, a reply is generated and the value of the issuer registration register 150-7 is notified to the message broadcast circuit 150-12 as issuer information. Then, the message issuing / generating circuit 150-10 sets the reply issued flag in the control register 150-4 to 1.

  The message broadcast circuit 150-12 that has received the reply and issuer information from the message issuing / generating circuit 150-10 broadcasts the reply to all the processors registered in the issuer information (S15 in FIG. 3-B).

  Further, it waits for reply data from the memory (S16 in FIG. 3B), and when reply data is received, refers to the reply issued flag in the control register 150-4. When the reply issued flag is 1, the issuer registration register 150-8 is referred to (S17 in FIG. 3-B), and when there is no processor registered in the issuer registration register 150-8, the control register 150-4 Set the entry valid flag to 0.

  If there is a processor registered in the issuer registration register 150-8, the reply data is registered in the message storage buffer 150-5, and the reply data reception flag and issue request flag in the control register 150-4 are set to 1. . The message issuance / generation circuit 150-10 determines an entry to be issued from an entry whose issuance request flag is 1, and controls the control register 150-4, message storage buffer 150-5, and issuer registration register 150-7 of the entry. And the value stored in the issuer registration register 150-8 are read, and when the reading is completed, the issue request flag of the control register 150-4 is set to 0.

  The message generation / issuance circuit 150-10 generates reply data from the read information. Then, the message generation / issue circuit 150-10 notifies the message broadcast circuit 150-12 of the value of the issuer registration register 150-8 as issuer information, and sets the entry valid flag of the control register 150-4 to 0. The message broadcast circuit 150-12 that has received the reply data and issuer information from the message issue / generate circuit 150-10 broadcasts the reply data to all the processors registered in the issuer information (S18 in FIG. 3-B). ).

  Next, when the write-back reception flag is 0 and the reply data reception flag is 1, the message issuing / generating circuit 150-10 generates two types of reply and reply data. The message issuance / generation circuit 150-10 notifies the message broadcast circuit 150-12 of the value of the issuer registration register 150-7 for the reply, and the value of the issuer registration register 150-8 for the reply data. Set the entry valid flag of the control register 150-4 to 0.

  However, when nothing is registered in the issuer registration register 150-8, reply data is not generated.

  The broadcast circuit 150-12 that has received the reply information from the message issuance / generation circuit 150-10 and the reply source data corresponding to the reply data broadcasts the reply and reply data to all the processors registered in the publisher information (see FIG. 4 S19).

  Next, when the write-back reception flag is 1 (S13 in FIG. 3-B), two types of reply and reply data write-back data are generated, and the value of the issuer registration register 150-7 is set for reply. As for reply data, the value of the issuer registration register 150-8 is notified to the message broadcast circuit 150-12. Again, if nothing is registered in the issuer registration register 150-8, no reply data is generated.

  The message broadcast circuit 150-12 that has received the issuer information corresponding to the reply and reply data from the message issuance / generation circuit 150-10 broadcasts the reply and reply data to all the processors registered in the issuer information.

  The write back request for the memory is issued after the reply data for the Shared request is received, and when the reply for the write back is received, the entry valid flag of the control register 150-4 is set to 0 (S20 in FIG. 3-B).

  In the case of a Shared request, address comparison is performed by the address matching circuit 150-2 (S2 in FIG. 3A). If there is a match, the value of the acceptability determination register 150-6 of the matched entry is extracted. Then, a determination is made as to whether or not acceptance is possible from the acceptance flag in the acceptance determination register (S21 in FIG. 3-A). If the acceptance is not possible, a message is registered in the retry buffer 150-9 to retry (FIG. 3). A's S22).

  On the other hand, if it can be accepted, the issuer registration register instruction flag is referred to (S23 in FIG. 3-A), and if the issuer registration register instruction flag is 0, it corresponds to the issuer of the issuer registration register 150-7. The bit is set to 1 (S24 in FIG. 3-A), and if the issuer registration register instruction flag is 1, the bit corresponding to the issuer of the issuer registration register 150-8 is set to 1 (S25 in FIG. 3-A). .

  FIG. 4 shows the operation when the snoop is received in the global switch / directory control unit 250 of the node where the memory of the target address does not exist.

  When the snoop is received, the arbitration circuit 350-1 registers the snoop message in the message storage buffer 350-3, and registers the issuer information carried together in the issuer registration register 350-4. Then, the arbitration circuit 350-1 sets the entry valid flag and issue request flag of the control register 350-2 to 1 (S1 in FIG. 4).

  The message issuance / generation circuit 350-5 refers to the control register 350-2 and determines an entry to be issued from an entry whose issue request flag is “1”. Then, the message issuing / generating circuit 350-5 reads the contents of the control register 350-2, message storage buffer 350-3, and issuer registration register 350-4 of the entry, and when the reading is completed, the control register 350-2 Set the issuance request flag to 0.

  The message issuing / generating circuit 350-5 newly generates a snoop from the read information and issues it to the cache having valid data via the local switch 110 (S2 in FIG. 4).

  When a snoop is issued, a response from the cache is waited (S3 in FIG. 4). When a response is received, the arbitration circuit 350-1 sets the response reception flag of the control register 350-2 to 1, and if there is data transfer, the data transfer flag Is set to 1, and the issue request flag is set to 1.

  The message issuance / generation circuit 350-5 determines an entry to be issued from an entry whose issuance request flag is 1, and includes a control register 350-2, a message storage buffer 350-3, and an issuer registration register 350-4. The issuance request flag is set to 0 when reading is completed.

  The message issuing / generating circuit 350-5 refers to the data transfer flag of the control register 350-2 from the read value (S4 in FIG. 4), generates a response when there is no data transfer, and returns it to the snoop issuer Then, the entry valid flag of the control register 350-2 is set to 0 (S5 in FIG. 4).

  When the data transfer flag is 1, the message issuing / generating circuit 350-5 generates two types of response and data, and sends the response to the snoop issuer and the data together with the value of the issuer registration register 350-4 Is sent to the broadcast circuit 350-6, and the entry valid flag in the control register 350-2 is set to zero.

  Upon receiving the response and data from the message issuing / generating circuit 350-5 and the corresponding issuer information, the message broadcast circuit 350-6 broadcasts the data to all the processors registered in the issuer information (S6 in FIG. 4). ).

  As described above, in this embodiment, since the publisher information is registered and a plurality of messages can be processed together without retrying, the latency can be shortened.

100, 200, 300 Node 101, 102, 201, 202, 301, 302 Processor 110, 210, 310 Local switch 120, 220, 320 Memory directory control unit 130, 230, 330 Directory 140, 240, 340 Memory 150, 250 , 350 Global switch directory control unit 160, 260, 360 Directory 150-1 Arbitration circuit 150-2 Address matching circuit 150-3 Registration determination circuit 150-4 Control register 150-5 Message storage buffer 150-6 Acceptance determination register 150 -7 Issuer registration register 150-8 Issuer registration register 150-9 Retry buffer 150-10 Message issue / generation circuit 150-11 Arbitration circuit 150-12 Message block De Cast circuit 350-1 arbitration circuit 350-2 control register 350-3 message storage buffer 350-4 issuing registration register 350-5 message issuing-generating circuit 350-6 message broadcast circuit

Claims (24)

In a latency reduction system that includes multiple nodes,
The node is
Multiple processors,
Shared memory,
While processing a first request for processing a specific storage area in the shared memory, the second request is different from the first request in response to a second request for processing the specific storage area. Creating means for accepting the request without retrying and creating control information for identifying the first processor that has executed the second request among the plurality of processors;
Transmission means for transmitting the reply data as a reply to the second request to the first processor based on the control information in response to transmitting reply data for the first request. Latency reduction system. The node comprises a cache;
The latency reduction according to claim 1, wherein the transmission means determines the first processor based on the control information when data is received from the cache or the shared memory in response to the first request. system. The node includes a determination unit that determines the type of request,
When the determining means determines that the first request and the second request are shared requests indicating that the valid data is shared with the cache of another node, the creating means determines that the other node Create control information to identify the request issuer,
When the determination unit determines that the first request or the second request is other than the Shared request, the generation unit does not generate control information that identifies the other node as the request issuer. The latency shortening system according to claim 2. Each of the nodes is
A directory that manages the shared memory of the local node and other nodes;
A directory controller that searches the directory to determine whether there is a valid cache;
If there is valid cache to the other nodes, to generate a snoop for the other nodes having a valid cache together with control information identifying the own node, and message issuing-generating circuit which issues said snoop ,
The latency shortening system according to claim 2, further comprising:   5. The other node that has received the snoop reads data from the valid cache and transmits the data to the own node specified by the control information received together with the snoop. The latency reduction system described.   6. The latency shortening system according to claim 5, wherein when the other node reads the data from the valid cache, the other node returns a response to the own node that is the issuing source of the snoop. While processing a first request for processing a specific storage area in the shared memory, the second request is different from the first request in response to a second request for processing the specific storage area. with accepted without retrying, among multiple processors, a creation step of creating a control information identifying the first processor implementing the second request,
A transmission step of transmitting the reply data as a reply to the second request to the first processor based on the control information in response to transmitting reply data for the first request. To reduce latency.   8. The latency reduction method according to claim 7, wherein, in the transmission step, the first processor is determined based on the control information when data is received from a cache or the shared memory in response to the first request. . A determination step for determining the type of request;
In the determination step, when it is determined that the first request and the second request are shared requests that share valid data with caches of other nodes and hold valid data, in the creation step, the other nodes Create control information to identify the request issuer,
In the determination step, when it is determined that the first request or the second request is other than the Shared request, control information for identifying the other node as a request issuer is generated in the creation step The latency shortening method according to claim 7 or 8, wherein: A determination step of determining whether there is a valid cache by searching a directory managing the shared memory of the own node and other nodes;
A snoop generation step for generating a snoop when the other node has a valid cache; and
An issuing step of with respect to the other node, issuing said snoop with valid cache along with said control information,
10. The latency shortening method according to claim 8 or 9, wherein:   The other node that has received the snoop has a second transmission step of reading data from the valid cache and transmitting the data to the own node specified by the control information received together with the snoop. The latency shortening method according to claim 10, wherein:   12. The latency shortening method according to claim 11, further comprising: a return step of returning a response to the own node that is the source of the snoop when the other node reads the data from the valid cache. . While processing a first request for processing a specific storage area in the shared memory, the second request is different from the first request in response to a second request for processing the specific storage area. together with accepted without retrying, among multiple processors, a creation function for creating control information for identifying the first processor implementing the second request,
In response to transmitting reply data for the first request, the first processor is caused to execute a transmission function for transmitting the reply data as a reply to the second request based on the control information. A latency reduction program.   14. The latency shortening program according to claim 13, wherein in the transmission function, the first processor is determined based on the control information when data is received from the cache or the shared memory in response to the first request. . To execute the determination process for determining the type of requests,
In the determination process, when it is determined that the first request and the second request are shared requests that share valid data with caches of other nodes and hold valid data, Create control information to identify the request issuer,
In the determination process, when it is determined that the first request or the second request is other than the Shared request, the creation function creates control information that identifies the other node as a request issuer. 15. The latency shortening program according to claim 13 or 14, wherein: A determining process of determining whether there is a valid cache by searching the directory for managing a shared memory of multiple nodes,
A snoop generation process for generating a snoop when another node of the plurality of nodes has a valid cache; and
Issuing process for issuing the snoop to the other node having the valid cache together with the control information for identifying the own node ;
16. The latency shortening program according to claim 14 or 15, wherein: In the other node,
When the snoop is received, a second transmission process for reading data from the valid cache and transmitting the data to the own node specified by the control information received together with the snoop is sent to the second computer. The latency shortening program according to claim 16, wherein the latency shortening program is executed. In the other node,
The latency according to claim 17, wherein when the data is read from the valid cache, the second computer is caused to execute a return process for returning a response to the local node that is the snoop issuer. Abbreviation program. While processing a first request for processing a specific storage area in the shared memory, the second request is different from the first request in response to a second request for processing the specific storage area. with it accepted without retrying, among multiple processors, and generating means for generating control information specifying the first processor implementing the second request,
Transmission means for transmitting the reply data as a reply to the second request to the first processor based on the control information in response to transmitting reply data for the first request. Node to perform. With a cache,
The node according to claim 19, wherein the transmitting unit determines the first processor based on the control information when data is received from the cache or the shared memory in response to the first request. A determination means for determining the type of request;
When the determining means determines that the first request and the second request are shared requests indicating that the valid data is shared with the cache of another node, the creating means determines that the other node Create control information to identify the request issuer,
Wherein when the first request or the second request by determining means is determined to be other than the Shared request memorize means control information the generating means to identify the issuer of the request to the other nodes The node according to claim 20, wherein the node is not created. A directory that manages the shared memory of the local node and other nodes;
A directory controller that searches the directory to determine whether there is a valid cache;
If there is valid cache to the other nodes, to generate a snoop, to other nodes having a front Symbol valid cache along with the control information, and message issuing-generating circuit which issues said snoop,
The node according to claim 20 or 21, characterized by comprising: When receiving the snoop reads data from the valid cache, the node of claim 22, wherein the transmitting the data to the node specified by the control information received together with the snoop.   The node according to claim 23, wherein when the data is read from the valid cache, a response is returned to the node that issued the snoop.

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