JP3259095B2 - Data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method,
In particular, the present invention relates to a data transfer method having a channel control device for transferring data from a main storage device connected to a central processing unit to an input / output device.

[0002]

2. Description of the Related Art In a conventional data transfer method, a channel control device is connected to a main storage device and a central processing unit, controls a plurality of channel devices, and controls a main input / output device connected to each channel device. It has a prefetch data buffer shared by a plurality of channels used when data is transferred from the storage device. Since this prefetch data buffer has a fixed storage capacity, a fixed prefetch data buffer is prepared regardless of the performance of the input / output device connected under the channel.

[0003]

In the above-mentioned conventional data transfer method, since the size of the prefetch data buffer per channel device is fixed, the input / output devices having different transfer performances are controlled under the channel device. Is connected, a prefetch data buffer necessary for transfer of a high-performance I / O device is prepared, so that a prefetch data buffer connected to an I / O device with a low transfer performance is wasted. was there. Further, in recent years, the speed of the input / output device has been further increased, and the combination of an input / output device having a high transfer performance and a low input / output device cannot be avoided. Therefore, there is a problem that waste of the prefetched data buffer is increased.

[0004]

According to a data transfer method of the present invention, an input / output device is connected to a main storage device and a central processing unit, controls a plurality of channel devices, and is connected to the main storage device and the channel devices. A shared prefetch data buffer for temporarily storing data to be transferred to the plurality of channel devices; and a channel device or an input / output device for each data transfer from the central processing unit. First means for receiving the transfer performance of the prefetch data buffer, second means for managing the use status of the prefetch data buffer and securing a use area of the prefetch data buffer according to the transfer performance, and Third means for performing memory access according to a use area and controlling data transfer between the main storage device and the input / output device .

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, in which channel devices 400 to 40 are controlled under a channel control device 300.
4 shows a case where four are connected.

In FIG. 1, a central processing unit 100 issues an input / output instruction 1 to a channel control unit 300 when performing input / output processing on data for arithmetic processing. The input / output instruction 1 includes information indicating the transfer performance of the channel device that performs data transfer. The main storage device 200 is connected to the central processing unit 100 and the channel control device 300,
Read and write data of the input / output device required by the central processing unit 100 via the channel device 400,
For one memory request 3 issued from the channel control device 300, a one-word memory reply 4 is transmitted. The channel control device 300 controls the channel device according to the input / output command 1 issued by the central processing unit 100 to transfer data between the main storage device and the input / output device. The channel devices 400, 401,...
503, and transfers the transfer output data 7 received from the channel control device 300 to the input / output device 500.

The channel control circuit 301 decodes the input / output command 1 received from the central processing unit 100, and
The data transfer control circuit 3 secures a prefetch data buffer area corresponding to the transfer performance of the channel device indicated by
04 and the channel device 400. The prefetch data buffer 302 is a buffer that writes and reads the transfer data read from the main storage device 200 to the address specified by the prefetch data buffer control circuit 303 before the transfer.

The prefetch data buffer control circuit 303
The write address 16 and the read address 15 are generated in accordance with the available area of the prefetch data buffer 302 allocated to the channel device to be transferred with reference to the prefetch data buffer management display flag 305, and the data transfer control circuit 304 The number of times of memory access is limited to control the amount of data in the prefetch data buffer 302. When the used area of the prefetch data buffer 302 allocated to the channel device becomes full, a request suppression signal 13 is output, and the request is output in the order in which memory requests were made. When the channel device number of the memory request is stored, the write address 16 of the prefetch data buffer 302 is output each time the data input register 306 receives the memory reply data 4, and the memory reply data is output to the channel device. Delivering a read address 15 of the prefetch data buffer 302 and the channel unit number 11 to be transferred.

The data transfer control circuit 304 responds to the data transfer instruction 8 of the channel control circuit 301 to
0 is accessed by the memory request 3. The memory request 3 for each channel device is continuously transmitted until the request suppression signal 13 for each channel is output from the prefetch data buffer control circuit 303, and the memory request 3 is transmitted once. Each time the request is transmitted, the request transmission signal 14 for each channel device is transmitted to the prefetch data buffer control circuit 303.

One flag is assigned to the display flag 305 per unit area of the prefetch data buffer 302, and is composed of a channel device number and an in-use bit. The channel device number and busy bit “1” are set when the channel device connected to 300 is in use for data transfer, and the busy bit 0 when not in use.
The setting and resetting are performed by the channel control circuit 301 and the prefetch data buffer 302 is always set.
Is displayed.

The data input register 306 is a register for receiving the memory reply data 4 from the main storage device 200 and writing it into the prefetch data buffer 302.
The data output register 307 stores the prefetch data buffer 3
This is a register for transmitting the data 6 read from the data 02 to the channel device designated by the channel device number 11 output from the prefetch data buffer control circuit 303.

Next, the operation of this embodiment will be described.
The central processing unit 100 issues the input / output command 1 to the channel control device 300. In the channel control device 300, the channel control circuit 301 decodes the input / output command 1 to check the transfer performance of the channel device. Referring to the display signal 10, it is determined whether the input / output instruction 1 is executable based on the use status of the prefetch data buffer 302. If the use area of the prefetch data buffer 302 necessary for executing the input / output instruction 1 is sufficient. If not, it notifies the central processing unit 100 that execution is not possible due to prefetch buffer busy (BUSY). At the time of the prefetch buffer BUSY, the central processing unit 100 selects another I / O device path and issues the I / O instruction 1. Channel control circuit 301
Is the display flag 30 when the input / output instruction 1 can be executed.
5 is set to the channel device number and the busy bit “1”, and the used area of the prefetch data buffer 302 necessary for executing the input / output instruction 1 is secured. Then, the start of transfer is notified to the channel device designated by the input / output command 1 via the signal line 0. Notified channel devices 400 to 40
4 is in a state of waiting for input / output data. Further, the channel control circuit 301 supplies the transfer control information 8 to the data transfer control circuit 304 to start the memory access. The data transfer control circuit 304 having received the transfer control information 8 sends a request transmission signal 14 to the prefetch data buffer control circuit 303 each time the transmission of the memory request 3 is started and the transmission of the memory request 3 is performed once. The request signal 14 is continuously transmitted until the buffer control circuit 303 outputs the request suppression signal 13. The prefetch data buffer control circuit 303 refers to the display signal 10 of the display flag 305, and when the used area of the prefetch data buffer 302 allocated to the channel device 400 being transferred becomes full, sends a request suppression signal to the data transfer control circuit 304. 13 is output.

Also, a plurality of channel devices 400 to 404
In this case, the memory request 3 of each channel device is transmitted in accordance with the use area of the prefetch data buffer 302 allocated to each channel device. When the memory reply 4 arrives, the data input register 306 stores the memory reply data 5 in the prefetch data buffer 302 at the address specified by the prefetch data buffer control circuit 303. Prefetch data buffer 3
02 outputs the memory reply data 5 at the address designated by the prefetch data buffer control circuit 303 to the data output register 307 as data 6. The data output register 307 sends the transfer data 7 to the channel device designated by the number 11 by the prefetch data buffer control circuit 303 when the data 6 is received, and sends the data transmission signal 12 to the prefetch data buffer control circuit 303 when the transmission is completed. To notify completion of data output. The prefetch data buffer control circuit 303 includes a data output register 307
When the data early signal 12 comes from the server, the request suppression signal 1
3 is stopped, and the transmission of the memory request 3 is permitted to the data transfer control circuit 304. The above operation is repeated until the transfer amount specified by the input / output instruction 1 is completed. When the data transfer is completed, the channel control circuit 301
Then, an end report 2 of the input / output instruction 1 is output to 00, and the operation of the channel control device 300 ends.

FIG. 2 shows a prefetch data buffer 3 according to this embodiment.
FIG. 12 is a diagram showing the relationship between the display flag of the prefetch data buffer 302 and the display flag of the prefetch data buffer 302. FIG. It comprises a device number of the channel device being used and a busy bit indicating whether or not the channel device is in use. When the busy bit is "0", the corresponding prefetch data buffer 30
This indicates that the unit area No. 2 is unused. The channel control circuit 301 determines the required number of unit areas of the prefetch data buffer 302 from the number of words of prefetch data required for execution of the input / output instruction 1, and determines the device number of the channel device to be used prior to the transfer operation and the busy bit. Is set. When the transfer operation is completed, the busy bit is immediately reset.

[0015]

As described above, according to the present invention, the prefetch data buffers of a plurality of channel devices to which input / output devices having different transfer capacities are connected are shared, and the input / output devices corresponding to the transfer capacities of the input / output devices performing the transfer operation are used. By making the usage amount of the prefetch data buffer variable, the prefetch data buffer can be used efficiently. Further, since an input / output device having a high transfer performance and an input / output device having a low transfer performance can be freely connected, there is an effect that a prefetch data buffer is not wasted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the present embodiment.

[Explanation of symbols]

 Reference Signs List 100 central processing unit 200 main storage device 300 channel control device 301 channel control circuit 302 prefetch data buffer 303 prefetch data buffer control circuit 304 data transfer control circuit 305 display flag 306 data input register 307 data output register 400, 401... 403 channel device 500 , 501 ... 503 I / O device

Claims (1)

(57) [Claims] 1. A channel control device connected to a main storage device and a central processing unit for controlling a plurality of channel devices and performing data transfer between the main storage device and an input / output device connected to the channel device. A shared prefetch data buffer for temporarily storing data to be transferred to the plurality of channel devices, and first means for receiving transfer performance of the channel device or the input / output device for each data transfer from the central processing unit; A second means for managing a use state of the prefetch data buffer and securing a use area of the prefetch data buffer according to the transfer performance; and performing a memory access according to the use area of the prefetch data buffer to execute the main storage. A data transfer method, comprising: third means for controlling data transfer between a device and the input / output device.