JP2826780B2 - Data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method,
The present invention relates to a data transfer method including a channel control device for transmitting and receiving data to and from a main storage device connected to a central processing unit and an input / output device connected to a channel device.

[0002]

2. Description of the Related Art In a conventional data transfer method, when transferring data from a connected central processing unit and main storage device to an input / output device via a channel device, a channel control device is connected under one channel device. Since a fixed-size prefetch data buffer is provided inside the channel device according to the transfer performance of the input / output device to be connected, different channel devices are configured according to the transfer performance of the input / output device connected under the channel device.

[0003]

Since the channel control device in the above-mentioned conventional data transfer method has a prefetch data buffer of a fixed size inside one channel device, an input / output device connected under the channel device is used. There is a problem that a high-performance channel device must be provided every time the transfer performance of the device increases. Also, if I / O devices with different transfer performances are connected under the channel device, a prefetch data buffer necessary for transfer of high-performance I / O devices is prepared, so it is connected to I / O devices with low transfer performance. There is a problem that the prefetched data buffer is wasted. Further, in recent years, the speed of the input / output devices has been further increased, and a combination of an input / output device having a high transfer performance and a low input / output device cannot be avoided. Therefore, there is a problem that the waste of the prefetch data buffer is increased.

[0004]

According to a data transfer method of the present invention, an input / output device is connected to a main storage device and a central processing unit, controls a plurality of channel devices, and is connected to the main storage device and the channel devices. In a channel control device that performs data transfer between, a shared prefetch data buffer that temporarily stores data to be transferred to the plurality of channel devices,
First means for receiving and storing the transfer performance of the input / output device connected thereto from the central processing unit at the time of initial setting; and transfer performance of the input / output device which manages and stores the use status of the prefetch data buffer Second means for allocating a use area of the prefetch data buffer according to the data, and performing a memory access according to the use area of the reserved prefetch data buffer to perform data access between the main storage device and the input / output device. And third means for performing transfer control.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
The case where four 0 to 404 are connected is shown.

In FIG. 1, a central processing unit 100 is a device for performing arithmetic processing, issues an input / output instruction 1 to a channel control device 300 when performing data input / output processing, and At the time of initial setting of 300, transfer performance information 17 of all input / output devices connected under the control of the channel control device 300 is given.

[0008] The main storage device 200 has a central processing unit 100.
Is a storage device that is connected to the channel control device 300 and reads or writes data of the input / output devices 500 to 501 required by the central processing unit 100 via the channel devices 400 to 404. A one-word memory reply 4 is transmitted in response to one memory request 3 issued from 300.

[0009] The channel control device 300 responds to the input / output instruction 1 issued by the central processing unit 100 by the channel device 40.
Controlling the main storage device 200 and the input / output device 5
It is a device that performs data transfer between 00 and 501.

The channel devices 400, 401,... 403
Is a device that controls an interface with the input / output devices 500, 501,... 503, and transfers the transfer output data 7 received from the channel control device 300 to the input / output devices 500 to 504.

The channel control circuit 301 is a circuit that decodes and processes the input / output command 1 received from the central processing unit 100.
Is read from the I / O device transfer performance table 308, a prefetch data buffer area corresponding to the transfer performance of the I / O devices 500 to 504 is secured, and the data transfer control circuit 304 This is a circuit for giving data transfer instructions to the channel devices 400 to 404.

A prefetch data buffer 302 is a buffer for storing transfer data read from the main storage device 200 prior to data transfer, and a buffer for writing and reading data to and from an address designated by a prefetch data buffer control circuit 303. It is.

The prefetch data buffer control circuit 303
In accordance with the available area of the prefetch data buffer 302 allocated to the input / output devices 501 to 505 for transferring with reference to the prefetch data buffer management flag group 305,
This circuit generates the write address 16 and the read address 15 and controls the data transfer control circuit 304 to limit the number of memory accesses to control the amount of data in the prefetch data buffer 302.
When the used area of the prefetch data buffer 302 allocated to No. 4 becomes full, a request suppression signal 13 is output,
Also, the channel device number of the memory request is stored in the order in which the memory request was made, and the write address 16 of the prefetch data buffer 302 is output every time the data input register 306 receives the memory reply 4,
When the memory reply data is output to the channel devices 400 to 404, the read address 15 of the prefetch data buffer 302 and the channel device number 11 to be transferred are transmitted.

The data transfer control device 304 responds to the data transfer instruction 8 of the channel control circuit 301 by the main storage device 20.
0, and a request suppression signal 13 for each channel from the prefetch data buffer control circuit 303.
The memory request 3 for each of the channel devices 400 to 404 is continuously transmitted until the data request is output. Each time the memory request 3 is transmitted once, the request transmission signal 14 for each of the channel devices 400 to 404 is prefetched.
Send to 03.

The flag group 305 has one flag per unit area of the prefetch data buffer 302, and is composed of a channel device number and a busy bit. The corresponding unit area of the prefetch data buffer 302 is the channel control device 300. When the channel devices 400 to 404 connected to are used for data transfer, the channel devices 400 to 40
No. 4 and a busy bit “1” are set, and when not in use, the busy bit “0” is set. The channel control circuit 301 sets / resets the use status of the prefetch data buffer 302. Is always displayed.

The data input register 306 is a register for receiving the memory reply 4 from the main storage device 200 and writing it into the prefetch data buffer 302. The data output register 307 outputs the data read from the prefetch data buffer 302 to the prefetch data buffer control circuit 3.
This is a register for sending to the channel devices 400 to 404 specified by the channel device number 11 output from the channel device 03. The input / output device transfer performance table 308 stores the transfer performance of all the input / output devices 500 to 504 connected to the channel control device 300 given from the central processing unit 100 when the channel control device 300 is initialized. Memory.

Next, the operation of this embodiment will be described.
The central processing unit 100 issues an I / O command 1 to the channel control device 300, and the channel control device 300 decodes the I / O command 1 by the channel control circuit 301 and transfers data of the I / O devices 500 to 504 that perform data transfer. Is checked to determine whether the I / O instruction 1 can be executed based on the use status of the prefetch data buffer 302 with reference to the prefetch data buffer management flag group 305. Prefetch data buffer 30
If the used area is not enough, it notifies the central processing unit 100 that execution is impossible due to prefetch buffer busy (BUSY).

The central processing unit 100 includes a prefetch buffer B
At the time of USY, another I / O controller path is selected and the I / O instruction 1 is issued. If the input / output instruction 1 can be executed, the channel device number and the in-use bit “1” are set in the prefetch data buffer management flag group 305, and the prefetch data buffer 302 and the used area necessary for executing the input / output instruction 1 are set. To secure. Then, the start of data transfer is notified via the signal line 9 to the channel devices 400 to 404 to which the input / output devices 500 to 504 specified by the input / output command 1 are connected. Notified channel devices 400 to 40
4 is in a state of waiting for input / output data. Further, the channel control circuit 301 gives the transfer control information 8 to the data transfer control circuit 304 to start the memory access. The data transfer control circuit 304, which has received the transfer control information 8, sends a request sending signal 14 to the prefetch data buffer control circuit 303 each time a memory request 3 is started and one memory request is made, and the prefetch data buffer control is performed. The transmission of the memory request 3 is continued until the request suppression signal 13 is output from the circuit 303.

The prefetch data buffer control circuit 303
When the memory request of the input / output devices 500 to 504 during transfer with reference to the prefetch data buffer management flag group 305 becomes full when the use area of the prefetch data buffer 302 allocated to the input / output devices 500 to 504 during transfer is full. A request suppression signal 13 is output to the data transfer control circuit 304. In addition, a plurality of channel devices 400 to
In the case where the transfer operations are simultaneously performed by the channel devices 404, each of the channel devices 4 according to the use area of the prefetch data buffer 302 allocated to each of the channel devices 400 to 404.
A memory request 3 of 00 to 404 is transmitted.

When the memory reply 4 arrives, the data input register 306 stores the memory reply data 5 in the prefetch data buffer 302 at the address specified by the prefetch data buffer control circuit 303. The prefetch data buffer 302 outputs the memory reply data 5 at the address specified by the prefetch data buffer control circuit 303 as data 6 to the data output register 307. When the data output register 307 receives the data 6, the data output register 307 determines the channel device 400 designated by the prefetch data buffer control circuit 303.
404. When the transmission is completed, the data transmission signal 12 is sent to the prefetch data buffer control circuit 303 to notify the completion of the data output.

The prefetch data buffer control circuit 303
When the data transmission signal 12 comes from the data output register 307, the request suppression signal 13 is stopped, and the transmission of the memory request 3 is permitted to the data transfer control circuit 304. The above operation is repeated until the transfer amount specified by the input / output instruction 1 is completed. When the data transfer is completed, the channel control circuit 301 outputs the end report 2 of the input / output instruction 1 to the central processing unit 100. Then, the operation of the channel control device 300 ends.

FIG. 2 shows the prefetch data buffer 302 of FIG.
FIG. 9 is a diagram showing the relationship between a prefetch data buffer management flag group 305 and one prefetch data buffer management flag per unit area of the prefetch data buffer 302; It is composed of the channel device numbers of the channel devices 400 to 404 using the unit area of the buffer 302 and a busy bit indicating whether or not the channel device is busy. When the busy bit is “0”, the corresponding prefetching is performed. Data buffer 3
02 indicates that the unit area is unused. The channel control circuit 301 calculates a prefetch data buffer 302 based on the number of words of prefetch data necessary for executing the input / output instruction 1.
The required number of unit areas is determined, and the channel device numbers and busy bits of the channel devices 400 to 401 to be used are set prior to the data transfer operation. When the data transfer operation is completed, the busy bit is immediately reset.

[0023]

As described above, according to the present invention, the prefetch data buffers of a plurality of channel devices to which input / output devices having different transfer capacities are connected are shared, and the input / output devices corresponding to the transfer capacities of the input / output devices which perform the transfer operation. By making the usage amount of the prefetch data buffer variable, the prefetch data buffer can be used efficiently. Further, since an input / output device having a high transfer performance and an input / output device having a low transfer performance can be freely connected, there is an effect that a prefetch data buffer is not wasted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the present embodiment.

[Description of Signs] 100 Central processing unit 200 Main storage device 300 Channel control device 301 Channel control circuit 302 Prefetch data buffer 303 Prefetch data buffer control circuit 304 Data transfer control circuit 305 Display flag 306 Data input register 307 Data output register 308 Input / output Device transfer performance table 400, 401,... 404 Channel device 500, 501,.

Claims (1)

(57) [Claims] 1. A channel control device connected to a main storage device and a central processing unit for controlling a plurality of channel devices and performing data transfer between the main storage device and an input / output device connected to the channel device. A shared prefetch data buffer for temporarily storing data to be transferred to the plurality of channel devices, and first means for receiving and storing transfer performance of the input / output device connected thereto from the central processing unit at the time of initialization. Second means for managing a use area of the prefetch data buffer according to the transfer performance of the input / output device which manages and stores the use status of the prefetch data buffer; and Third means for performing a memory access in accordance with the data and controlling data transfer between the main storage device and the input / output device. Data transfer method.