JPH05204830A - Input/output controller - Google Patents

Abstract

PURPOSE:To control an input/output device without following any complicate procedure over a DMA channel when DMA transfer is performed by using an input/output bus controller. CONSTITUTION:A signal line 105 for controlling the input/output bus controller 101 and input/output devices 102, 103, and 104 is added to a single-input/output- bus system including a main memory 106. The input/output bus controller 101 receives an address or transfer-destination input/output device number, sent through an address bus, by an address register, sends it to a decoding circuit, and sends addresses decoded by the decoding circuit as individual select signals to the input/output devices 102, 103, and 104, connected to an input/output bus 107, through a signal line 105 one to one when determining a device as an input/output object prior to the transfer of data. When the DMA transfer is performed, the input/output devices in the computer system uses the individual select signals to perform control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device,
In particular, the present invention relates to an input / output control device for selectively controlling input / output control when controlling an input / output data bus in a computer system.

[0002]

2. Description of the Related Art Although there are many conventional input / output control devices in a computer system, a system using a single input / output bus is mainly used in small and medium computer systems.

The single input / output bus system is, as shown in FIG. 3, a central processing unit (CPU) 301 and a main memory 30.
2 and input / output devices 303 and 304 are connected via an input / output data bus 305 to perform data transfer between these devices.

The data transfer procedure is as follows. First, the CPU 301 sends a fixed address to the input / output devices 303 and 304, and selects the above-mentioned input / output devices 303 and 304 by the address. As a result, the above-mentioned CPU 301 and the above-mentioned input / output devices 303, 3
It is to exchange with 04.

When the input / output devices 303 and 304 can handle a large amount of data, such as a magnetic disk, the above procedure is inefficient. Therefore, there is a DMA channel system.

In the DMA channel system, the CPU does not directly transfer data between the main memory and the input / output device, but the CPU sends only the information necessary for the data transfer to the input / output device. In response to this, the input / output device performs data transfer by itself. That is, the address is issued to the main memory to transfer the data. At this time, the address update and the management of the number of data transfer words are all performed by the input / output device side.

In a simple control system for a single input / output bus, a series of addresses are attached to these CPU, main memory, respective registers of the input / output device, memories, etc., so that the input / output control can be easily performed. It is a typical structure. Therefore, in recent computer systems, there is a tendency that a huge capacity is required for the main memory, and when an address is attached, the address may be unnecessarily used within a certain number of bits.

Therefore, an I / O device number is further added to each I / O device on the series of addresses, and thereby a desired device among a plurality of devices connected to a single I / O bus is designated and selected. Is done.

Now, consider general data block transfer and command block transfer in channel transfer of an input / output device. Normally, in block transfer, two transfer destination input / output device numbers in data transfer are required. That is, in the block transfer, when the command from the CPU for instructing a series of data transfer is completed, another subsequent command is read out again by the DMA channel and the block transfer is continued.

Therefore, the DM which has received the block transfer designation
The A channel stores the input / output device number of the data transfer destination and the transfer destination input / output device number for command reading,
It is necessary to properly use the two device numbers depending on the type of data required.

[0011]

In the conventional computer system, the above-mentioned DMA is used when the input / output device is controlled.
There is a problem that a complicated procedure such as storing two transfer destination input / output device numbers in the channel and selectively using them is performed in the DMA channel.

An object of the present invention is to provide an input / output device which solves the above problems and eliminates the need for complicated procedures.

[0013]

The structure of the present invention is a CP
In an input / output control device in which a plurality of devices such as U, main memory, and input / output device are connected to the input / output bus as input / output devices, address bus and input / output for device selection connected to the above-mentioned input / output bus For the bus, monitor the signal line for uniquely determining the device to be driven and the output state of the signal line so that the device to be driven is uniquely selected by the output from the signal line. A controller is provided, and the device to be driven is selected according to the output state of the signal line when performing the DMA transfer.

[0014]

1 is a block diagram of an input / output control device according to an embodiment of the present invention.
Shown in.

In FIG. 1, in this embodiment, a signal line 105 for controlling the input / output bus control device 101 and the input / output devices 102, 103, 104 is used in a single input / output bus system including a main memory 106. It was added.

In FIG. 2, the input / output bus controller 10 is shown.
In determining the device to be input / output performed prior to the data transfer, 1 receives the address on the address bus 201 or the transfer destination input / output device number in the address register 202 and sends it to the decoding circuit 203. , The address decoded here is the individual selection signal 2
As 04, it is sent to each device connected to the input / output bus on a one-to-one basis.

When performing the DMA transfer, the input / output device in the computer system is controlled by using the individual selection signal.

Next, an input / output control device of another embodiment of the present invention will be shown. This embodiment is based on the content of the one embodiment described above.
An individual selection signal line is connected to the CPU instead of the input / output device. That is, in the present system, the CPU is also regarded as one device connected to the input / output bus, and is connected so that the individual selection signal can be received.

[0019]

As described above, according to the present invention, when controlling the input / output device, the complicated procedure of storing or selectively using the two transfer destination input / output device numbers in the DMA transfer described above is performed. This has the effect of eliminating the need for the DMA channel.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first portion of an input / output control device of an embodiment of the present invention.

FIG. 2 is a block diagram showing a second part of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a conventional input / output control device.

[Explanation of symbols]

 101 input / output bus control device 102-104, 303, 304 input / output device 105, 204 individual selection signal line 106, 302 main memory 107, 201, 305 address bus 202 address register 203 decoding circuit 301 CPU

Claims (1)

[Claims] 1. An input / output control device in which a central processing unit, a main memory, and a plurality of input / output devices are connected to the input / output bus as input / output devices, respectively. A signal line for uniquely determining a device to be driven for the address bus and the input / output bus, and the device to be driven is uniquely selected by an output from the signal line. A controller for monitoring the output state of the signal line,
An input / output control device, wherein the driven device is selected in accordance with an output state of the signal line when data is transferred.