JP2000132498A - Dma transfer controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA(direct memory access) transfer controller which can improve the performance of the whole system by decreasing the occupancy ratio of a system bus and an I/O bus. SOLUTION: When DMA transfer becomes necessary, a CPU 1 sets information needed for the DMA transfer in peripheral input/output controllers 4 to 6 as objects of the DMA transfer and DMA control circuits 11, 12. Then the DMA control circuit 12 divides data to be transferred by the number of buffer memories 16 to 18 and outputs the start address of the divided data to respective buffer memory control circuits 13 to 15. The DMA control circuit 12 performs the burst transfer of the data of the peripheral input/output controllers 4 to 6 to the buffer memories 16 to 18. The DMA control circuit 11 restores the divided data according to the start addresses in the buffer memories 16 to 18 and outputs them to a system bus 100 when the data are stored in the buffer memories 16 to 18 by a certain quantity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer controller, and more particularly to a DMA (Direct Memory Access) between a main memory and a peripheral input / output controller.
s) The present invention relates to a DMA transfer control device for controlling transfer.

[0002]

2. Description of the Related Art Conventionally, an information processing apparatus generally has a CPU (central processing unit), a main memory (main memory), a system bus, an I / O bus, and the like. DMA transfer is used for reading and writing data between the memory and the peripheral input / output control device.

In this DMA transfer, if the data width of the system bus to which the main memory is connected is different from the data width of the device controller, the I / O (input / output) bus to which the device controller is connected and the system bus are different. A buffer is provided in between, and the data bus width is matched by the buffer. Here, the device controller has a plurality of data widths, such as 8 bits, 16 bits, and 32 bits, and does not always match the data width of the system bus.

As a method for increasing the speed of the DMA transfer, there is a method disclosed in Japanese Patent Application Laid-Open No. 04-052948. The data transfer system according to this method is shown in FIG.
As shown in FIG. 5, a buffer memory control circuit 21 for controlling a buffer memory 23, a main processor 22 for controlling a data transfer state, a first input / output control circuit 24 for controlling a first input / output device 26, Second input / output device 27
, A CPU (Central Processing Unit) 28 in the information processing apparatus, and a main memory (main memory) 29.

When one of the first input / output device 26 and the second input / output device 27 is performing DMA transfer with the main memory 29 via the high-speed DMA bus 201, the first
If there is a request to transfer data from the other one of the input / output device 26 and the second input / output device 27 to the main memory 29, the data is stored in the buffer memory 23.

When a notification of the end of the DMA transfer is received from the first input / output control circuit 24, the data stored in the buffer memory 23 is DMA-transferred to the main memory 29 via the high-speed DMA bus 201. The data transfer path in the buffer memory control circuit 21 is switched and controlled, and a DMA using the high-speed DMA bus 201 is connected between each of the first input / output device 26 and the second input / output device 27 and the main memory 29. Perform a transfer.

[0007]

In the above-mentioned conventional information processing apparatus, at the time of writing to the device controller, data from the main memory is written to the buffer until the data stored in the buffer is written to the device controller. There is a problem that can not be included.

In this information processing apparatus, at the time of reading from the device controller, the data is resident in the buffer until the data matches the data width of the system bus, and when the data width matches, the data in the buffer is written to the main memory. The data transfer from the device controller cannot be accepted until the data in the buffer is written into the main memory. Therefore, there is a problem that the DMA transfer depends on the data transfer capability of the device controller.

On the other hand, in the DMA transfer system described in the publication, one input / output control circuit
During the A transfer, the other input / output control circuit stores data in the buffer memory.

In this DMA transfer system, when the data transfer of the input / output control circuit that has been performing the DMA transfer between the main memories is completed, the efficiency of the DMA transfer is improved by switching the data transfer path. However, there is a problem that speeding up in unidirectional data transfer is not performed.

Therefore, an object of the present invention is to solve the above-mentioned problems, to reduce the occupancy of the system bus and the I / O bus, and to improve the performance of the entire system. To provide.

[0012]

SUMMARY OF THE INVENTION A DMA transfer control device according to the present invention is a DMA transfer control device for controlling direct memory access transfer between a main memory and a peripheral input / output control device. A plurality of buffer memories for accumulating the data, a storage control means for dividing the data at the time of the direct memory access transfer and storing the divided data in each of the plurality of buffer memories, Transmission control means for restoring data and transmitting the data to a transfer destination.

First, the DMA transfer control device according to the present invention has a high-speed and high-speed operation by providing a plurality of stages of buffer memories for storing data during DMA transfer between the main memory and the peripheral input / output control device. Data can be transferred efficiently.

More specifically, in the DMA transfer control device according to the present invention, the D transfer between the main memory and the peripheral input / output control device is performed.
In the MA transfer, after a certain amount of data received from the peripheral input / output control device is accumulated in a buffer memory, the data is sequentially read out to a main memory, so that the system bus and the I / O bus can be used efficiently.

As described above, in the DMA transfer control device of the present invention, a buffer memory and a buffer memory control circuit are provided in a plurality of stages to temporarily store data on the system bus, and the system bus and the peripheral device controller. And a burst transfer in accordance with the data bus width.

Therefore, D in only one buffer memory
The occupancy of the system bus and the I / O bus can be reduced as compared with the MA transfer, and the performance of the entire system can be improved by effectively utilizing the reduced time.

[0017]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a DMA transfer control device according to one embodiment of the present invention.
In the figure, a DMA transfer control device 1 includes a system bus 10
0, a CPU (Central Processing Unit) 2 and a main memory 3, and an I / O (input / output) bus 101.
Are connected to the peripheral input / output control devices 4 to 6.
Further, the DMA transfer control device 1 includes the DMA control circuits 11, 1
2, buffer memory control circuits 13 to 15, and buffer memories 16 to 18.

The DMA transfer control circuits 11 and 12 control the DMA transfer, and the buffer memory control circuits 13 to 15 control the buffer memories 16 to 18. The buffer memories 16 to 18 temporarily store data for transferring data on the I / O bus 101 to the data bus of the system bus 100, and are constituted by nonvolatile memories.

FIG. 2 is a flowchart showing the processing operation of the DMA transfer control device 1 of FIG. These FIGS. 1 and 2
The processing operation of the DMA transfer control device 1 according to one embodiment of the present invention will be described with reference to FIG.

When the DMA transfer is required (step S1 in FIG. 2), the CPU 1 sends the DMAs of the peripheral input / output control devices 4 to 6 and the DMA transfer control device 1 to be subjected to the DMA transfer.
The information necessary for DMA transfer is set for the control circuits 11 and 12.

In the case of DMA transfer of device read / memory write, a DMA transfer start address and transfer length information are set by the CPU 1 in the DMA control circuits 11 and 12 (step S2 in FIG. 2). Addresses and data from the CPU 1 are transmitted to the peripheral input / output control devices 4 to 6 by the system bus 100.
From the I / O bus 1 through the DMA control circuits 11 and 12
01, and information necessary for DMA transfer is set in the peripheral input / output control device connected to the I / O bus 101.

As described above, the peripheral input / output control devices 4 to 6
When the DMA transfer setting is completed, the peripheral input / output control devices 4 to 6 output a device data request signal to the DMA control circuit 12.

After the above setting is completed, the DMA control circuit 12 divides the data to be transferred by the number of buffer memories 16 to 18 (step S3 in FIG. 2) and sends the start address of the divided data to each of the buffer memory control circuits 13 to 15. Output (Step S4 in FIG. 2).

In this case, the buffer memory control circuit 13 receives the start address of data # 1, the buffer memory control circuit 14 receives the start address of data # 2, and the buffer memory control circuit 15 receives the start address of data # 3. Each is output.

When a device data request is issued (step S5 in FIG. 2), the DMA control circuit 12 transfers the data of the peripheral input / output control devices 4 to 6 which issued the device data request to the buffer memory control circuits 13 to 15. Then, burst transfer is performed to each of the buffer memories 16 to 18 (step S6 in FIG. 2).

The DMA control circuit 12 controls each buffer memory 1
When a certain amount of data is accumulated in 6 to 18 (step S7 in FIG. 2), the data is transferred from each of the buffer memories 16 to 18 to the DMA control circuit 11. The DMA control circuit 11 restores the divided data by using each start address of each of the buffer memories 16 to 18, and
(Step S8 in FIG. 2). The above processing is executed until the DMA transfer from the peripheral input / output control devices 4 to 6 is completed (steps S6 to S9 in FIG. 2).

On the other hand, D of memory read / device write
In the case of the MA transfer, the DMA transfer controller 1 divides the data from the main memory 3 by the number of buffer memories 16 to 18 and restores the divided data to output to the I / O bus 101. Device lead
The same control as in the case of the DMA transfer of the memory write is performed. Therefore, this memory read / device write DM
Illustration of the A transfer processing operation is omitted.

Therefore, after the transfer source peripheral input / output control devices 4 to 6 and the DMA control circuits 11 and 12 are set, the DM
The A control circuits 11 and 12 transfer data sent from the system bus 100 to the I / O bus 101 in response to data transfer request signals from the peripheral input / output control devices 4 to 6, and 6 will be written.

As described above, during DMA transfer between the main memory 3 and the peripheral input / output control devices 4 to 6, the buffer memories 16 to 18 for accumulating data are provided in a plurality of stages, and the peripheral input / output control devices After a certain amount of data received from the main memory 3 or the peripheral input / output control device 4 is stored in the buffer memories 16 to 18,
6, the system bus 100 and the I / O bus 101 can be used efficiently.

Therefore, D in only one buffer memory
System bus 100 or I / O bus 10 rather than MA transfer
1 can be reduced, and by utilizing the reduced time effectively, the performance of the entire system can be improved.

[0031]

As described above, according to the present invention, in a DMA transfer control device for controlling direct memory access transfer between a main memory and a peripheral input / output control device, data of direct memory access transfer is accumulated. The data of the direct memory access transfer is divided and stored in each of the plurality of buffer memories, and the data divided and stored in each of the plurality of buffer memories is restored and transmitted to the transfer destination. There is an effect that the occupancy of the O bus can be reduced and the performance of the entire system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a DMA transfer control device according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing operation of the DMA transfer control device of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a data transfer system according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 DMA transfer control device 2 CPU 3 Main memory 4-6 Peripheral I / O control device 11, 12 DMA control circuit 13-15 Buffer memory control circuit 16-18 Buffer memory 100 System bus 101 I / O bus

Claims (4)

[Claims] 1. A DMA transfer control device for controlling a direct memory access transfer between a main memory and a peripheral input / output control device, comprising: a plurality of buffer memories for storing data of the direct memory access transfer; Storage control means for dividing the data at the time of memory access transfer and storing the data in each of the plurality of buffer memories, and transmission control means for restoring the data divided and stored in each of the plurality of buffer memories and transmitting the data to the transfer destination A DMA transfer control device comprising: 2. The transmission control means according to claim 1, wherein said transmission control means is configured to sequentially read and transmit the data to said transfer destination when said data is accumulated in a predetermined fixed amount in said buffer memory. DMA transfer control device. 3. A plurality of buffer memory control circuits provided corresponding to each of said plurality of buffer memories and controlling accumulation of said data in said buffer memories. 2. The DMA transfer control device according to claim 1. 4. The DMA transfer control device according to claim 1, wherein said storage control means is configured to perform burst transfer of said data to each of said plurality of buffer memories.