JP2533886B2 - Data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a control method for controlling data transfer by providing a buffer between two data transfer paths having different transfer rates in a data processing device. In order to efficiently perform data transfer between two different interfaces, a first interface and a second interface having a different data transfer rate from the first interface via a data buffer that temporarily stores transfer data. In the data transfer circuit in the data processing device for performing data transfer with the interface, a means for storing control information for instructing the second interface to continue or stop the data transfer for each arbitrary unit,
A means for continuing or stopping the transfer operation according to the control information is provided, and the control information is updated corresponding to the content of the pointer indicating the address of the data buffer updated by the first interface within a fixed time. Configure.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control when data is transferred between two interfaces having different transfer rates via a buffer, and particularly to a control method when the transfer process is performed by firmware.

[Prior Art] When data is transferred between two types of interfaces having different transfer speeds and methods, a data buffer for transfer is generally provided, and the data transfer is realized via this buffer.

In this case, there are a method to control the buffer entirely by hardware, and a method to intervene the firmware as a part of the control.In addition, as a usage method of the data buffer, there are FiFO method and firmware control suitable for hardware control. There is a suitable ALTERNATE method.

Among these methods, the FiFO method is for performing speed conversion by outputting data input from one of a plurality of memories tangentially connected in a pipeline, from the other at a speed different from this, and In the alternate system, two buffer memories are used, and these buffer memories are alternately used to perform speed conversion between both interfaces.

[Problems to be Solved by the Invention] Among the above-mentioned conventional data transfer methods, the former one, which uses a FiFO method that is controlled only by hardware, has a high conversion speed, but the device is expensive, and the latter firmware is used. However, there is a problem in that the conversion efficiency is not good in the case of controlling by the alternate method though it is economical.

The present invention has been made in view of such conventional problems, and an object thereof is to provide a data transfer method by firmware control which is economical and has high data conversion efficiency.

[Means for Solving the Problems] According to the present invention, the above-mentioned object is achieved by the means described in the claims. That is, the present invention is
Through the data buffer that temporarily stores the transfer data,
In a data transfer circuit in a data processing device for performing data transfer between a first interface and a second interface having a different data transfer rate from the first interface, a second interface is provided for each unit. A means for storing control information for instructing to continue or stop data transfer and a means for continuing or stopping the transfer operation according to the control information are provided, and the first buffer updates the data buffer of the first interface within a fixed time. This is a data transfer method in which control information for controlling data transfer of the second interface is updated corresponding to the content of the pointer indicating the address.

[Operation] According to the present invention, the data buffer for transfer has a fixed size for the low speed interface of the two types of interfaces having different transfer rates for transferring data through the buffer. Instead of using the buffer memory for alternation, the buffer size used for data transfer by the low speed side interface is updated in response to the transfer operation of the high speed side interface, thereby performing the data transfer operation between two types of interfaces with different speeds. The transfer efficiency is improved by efficiently proceeding simultaneously.

[Embodiment] FIG. 1 is a block diagram of an embodiment of the present invention.
Is a channel, 2 is a channel adapter (abbreviated as CA in the figure), 3 is a CCU, 4 is a data transfer control unit, 5
Is a counter, 6 is a +1 circuit, 7 is a control storage (abbreviated as CS in the figure), 8 is firmware, 9 is a control table, 10 is a data buffer, 11 is an instruction execution unit, 12 is a bus control unit, 13 is a counter,
Reference numeral 14 is a +1 circuit, 15 to 18 are registers, and 19 is a bus control unit.

In the figure, a register 15 is a bus out register (in the figure, is abbreviated as BOR), a register 16 is a bus register (in the figure is abbreviated as and BIR), and a register 17 is a tag out register ( The register 18 is a tag-in register (abbreviated to TIR in the figure), and the counter 5 is a data buffer address 1 counter (abbreviated in the figure). The counter 13 is a data buffer address 2 counter (abbreviated in the figure as DBA2).

FIG. 2 is a flow chart showing the control relating to the data transfer of the above embodiment.

Data transfer from a central control unit (hereinafter referred to as CCU) to a channel control adapter (hereinafter referred to as CA) to a host (channel) will be described below as an embodiment of the present invention with reference to the drawings.

On the control memory (CS) 7, in addition to the firmware 8, a data buffer 10 for temporarily storing transfer data, and
A stop bit (STOP Bi) for accessing the data transfer control block to continue or stop the transfer function on the channel side.
There is a control table 9 for setting T). There is one stop bit for each data buffer byte.

Firmware 8, First, the transfer function on the CCU side (CCU → C
Start A). A stop bit for the number of bytes to be transferred next is set on the control table 9.
Next, the counter 13 (DBA2) in the bus control unit 12 is read.
The DBA2 advances the start address value of the data buffer for starting the transfer by the transfer function on the CCU side by the number of bytes transferred. The firmware 8 sets the stop bit for DBA2 on the control table 9 and activates the transfer function (CA → channel) on the channel side in the data transfer control unit 4. Next, the firmware 8 checks whether or not the transfer on the CCU side is being performed. If the transfer is in progress, the DBA2 is read again, the stop bit for the newly read DBA2 is set on the control table 9, and the stop bit read by DB2 before is reset. If it is not transferring, it only resets the stop bit for DBA2 read previously. If the CCU side is not transferring, the data for the number of bytes instructed by the CCU side has already been stored in the CS7 data buffer 10.
It will only reset the stop bit for the DBA2 read before and will transfer up to the stop bit for the indicated byte count. Whether or not the CCU side is transferring data is set at the start of data transfer by the firmware 8 having a flag. When the bus control unit 12 completes the transfer of the instructed byte count, an interrupt of a higher level than that under the transfer control is generated, and the reset is performed by resetting the interrupt and resetting the flag during transfer. . Next, the firmware 8 checks whether the channel side is transferring, and if it is transferring,
Repeat from the check whether the CCU side is transferring.

If not transferring, read the counter (DBA1).
The DBA1 advances the start address value of the data buffer that started the transfer by the number of bytes transferred from the data buffer 10 of CS7 to the channel by the data transfer control unit 4. Now, read DBA2, compare DBA1 and DBA2, and
If A1 = DBA2, it means that the transfer of the designated number of bytes has been completed, so the process proceeds to the process after the transfer is completed. At this point in time, as described above, the "flag indicating whether or not the CCU side is transferring" is reset. If DBA1 <DBA2, the transfer for the designated number of bytes has not been completed, so the transfer on the channel side is restarted, and the process is repeated from the above-mentioned check whether the transfer on the CCU side is being performed.

Since the count of DBA1 is stopped when the stop bit is detected, DBA1 <DBA2 is set except in the transfer end state. And DBA1 = DBA2 only in the transfer end state, DBA1> DB
There is no A2 condition.

Whether or not the channel is being transferred has a flag in the firmware 8 and is set at the start of transfer. When the data transfer control unit detects the stop bit, this flag is reset together with an interrupt reset when an interrupt to a higher level for which transfer control is performed occurs.

 The transfer in the opposite direction is possible by the same method.

[Effects of the Invention] As described above, according to the method of the present invention, by controlling the firmware, the data transfer in the two interfaces having different speeds can be simultaneously progressed in parallel by using the buffer. In addition, there is an advantage that a data transfer method with high efficiency and easy data transfer can be easily expressed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a flow chart showing control relating to data transfer of the embodiment. 1 ... Channel, 2 ... Channel adapter, 3 ... CC
U, 4 ... Data transfer control unit, 5 ... Counter, 6 ...
+1 circuit, 7 ... Control storage, 8 ... Firmware, 9 ... Control table, 10 ... Data buffer, 11 ... Command execution section, 12 ... Bus control section, 13
...... Counter, 14 …… + 1 circuit, 15-18 …… Register,
19 ... Bus control unit

Claims (1)

(57) [Claims] 1. A data processing device for performing data transfer between a first interface and a second interface having a different data transfer rate from a first interface via a data buffer for temporarily storing transfer data. In the data transfer circuit, the means for storing control information for instructing the second interface to continue or stop the transfer of data in arbitrary units, and means for continuing or stopping the transfer operation according to the control information. Data transfer, characterized in that the control information for controlling the second interface is updated according to the content of the pointer indicating the address of the data buffer updated by the first interface within a fixed time. method.