JPH06105922B2 - Communication control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a means for responding to a specification change of a communication control device.

〔Overview〕

The present invention relates to a communication control device in which a line between a line adapter and a host device is set by a line common control unit, by inserting a first-in first-out memory between the line common control unit and the line adapter. This is to make it possible to minimize the change in hardware related to the specification change.

[Conventional technology]

In this type of communication control device, the line common control unit sequentially scans processing requests from a plurality of line adapters, and if there is a processing request, sends transmission data to the corresponding line adapter.
It manages multiple lines by collecting received data, sending line control commands, and reading line status registers.

[Problems to be solved by the invention]

Therefore, when a high-speed line adapter is installed or a large number of line adapters are installed, the line common controller is redesigned each time to increase the processing capacity, or the bit of the bus connecting the line common controller and the line adapter is increased. I needed to make it wider.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a communication control device capable of minimizing changes in hardware.

[Means for solving problems]

The present invention relates to a communication control device comprising a line adapter connected to each of a plurality of communication circuits, and a line common control unit for setting a path between a host device and this line adapter. And a first memory which is a first-in first-out memory inserted in the transmission path between the line adapter and a second memory which is a first-in first-out memory inserted in the reception path between the line common control unit and the line adapter. A memory and control means for controlling the first and second memories are provided, and the control means writes the transmission data of a predetermined plurality of characters as one unit from the line common control unit into the first memory. After that, a means for transferring each character to the line adapter and reception data of a plurality of predetermined characters are accumulated in the second memory, and then the line common control unit Characterized in that it comprises a means for transferring the received data of a predetermined plurality characters as a unit.

[Action]

In the first embodiment, at the time of transmission, a predetermined fixed number of characters of transmission data including transmission control information are continuously transferred from the line common control unit to the transmission FIFO, and each time there is a transmission request from the line adapter. Characters are fetched from the transmission FIFO memory one by one according to the transmission control information and transferred to the line adapter.

Also, at the time of reception, each time there is a reception request from the line adapter, one character is read from the line adapter, is stacked in the receive FIFO memory, and a predetermined number of characters of receive data is stacked in the receive FIFO memory,
The line common control unit is made to continuously receive the reception data and the reception control information.

In the second embodiment, at the time of transmission, a valid display flag for each character is added to the transmission data, and transmission data having a predetermined fixed number of characters is continuously transferred from the line common control unit to the transmission FIFO memory, and the line adapter is used. Each time there is a request for transmission from the transmission FIFO memory, one character is taken out from the transmission FIFO memory and only the effective character is transferred to the line adapter based on the effective display flag.

When receiving, one character is read from the line adapter each time there is a receive request from the line adapter and the receive FIFO
Stack with the valid display flag added to the memory and receive FI
When a predetermined fixed number of characters of received data are stacked in the FO memory, the line common control unit is made to successively and continuously receive the received data.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The apparatus of this embodiment includes a microprocessor (hereinafter, referred to as MP) 6, a buffer memory (hereinafter, referred to as BM) 5 which is a memory for temporarily storing transmission / reception data for each line and storing a micro program, and not shown. Interface control unit (hereinafter referred to as IFC) 4 that controls data transfer between the main memory of the higher-level device and BM5, and FIFO control units 1-1 to 1-8 including a line-compatible transmission FIFO memory and reception FIFO memory , The line adapters 2-1 to 2-8, the line common control unit 3 for controlling transmission / reception between the BM5 and the FIFO control units 1-1 to 1-8 according to the instruction of the MP6, the processor bus 100, and the line common control. Part 3 and FIFO control part 1
A data bus 200 for connecting -1 to 1-8, and a FIFO
The control units 1-1 to 1-8 and the data buses 300-1 to 300-8 connecting the corresponding line adapters are provided. Here, the FIFO control units 1-2 to 1-8 and the line adapters 2-2 to 2-8 have the same functions as the FIFO control unit 1-1 and the line adapter 2-1 respectively.

Next, the operation of the first embodiment device will be described with reference to FIGS. Upon activation from the host device, IFC4 reads the control word from its main memory, decodes it, and transfers data from main memory to BM5 or from BM5 to main memory. MP6 runs the microprogram on BM5,
Receives processing request from IFC4 or line common control unit 3,
Issue a control command to the IFC4 or line common control unit 3. The MP6 also manages the send / receive buffer area for each line provided on the BM5. The line common control unit 3 is activated by a control command from MP6.

For transmission, FI is received after receiving the command to prepare for transmission.
The FO controller 1-1 and the transmitter of the line adapter 2-1 are initialized, the control word set in advance on the BM5 is read and decoded, and the transfer start address and transfer byte of the transmission data are stored in the DMA control register for transmission. Set the number. When the line common control unit 3 detects a transmission request from the FIFO control unit 1-1 during line scanning, it reads 4 bytes from BM5 according to the transmission DMA control register, adds transmission control information as control information to the beginning, and adds 1 byte. 5 bytes each are continuously transferred to the FIFO control section 1-1 via the data bus 200, and the DMA control register and the transfer byte number counter are updated. Similarly, every time there is a transmission request, the FIFO control unit 1 continues for 5 bytes.
Send data to -1 and request processing to MP6 at the end of transmission.

On the other hand, for reception, the command to prepare for reception is MP6.
Received from FIFO controller 1-1 and line adapter 2-
Initialize the receiving unit of 1, request the write start address of the receive buffer on BM5, and set the secured write start address in the receive DMA control register. When the line common control unit 3 detects a reception request from the FIFO control unit 1-1 during a line scan, it reads from the FIFO control unit 1-1 one byte at a time for 5 consecutive bytes, and according to the reception DMA control register and reception control information. Received data is written to BM5 and the DMA control register is updated. Each time there is a reception request from the FIFO control section 1-1, the DMA control register is updated and the reception data is accumulated on the BM5. At the end of reception, the processing request is sent to the MP6.

That is, in the case of transmission, BM is sent from the host device via IFC4.
The transmission data is temporarily stored in 5, and is further transferred from the BM5 to the FIFO control unit 1 by the line common control unit 3. In the case of reception, the data received from the FIFO control unit 1 is temporarily stored in the BM5 by the line common control unit 3 and transferred to the upper main memory by the IFC4.

Next, the FIFO control unit, which is a feature of the present invention, will be described. FIG. 2 is a block diagram of the FIFO control section 1-1, and FIGS. 3 and 4 are format diagrams of transmission control information (hereinafter referred to as TBP) and reception control information (hereinafter referred to as RBP). . This FIFO control unit 1-1 is a transmission FIFO
The memory 11-1, the reception FIFO memory 12-1, the bidirectional driver 13-1, and the TBP read from the transmission FIFO memory 11-1
A register (hereinafter, referred to as TBPR) 16-1 for holding
A register that writes RBP to the receive FIFO memory 12-1 (hereinafter R
It is called BPR. ) 17-1, a status register (hereinafter referred to as FSTR) 14-1 of the FIFO control unit 1-1, and a register (hereinafter referred to as LSTR) 15-1 for reading and holding the status of the line adapter 2-1. And the control circuit 18-1,
An interrupt request line 400-1 to the line common control unit 3, an interrupt request line 500-1 from the line adapter 2-1 and a command writing line 600-instructing the line adapter 2-1 that the last character has been sent. 1 and 1.

The transmission data and TBP from the line common control unit 3 and the reception data and RBP to the line common control unit 3 are respectively transmitted F
The control information other than these is stacked in the IFO memory 11-1 and the reception FIFO memory 12-1, but the line common control unit 3 directly reads the line adapter 2-1 via the bidirectional driver 13-1. Or write.

First, the case of transmission will be described. Line common control unit 3
When a command from the transmission control unit is sent from the FIFO control unit 1-1 to the FIFO control unit 1-1 via the data bus 200, the bidirectional driver 13-1
Is written to the line adapter 2-1 through the line, the line adapter 2-1 is set to the transmission state, the transmission interrupt mask is released by the control circuit (not shown), and the transmission FIFO memory 11-
If the number of remaining bytes of 1 is 5 bytes or more, that is,
If 4 bytes of transmission data and 1 byte of TBP can be written, the transmission character request bit of FSTR14-1 is turned on (logic "1"). The line common control unit 3 scans the FIFO control units 1-1 to 1-8. When the interrupt is detected by the interrupt request line 400-1 by the scan of the FIFO control unit 1-1, the line common control unit 3 causes the FSTR14 Read -1. In this FSTR 14-1, a transmission character request bit from the FIFO control section 1-1 to the line common control section 3, a reception character takeover request bit, and a transmission interrupt for displaying the transmission / reception interrupt from the line adapter 2-1 as they are It consists of a request bit, a reception interrupt request bit, and a peripheral interrupt request bit. The line common control unit 3 reads FSTR14-1 and if the transmission character request bit is ON, TB
5 bytes of continuous transmission of P and transmission data FIFO memory 11
Write to -1. The transmission FIFO memory 11-1 has TBP and TCR.
Transmission data is written in the order of 0, TCR1, ..., TCR3. TBP
When B0 of is on, it indicates that TCR0 is a valid transmission character, and when B0 is off, it indicates that TCR0 is invalid data. Similarly, B1 and TCR1 correspond, TCR2 of B2 corresponds, and B3 and TCR3 correspond.

Next, when there is an interrupt request from the line adapter 2-1 to the FIFO control section 1-1 via the interrupt request line 500-1, the status register of the line adapter 2-1 is read out and LSTR15-1
Hold on. The status of the line adapter 2-1 consists of a transmission character request bit, a reception character take-up request bit, a transmission interrupt bit, a reception interrupt bit and a peripheral interrupt bit. The transmission interrupt bit, the reception interrupt bit and the peripheral interrupt bit are LSTR15. It is also set in FSTR14-1 at the same time when it is read to -1. One byte or more is stacked in the transmission FIFO memory 11-1 and LSTR
When the transmission character request bit is set in 15-1, the control circuit 18-1 reads one byte from the transmission FIFO memory 11-1 and sets it in TBPR16-1, and the B0 of TBP set in TBPR16-1 is turned on. If so, transmit FIFO memory 11
-1 to 1 byte (TCR0) read, data bus 300-1
The transmission character register of the line adapter 2-1 is written to the transmission character request bit of LSTR15-1 and the transmission operation is completed. Here, if B0 of TBP is off, empty reading of TCR0 is performed from the transmission FIFO memory 11-1, and if B1 of TBP is on, one more byte TCR1
Is read and written in the transmission character register of the line adapter 2-1. In this operation, B0 to B3 of TBP are sequentially examined, and TCRi-1 corresponding to ON Bi is read idle until TCRi-1 is sent to the line adapter. Similarly, when an interrupt request is further read from the line adapter 2-1 to the LSTR15-1, TCRi + 1 is sequentially read from the transmission FIFO memory 11-1.
Transmission data is transmitted to the line adapter 2-1 until it becomes TCR3, and when TCR3 is transmitted, next, TBP is read to TBPR16-1 and the above operation is repeated.

In this series of transmission operations, transmission characters are sequentially transmitted to the line adapter in accordance with the TBP read by TBPR16-1, and if all of TBP from Bi to B3 are off, the T for Bi is
From CR1 to TCR3, empty reading is performed from the transmission FIFO memory 11-1, and the data is removed from the transmission FIFO memory 11-1. Also TB
If the EOC bit of TBP set in PR16-1 is on, after sending the transmission character from B0 to B3 of TBP or empty reading, write line 600 to line adapter 2-1.
-1 and 300-1 to send a transmission end command. In addition, the control circuit transmits from the line common control unit
It counts the number of bytes written to the FIFO memory 11-1, that is, "0" to "4". When this count value is "0", it is the timing at which TBP is written to the transmission FIFO memory 11-1. , If the EOC bit of this TBP is checked and it is on, the transmission interrupt mask is turned on and TBP is turned on.
After writing the 4 bytes of transmission data following to the transmission FIFO memory, the transmission request from the FIFO control unit 1-1 to the line common control unit 3 is suppressed. The interrupt mask of this transmission is canceled again when the transmission end command is written to the line adapter 2-1 via the write line 600-1, as described above.

Next, the case of reception will be described. Line common control unit 3
When a command for initial setting of the receiving section and a command for receiving control is written to the line adapter 2-1 via the bidirectional driver 13-1, the state becomes receivable. 1 in line adapter 2-1
When the character is received, a processing request is issued to the FIFO control section 1-1 via the interrupt request line 500-1. FIFO control unit 1-
When 1 detects this interrupt, it reads and sets the status of the line adapter 2-1 to LSTR15-1, and if the received character take-up request bit of the status is ON, 1 is received from the received character register of the line adapter 2-1. Stacked in character read / receive FIFO memory 12-1, and LSTR
Reset the received character take-up request bit of 15-1. After that, similarly, every time there is a request for receiving the received character from the line adapter 2-1, the received character is stacked in the receiving FIFO memory 12-1, and 4 bytes (in this embodiment, one character is 8 bits and is the same as 1 byte). After being stacked, the control circuit 18-1 sets the RBP in the RBPR 17-1 and stacks this RBP in the reception FIFO memory 12-1. Here, B0 to B3 of RBP are the reception FIFO memory 12-1.
The received characters RCR0 to RCR3 stacked on each correspond to each other, and represent the valid and invalid states of RCR0 to RCR3.
That is, when B0 to B3 are on, the corresponding RCR0 to RCR3 are valid reception data.

When 5 bytes including RBP are stacked in the reception FIFO memory 12-1 in this way, the control circuit turns on the reception character take-up request bit of FSTR14-1 and interrupt line 400
An interrupt request is sent to the line common controller 3 via -1. When the line common control unit 3 detects that there is an interrupt request when scanning the FIFO control unit 1-1, it reads FSTR14-1, examines each bit of FSTR14-1 and turns on the receive character take-up request bit. If so, receive FIFO memory 12-
Reads 1 to 5 bytes in succession from RCR0 to RBP.
The line common control unit 3 transfers only valid received characters to BM5 according to this RBP. The OE bit of RBP is turned on when both the reception character take-up request bit and the reception interrupt bit are on in the status read by the interrupt request from the line adapter 2-1. That is, the fact that an overrun error has occurred in the line adapter 2-1 is reported to the line common control unit 3 by RBP.

When RCRi characters are stacked in the receive FIFO memory 12-1 and a receive interrupt request is received from the line adapter after that, dummy data is written to the characters from RCRi + 1 to RCR3 and the corresponding RBP is from B0 to Bi. Turn on, turn off Bi + 1 to B3 and tack.

The transmission and reception have been described above, but the transmission FIFO memory
11-1 and the reception FIFO memory 12-1 have TBP or TCR3 or RCR0 if the remaining bytes of the FIFO memory are empty.
It is also possible to stack one or more sets of each RBP. In addition, as described above, the line common control unit 3
If the transmit interrupt bit, transmit interrupt bit, and peripheral interrupt bit are on when TR14-1 is read,
The line common control unit 3 reads the transmission interrupt factor register, the reception interrupt factor register, and the peripheral interrupt factor register from the line adapter 2-1 through the bidirectional driver 13-1 and sends a processing request to MP6 to control the line state. .

Next, the operation of the apparatus of the second embodiment will be described with reference to FIGS. 1 and 5. Upon activation from the host device, IFC4 reads the control word from its main memory, decodes it, and transfers data from main memory to BM5 or from BM5 to main memory. MP6 runs a micro program on BM5,
It receives a processing request from the IFC4 or the line common controller 3, and issues a control command to the IFC4 or the line common controller 3. The MP6 also manages the send / receive buffer area for each line provided on the BM5. Line common control unit 3 is MP
It is started by the control command from 6.

In case of transmission, FI is received after receiving the command to prepare for transmission.
The FO controller 1-1 and the transmitter of the line adapter 2-1 are initialized, the control word set in advance on the BM5 is read and decoded, and the transfer start address and transfer byte of the transmission data are stored in the DMA control register for transmission. Set the number. When the line common control unit 3 detects a transmission request from the FIFO control unit 1-1 during the line scanning, it adds 4 bytes from BM5 according to the DMA control register for transmission and adds a valid display flag indicating valid or invalid, Four bytes one by one are continuously transferred to the FIFO control section 1-1 via the data bus 200, and the DMA control register and the count of the number of transfer bytes are updated. Similarly, every time there is a transmission request, 4 bytes are consecutively FI
Data is read to the FO control unit 1-1, and a processing request is sent to MP6 when the transmission is completed.

On the other hand, in the case of reception, when the reception preparation command is received from MP6, the FIFO control unit 1-1 and the reception unit of the line adapter 2-1 are initialized and the write start address of the reception buffer on BM5 is requested to MP6. , Set the secured write start address in the receive DMA control register. When the line common control unit 3 detects a reception request from the FIFO control unit 1-1 during a line scan, it continuously reads out 4 bytes of reception data with a valid display flag from the FIFO control unit 1-1, and receives the reception data.
Received data is written to BM5 according to the DMA control register and valid display flag, and the DMA control register is updated. FIF
Whenever a reception request is received from the O control unit 1-1, the DMA control register is updated to accumulate the reception data on the BM5, and when the reception is completed, the MP6 is requested to process.

That is, in the case of transmission, BM is sent from the host device via IFC4.
The transmission data is temporarily stored in 5, and is further transferred from the BM5 to the FIFO control unit 1 by the line common control unit 3. In the case of reception, the data received from the FIFO control unit 1 is temporarily stored in the BM5 by the line common control unit 3 and transferred to the upper main memory by the IFC4.

Next, the FIFO control unit, which is a feature of the present invention, will be described. FIG. 5 is a block diagram of the FIFO control section 1-1. The FIFO control unit 1-1 includes a transmission FIFO memory 11-1 and a reception FIFO memory.
FO memory 12-1, bidirectional driver 13-1, and status register of the FIFO control section 1-1 (hereinafter referred to as FSTR).
14-1, a register for reading and holding the status of the line adapter (hereinafter referred to as LSTR) 15-1, and a register for holding a transmission end command (hereinafter referred to as EOCR).
19-1, a control circuit 18-1, an interrupt request line 400-1 to the line common control unit 3, and an interrupt request line 500-1 from the line adapter 2-1.

The transmission data from the line common control unit 3 and the reception data to the line common control unit 3 are stacked in the transmission FIFO memory 11-1 and the reception FIFO memory 12-1, respectively, and the transmission end command is held in the EOCR19-1. The line common control unit 3 linearly reads or writes the control information other than these to the line adapter 2-1 through the bidirectional driver 13-1.

First, the case of transmission will be described. Line common control unit 3
When a transmission control command is sent from the FIFO control unit 1-1 to the FIFO control unit 1-1 via the data bus 200, it is written in the command register of the line adapter 2-1 via the bidirectional driver 13-1. While setting -1 to the transmission state,
A control circuit (not shown) releases the transmission interrupt mask,
If the remaining number of bytes of the transmission FIFO memory 11-1 is 4 bytes or more, the transmission character request bit of FSTR 14-1 is turned on (logic "1"). The line common control unit 3 scans the FIFO control units 1-1 to 1-8, and the FIFO control unit 1
When the interrupt is detected by the interrupt request line 400-1 in the scan of -1, the line common control unit 3 reads FSTR14-1. The FSTR 14-1 includes a transmission character request bit from the FIFO control unit 1-1 to the line common control unit 3, a reception character takeover request bit, and a transmission / reception interrupt request bit for directly displaying a transmission / reception interrupt from the line adapter 2-1. It consists of 5 bits, a reception interrupt request bit and a peripheral interrupt request bit. The line common control unit 3 reads FSTR14-1 and if the transmission character request bit is ON, the valid display flag and 4 bytes of transmission data are consecutively set. Send FIFO
Write to memory 11-1. Transmission data is written in the transmission FIFO memory 11-1 in the order of TCR0, TCR1, ..., TCR3. When the valid display flag B0 is on, it indicates that TCR0 is a valid character, and when B0 is off, it indicates that TCR0 is invalid data. Similarly, B1 and TCR1 correspond, B2 and TCR2
Corresponds, and B3 and TCR3 correspond.

Next, when there is an interrupt request from the line adapter 2-1 to the FIFO control section 1-1 via the interrupt request line 500-1, the status register of the line adapter 2-1 is read out and LSTR15-1
Hold on. The status of the line adapter 2-1 consists of a transmission character request bit, a reception character take-up request bit, a transmission interrupt bit, a reception interrupt bit and a peripheral interrupt bit. The transmission interrupt bit, the reception interrupt bit and the peripheral interrupt bit are LSTR15. It is also set in LSTR14-1 at the same time when it is read to -1. One byte or more is stacked in the transmission FIFO memory 11-1 and LS
When the transmission character request bit is set in TR15-1, one byte (TCR0) is read from the transmission FIFO memory 11-1 by the control circuit 18-1, and if the valid display flag B0 is on, the data bus 300- 1 through line adapter 2
-1 is written to the transmission character register, the transmission character request bit of LSTR15-1 is reset, and the transmission operation is ended. Here, if the valid display flag B0 corresponding to TCR0 is off, an empty read of TCTR0 is performed from the transmission FIFO memory 1-1, and if TCR1 is read and the corresponding valid display flag B1 is on, the line adapter is read. Write to the transmission character register 2-1. In this way, the transmit FIFO memory 11-
Empty reading is performed until the valid display flag read from 1 is turned on, and only valid transmission characters are sent to the line adapter 2
Transfer to -1. The same operation is repeated every time there is a transmission request from the line adapter 2.

The transmission character is transferred as described above, and when the line common control unit 3 writes a transmission end command in the EOCR 19-1, the above transmission interrupt mask is turned on and the line common control is performed from the transmission FIFO memory 11-1. Suppress the request to send to Part 3,
Do not write transmission data to the transmission FIFO memory 11-1. Then, all valid transmission characters stacked in the transmission FIFO memory 11-1 are transferred to the line adapter 2-1.
To the command register of the line adapter 2-1, the transmission interrupt mask is released again, and the transmission data from the line common control unit 3 to the transmission FIFO memory 11-1 is transferred to the transmission FIFO memory 11-1. Allow transfer.

Next, the case of reception will be described. Line common control unit 3
When a command for receiving section initialization and reception control is written to the line adapter 2-1 via the bidirectional driver 13-1, the reception becomes ready. When the line adapter 2-1 receives one character, it makes a processing request to the FIFO control unit 1-1 via the interrupt request line 500-1. FIFO controller 1-1
When this interrupt is detected, the status of the line adapter is read and set in LSTR15-1, and if the receive character take-up request bit of the status is ON, one character is read from the receive character register of line adapter 2-1 and received. The valid display flag is turned on and stacked in the FIFO memory 12-1, and the received character take-up request bit of LSTR15-1 is reset. After that, similarly, line adapter 2
-1 Receive FIFO every time there is a request to receive the received character
Stack in memory 12-1. Here, when RCRi characters are stacked in the receive FIFO memory 12-1 and a receive interrupt request is issued from the line adapter after that, RCRi + 1
Dummy data is written to the characters from RCR3 to RCR3, and the corresponding valid display flags are set to B0 to Bi on and Bi + 1 to B3 off. When the 4-byte received character is stacked in the receive FIFO memory 12-1 in this way, the control circuit 18-1 causes the FSTR14
The received character take-up request bit of -1 is turned on, and an interrupt request is issued to the line common control unit 3 via the interrupt line 400-1. When the line common control unit 3 detects that there is an interrupt request when scanning the FIFO control unit 1-1, FSTR
14-1 is read, each bit of FSTR14-1 is examined, and if the receive character take-up request bit is on, the receive FIFO
4 bytes are continuously read from the memory 12-1 in the order of RCR0 to RCR3. The line common control unit 3 transfers only valid received characters to the BM5 according to the valid display flag.

The transmission and reception have been described above, but the transmission FIFO memory
11-1 and the reception FIFO memory 12-1 have TCR0 to TCR3 or RCR0 if there are empty bytes remaining in the FIFO memory.
It is also possible to stack one or more sets of each RCR3. In addition, as described above, the line common control unit 3
If any of the transmission interrupt bit, the reception interrupt bit, and the week side interrupt bit is on when TR14-1 is read, the line common control unit 3 causes the line adapter 2-1 to pass through the bidirectional driver 13-1. The transmit interrupt factor register, receive interrupt factor register, and peripheral interrupt factor register are read, and a processing request is sent to MP6 to control the line status.

Next, the line adapter will be described. Figure 6 shows HDLC
It is a block block diagram which shows the structure of the line adapter which transmits and receives a procedure. The input / output control circuit 21-1 is a circuit for controlling input / output of a readable or writable register in the line adapter, and signals D ₀ to D ₇ are transmitted / received to / from the data bus 300-1 and addresses A ₀ to A ₂ Is the read register 22'-
1 or the address of the write register 22-1. The control line RD is a control line for instructing reading, and the control line WR is a control line for instructing writing. The write register 22-1 includes a command register, a reset register, and a transmission character register. The command register is a register that controls the operation of the line adapter, and the reset register is a register that initializes the entire line adapter. The register is a register for writing a transmission character. Read register 22 ′
-1 has 6 types of registers, of which the status register consists of 5 bits: week side interrupt bit, transmission character request bit, transmission interrupt bit, reception interrupt bit, and reception character take-up request bit. The interrupt factor is set in, the write request to the transmit character register, the interrupt factor is set in the transmit interrupt register, the interrupt factor is set in the receive interrupt register, and the receive from the receive character register A request to collect data is displayed. The peripheral status register indicates the status of the peripheral input pins PI1 and PI5. The INT signal is a signal obtained by ORing each bit of the status register and indicates that there is any interrupt.

When transmission data is set in the transmission character register, the transmission / reception control circuit 24-1 controls the internal data bus 700.
-1 is written in the transmission shift register of the transmission circuit 25-1 and the parallel-serial conversion is performed here.
Sent to the line via -1. The driver circuit 27-1 performs code conversion and level conversion of transmission data. At the time of reception, the receiver circuit 28-1 performs level conversion and code conversion of the data on the line, the transmission / reception control circuit 24-1 shifts the received shift register of the reception circuit 26-1 bit by bit, and when one character is received, the internal data is received. Bus 700-
It is set in the receive character register of the read register 22'-1 via 1 and the bit of the receive data take-up request of the status register is turned on to make an interrupt request.

〔The invention's effect〕

As described above, the present invention provides the FIFO control section between the line common control section and the line adapter to continuously transfer the data between the line common control section and the FIFO control section by a predetermined number of bytes. By doing so, it is possible to minimize the change in the hardware of the line common control unit and connect a large number of line adapters or high-speed line adapters.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. FIG. 2 is a block configuration diagram showing the configuration of the FIFO control unit of the first embodiment. Figures 3 and 4 are TBP and RBP format diagrams. FIG. 5 is a block diagram showing the structure of the FIFO control unit of the second embodiment. FIG. 6 is a block diagram showing the configuration of the line adapter. 1 ... FIFO control unit, 2 ... line adapter, 3 ... line common control unit, 4 ... interface control unit (IFC), 5 ...
… Buffer memory (BM), 6 …… Microprocessor (MP), 11 …… Transmission FIFO memory, 12 …… Reception FIFO memory, 13 …… Bidirectional driver, 14 …… Status register (FSTR), 15 …… Register (LSTR), 16 ... Register (TBPR), 17 ... Register (RBPR), 18 ... Control circuit,
19 ... Register (EOCR), 21 ... Input / output control circuit, 22 ...
... write register, 22 '... read register, 23 ... interrupt control circuit, 24 ... transmission / reception control circuit, 25 ... transmission circuit, 26 ... reception circuit, 27 ... driver circuit, 28 ... receiver circuit, 29 ... peripheral input / output control circuit, 100 ... processor bus, 200, 300 ... data bus, 400, 500 ... interrupt request line, 600 ... command write line for transmission end, 700 ...
… Internal data bus.

Claims (1)

[Claims] 1. A line adapter (2-1 to 2-8) connected to each of a plurality of communication circuits, and a line common control unit (3) for setting a route between a host device and this line adapter. A communication control device comprising: a first memory (11) which is a first-in first-out memory inserted in a transmission path between the line common control unit and the line adapter; the line common control unit and the line adapter; A second memory (12) which is a first-in first-out memory inserted in the reception path between the two and a control means for controlling the first and second memories, wherein the control means transmits a predetermined plurality of characters. Data is written as one unit from the line common control unit to the first memory and then transferred to the line adapter for each character. A communication control device which comprises a means for transferring as a unit of the received data of a predetermined plurality characters to the line common control unit after being stored in the memory.