JPS58120346A - Line adaptor - Google Patents

Abstract

PURPOSE:To improve the high processing speed and the economy of the device, by avoiding the storage of reception data in a reception line adaptor of the character buffer system. CONSTITUTION:When a reception data bit from a line is given to a shift register 2 via a first-in first-out shift memory 1, while a reception character finished for the assembling exists in a buffer register 3 just before without being fetched to a communication controller LC, after the reception of bits subtracted by 1 bit, a reception control circuit 4 controls that the input of reception data bit from the memory 1 to the shift register 2 is tentatively stopped. Thus, normally, since the reception data is not stored, the processing speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving line adapter using a character buffer method.

Generally, as a control method for received data applied to a data communication system, the received data from one line is assembled into characters by a line adapter LA, and the first communication control device LC pulls the received data character by character from the line adapter LA. The method of taking is adopted. This system is schematically shown in Figure 1. In this figure, PU is a data processing device controlled by a communication control device LC. In this method, when the second communication control device LC receives a special received character, the processing time for that received character may temporarily increase.

Even in such a case, in order to receive the subsequent received data normally without overflowing, it is possible to shorten the character processing time of the two communication control devices, provide multiple character buffers in one line adapter, or
Measures such as providing first-in/first-out memory are being taken. However, among these methods, it is difficult to shorten the character processing time when the bit transmission speed becomes faster.
Furthermore, the method of providing a plurality of character buffers has the disadvantage that the circuit of the line adapter increases. Therefore, a method of providing a first-in/first-out shift memory is currently adopted.

However, in the method using the first-in/first-out shift memory, if the difference between the bit transmission speed of the received data from one line and the speed of extracting the contents of the first-in/first-out shift memory is insufficient, the conventional method uses To prohibit the input of received data bits from the first-in/first-out shift memory to the shift register for assembling received characters until the received data in the received character buffer is received by the communication control device 1 when the received character buffer is full. To,
There was a drawback that received data was accumulated in the first-in/first-out shift memory.

The purpose of the present invention is to transfer data from the line to the first-in/first-out shift memory even if the difference between the bit transmission rate of received data from one line and the speed of extracting the contents of the first-in/first-out shift memory is insufficient. It is an object of the present invention to provide a communication control line adapter that can perform high-speed processing by eliminating the accumulation of received data.

According to the present invention, there is provided a first-in/first-out shift memory that sequentially stores received data bits from two lines at the bit transmission rate of the line, and a reception character of a required number of bits based on the output of the first-in/first-out shift memory. It is equipped with a shift register that is assembled into a shift register, and a buffer register that temporarily stores the received characters assembled by the shift register, and when receiving data from the 9th line, the received characters that have been assembled just before are received by the communication control device. A line adapter can be obtained which controls the input of the required number of bits minus 1 bit while it is present in the buffer register without being stored.

Next, nine embodiments of the line adapter according to the present invention will be described with reference to two drawings.

FIG. 2 shows the configuration of an embodiment according to the present invention.As seen in the specific example of the receive character assembly shift register 21, the receive character buffer register 3, and the receive control circuit diagram, first-in first-out cascade connection is performed. It is formed by shift memories 1-1 to 1-n. When the shift memory 1-1 is counted once, if the shift memory 1-1 is empty, the received data bits are stored at a timing synchronized with the bit transmission speed of the two lines.

The received data stored in the first-in/first-out shift memory is transferred to the first-in/first-out shift memory 1-2 after waiting for the first-in/first-out shift memory 1-2 to become empty. Thereafter, this received data moves each bit of the first-in/first-out shift memory toward the first-in/first-out shift memory 1-n by the same operation.

The reception control circuit 4 checks the state of the first-in/first-out shift memory l-n and the state of the reception character buffer register 3 at a timing faster than the bit transmission rate of one line, and checks the state of the first-in/first-out shift memory 1. ．． - If n characters are full and the reception character buffer register 3 is "empty", input the reception data bits stored in the first-in/first-out shift memory 1-n to the reception character assembly shift register 2. . Immediately after this, when the received character assembling shift register 2 detects the completion of assembling one character, the received character is transferred to the received character buffer register 3. The received character buffer completion register 3 to which the received character has been transferred does not display an indication that the received character buffer register is "full" until the received character is received by the communication control device LC (see Figure 1). Do it in 4. The reception control circuit 4 prohibits the reception character register 3 from being "full" and inputting the reception data bits to the shift register 2 for the required bit.

To explain the reason why the input of received data bits to the shift register 2 is prohibited, 9. For example, suppose that the bit transmission rate of one line is 48 Kbps, and the speed at which the received data stored in the first-in/first-out shift memory is received is Assuming that 64 Kbpa, the required number of bits is 8 bits, the receive character buffer register is "full", and it takes 10 μs for the 2nd communication control unit LC to take over the contents of the receive character buffer register, the conventional method uses 4 bits.
1 character time approximately 20.8μS at 8Kbps speed
r 1 character time at a speed of 64Kbps approximately 1
It takes 5.6 μs. From this, the time it takes for the reception character register to become "full" and the communication control device 9 to take over the data until the reception character buffer becomes "full" is the 64 in the time it takes to receive data from the buffer register
The time for one character at a speed of Kbps is approximately 256 μs, which exceeds the time for one character at a speed of 48 Kbps (approximately 208 μSi. This means that the data is reliably stored in the first-in e first-out shift memory. On the other hand, according to the method of the present invention, under the above assumption, it can be achieved in about 15.6 μs, and temporary first-in
Even if the received data is stored in the first outshift memory, there are no drawbacks as in the prior art.

Also, the point at which input of received data bits is prohibited is set to the required number of bits minus 1 bit.

In order to automatically set the timing at which received data is set from the receive character assembly shift register to the receive character buffer and buffer registers according to the required number of bits, conventionally the receive character buffer register was set to "empty". The time from "full" to "full" is 1 pit (in the above example, about 1 , 95 μs).

Note that in the above embodiment, when the timing synchronized with the bit transmission rate of one line is output.

First-in/first-out shift memory 1-1
If the received data bits cannot be stored and overflow occurs when the data bits are less than 1, the reception control circuit 4 notifies the communication control device LC of the detection of the overflow.

Preferably, the capacity of the first-in/first-out shift memory is selected to such an extent that the difference between the bit transmission speed of one line and the processing speed of the communication control device LC does not cause overflow.

As is clear from the above explanation, (1) according to the present invention, there is a sufficient difference between the bit transmission speed of the received data from the 9 lines and the speed at which the received data stored in the first-in/first-out shift memory is received. If not, even if the received data from the line may be temporarily accumulated in the first-in/first-out shift memory, it is possible to prevent the received data from being accumulated in the normal case with a simple configuration. Thereby, the effects of increasing the processing speed and improving the economical efficiency of the apparatus are significant.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an outline of a general reception data control method applied to a conventional data communication system, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. FIG. 2 is a block diagram showing a configuration example of a first-in/first-out shift memory in FIG. 2; In each figure, 1 is a first-in/first-out shift memory, 1-1 to 1-n are each shift memory stage of the first-in/first-out shift memory, 2 is a shift register for assembling received characters, and 3 is a buffer for receiving characters. 4 is a register, a reception control circuit, LA is a circuit adapter, LC is a communication control device, and PU is a data processing device. Figure 1 Figure 3

Claims (1)

[Claims] 1. A first-in/first-out shift memory that sequentially stores received data bits from the line at the bit transmission rate of the line, and a shift register that receives the output of the first-in/first-out shift memory and assembles it into a received character with the required number of pits. and a buffer register that temporarily stores the received characters assembled by the shift register, and when the received characters assembled by the shift register are given to the shift register, the previously assembled received character is not picked up by the communication control device and remains in the buffer register. A line adapter that controls the input of received data bits to the shift register to be temporarily stopped.