JPS6342546A - Communication control equipment - Google Patents

Abstract

PURPOSE:To connect a high-speed line adapter by writing transmission data, which consists of a prescribed number of characters including an effective display flag for each character, in the first memory from a common control part and providing a means which transfers transmission data, which indicates that the effective display flag is effective, for each character to the line adapter connected to the first memory. CONSTITUTION:In case of transmission, a command is written in a command register of a line adapter 2-1 through a bidirectional driver 13-1 when the command of transmission control is transmitted from a line common control part 3 to a FIFO control part 1-1 through a data bus 200. An FSTR 14-1 consists of 5 bits, namely, the bit of transmission character request from the FIFO control part 1-1 to the line common control part 3, the bit of reception character acceptance request, the bit of transmission/reception interrupt request where the transmission/reception interrupt from the line adapter 2-1 is displayed as it is, the bit of reception interrupt request, and the bit of peripheral interrupt request, and the line common control part 3 reads out contents of the FSTR 14-1, and the control part 3 writes continuously 4-byte transmission data in a transmission FIFO memory 11-1 together with the effective display flag if the bit of transmission character request is turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to means for responding to changes in specifications of a communication control device.

〔overview〕

The present invention provides a communication control device in which a route between a line adapter and a higher-level device is set by a line common control unit, by inserting a first-in, first-out memory between the line common control unit and the line adapter. This makes it possible to minimize changes in the /'t-ware related to specification changes.

(Prior Art) In this type of communication control device, a line common control unit sequentially scans processing requests from multiple line adapters, and if there is a processing request, sends transmission data to the corresponding line adapter.
It manages multiple lines at once by receiving received data, sending line control commands, reading line status registers, etc.

[Problem that the invention seeks to solve]

Therefore, when a high-speed line adapter or a large number of line adapters are installed, it is necessary to redesign the line common control unit each time to increase the processing capacity, or to increase the processing capacity of the bus that connects the line common control unit and the line adapters. It needed to be wider.

The present invention aims to eliminate such drawbacks and to provide a communication control device that can minimize changes in hardware.

[Means for solving problems]

The present invention provides a communication control device including a line adapter connected to each of a plurality of communication circuits and a line common control unit that sets a route between a host device and the line adapter. a first memory that is a first-in, first-out memory inserted in a transmission path between the line common controller and the line adapter; and a second memory that is a first-in, first-out memory that is inserted in a reception path between the line common control unit and the line adapter. The device is characterized by comprising a memory and control means for controlling the first and second memories.

The control means writes a predetermined number of transmission data including a valid display flag for each character of the transmission data from the common control unit to the first memory, and writes one transmission data indicating that the validity flag is valid. A means for transferring each character to a line adapter connected to this memory, and writing the received data character by character to the second memory together with a valid display flag attached to each character of the received data. It may also include means for transmitting received data indicating that the validity display flag is valid, character by character, to the line common control unit when a predetermined number of characters are stacked in the memory.

Further, the control means writes transmission data of a predetermined number of characters including transmission control information of 1 character from the line common control unit to the first memory, and writes transmission data of 1 character indicating that the transmission control information is valid. A means for transferring each character to a line adapter connected to this memory, and a means for writing received data character by character to the second memory, and when a predetermined number of characters are stacked in this second memory, l. It may also include means for transferring received data including character reception control information to the line common control section.

[Operation] In the first embodiment, at the time of transmission, transmission data of a predetermined number of characters including transmission control information is continuously transferred from the line common control unit to the transmission FIFO, and a transmission request from the line adapter is received. Transmit F according to the transmission control information every time
Extract each character from the IFO memory and transfer it to the line adapter.

Also, during reception, each time there is a reception request from the line adapter, one character is read out from the line adapter, and the reception FIF
When received data of a predetermined number of characters are stacked in the O memory and received data of a predetermined number of characters are stacked in the receive FIFO memory, the line common control unit is made to sequentially and continuously receive the received data and reception control information.

In the second embodiment, at the time of transmission, a valid display flag for each character is added to the transmission data, and the transmission data of a predetermined number of characters is continuously transferred from the line common control unit to the transmission FIFO memory, and the line adapter Each time there is a transmission request from the transmission FIFO memory, one character is taken out from the transmission FIFO memory, and only the valid characters are transferred to the line adapter based on the validity display flag.

Also, during reception, each time there is a reception request from the line adapter, one character is read out from the line adapter, and the reception FI
When a valid display flag is added to the FO memory and received data of a predetermined number of characters is stacked in the receive FIFO memory, the line common control unit is made to sequentially and continuously receive the received data.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. This embodiment device includes a microprocessor (hereinafter referred to as MP) 6, a buffer memory (hereinafter referred to as BM) 5, which is a memory that temporarily holds transmitted and received data for each line and stores a microprogram. An interface control unit (hereinafter referred to as IFC) that controls data transfer between the main memory of the host device and the 8M5.
4, FIFO controllers 1-1 to 1-8 including line-compatible transmission FIFO memory and reception FIFO memory, line adapters 2-1 to 2-8, and
A line common control unit 3 that controls transmission and reception between M5 and FIFO control units 1-1 to 1-8, a processor bus 100, a line common control unit 3, and F t F oil? 31 part 1
-1 to 1-8, and a data bus 200 connecting F
Data buses 300-1 to 300 connect IFO control units 1-1 to 1-8 and corresponding line adapters, respectively.
0-8. Here, F I F O*Ji!
It sections 1-2 to 1-8 and line adapters 2-2 to 2-8 have the same functions as FIFO control section 1-1 and line adapter 2-1, respectively.

Next, the operation of the apparatus of the first embodiment will be explained based on FIGS. 1 to 4. IFC by starting from the host device
4 sequentially reads and decodes control words from its main memory, and transfers data from the main memory to 8M5 or from 8M5 to the main memory.

MP6 executes the microprogram on 8MS, and the IF
It accepts processing requests from the C4 or line common control unit 3, and issues control commands to the IFC4 or line common control unit 3. Furthermore, the MP6 manages the transmitting and receiving buffer area corresponding to each line provided on the 8MS. The line common control unit 3 is activated by a control command from the MP6.

For sending, receive the command to prepare for sending and press F.
Initialize the IFO control unit 1-1 and the transmission unit of the line adapter 2-1, read and decode the control word set in advance on 8MS, and write the transmission data transfer start address and the transmission data into the transmission DMA control register. Set the number of bytes to transfer. The line common control unit 3 performs F I F during line scanning.
O*j? When a transmission request from i1 unit 1-1 is detected,
Read 4 bytes from 8M5 in the DMAa register for transmission, add transmission control information as control information to the beginning,
Five bytes are successively transferred one byte at a time to the FIFO control unit 1-1 via the data bus 200, and the DMA control register and transfer byte number counter are updated. Similarly, every time there is a transmission request, five consecutive bytes of data are sent to the FIFO control unit 1-1, and when the transmission ends, a processing request is made to the MP6.

On the other hand, in the case of reception, the command to prepare for reception is sent to MP.
6, initializes the FIFO control unit 1-1 and the receiving unit of line adapter 2-1, requests the write start address of the receive buffer on 8MS, and writes the secured write start address to the receive DMA control register. Set. The line common control unit 3 uses the FIFO control unit 1-1 during line scanning.
When a reception request is detected from PIFOf? JI Gobe 1-
Read 5 bytes continuously from 1 byte at a time, receive D
The received data is written to 8M5 according to the MA control register and reception control information, and the DMA control register is updated. DMA every time there is a reception request from the FIFO control unit 1-1.
The received data is accumulated on the 8MS while updating the w1'4TJ register, and upon completion of reception, a processing request is made to the MP6.

That is, in the case of transmission, transmission data is temporarily stored in the 8M5 from the host device via the IFC 4, and is further transferred from the 8M5 to the FIFO control unit l by the line common control unit 3. In the case of reception, the received data from the FIFO control unit 1 is temporarily stored on 8MS by the line common control unit 3, and transferred to the upper main memory by the IFC 4.

Next, the FIFO control unit, which is a feature of the present invention, will be explained. FIG. 2 is a block diagram of the FIFO control unit 1-1, and FIGS. 3 and 4 are transmission control information (hereinafter referred to as TBP)
That's what it means. ) and reception control information (hereinafter referred to as RBP).

) is a format diagram. This FIFO? blJ control section 1-1 has sending section 1FO memo January 1-1 and receiving FIFO
Memo January 2-1, bidirectional driver 13-1, and sending F
A register (hereinafter referred to as TBPR) 16-1 that holds the TBP read from the IFO memory 11-1, a register (hereinafter referred to as RBPR) 17-1 that writes the RBP to the receiving FIFO memory 12-1, and a FIFO Control part 1
-1 status register (hereinafter referred to as FSTR)
14-1, and a register (hereinafter referred to as LSTR) 15 that reads and holds the status of the line adapter 2-1.
~l, the control circuit 18-1, the interrupt request vA400-1 to the line common control unit 3, and the interrupt request from the line adapter 2-1! 500-1, and a command write line 600-1 for instructing the line adapter 2-1 that the final character has been sent.

The transmission data and TBP from the line common control unit 3 and the reception data and RBP to the line common control unit 8 3 are stacked in the transmission FIFO memory 11-1 and the reception FIFO memory 12-1, respectively, but other than these The line common control unit 3 directly reads or writes the control information to the line adapter 2-1 via the bidirectional driver 13-1.

First, the case of transmission will be explained. Line common control unit 3
When a command from the transmission control section is sent from the FIFO control section 1-1 to the FIFO control section 1-1 via the data bus 200, it is written to the line adapter 2-1 via the bidirectional driver 13-1. At the same time, the control circuit (not shown) cancels the transmission interrupt mask, and the transmission FIF
If the remaining number of bytes in the O memory 11-1 is 5 or more, that is, if it is possible to write 4 bytes of transmission data and TBPI bytes, turn on the transmission character request bit of the FSTR 14-1 (logic "L"). ). The line common control unit 3 scans the FIFO control units 1-1 to 1-8, and when an interrupt is detected on the interrupt request line 400-1 during scanning of the FIFO control unit 1-1, the line common control unit 3 -1 is read. This F
STR14-1D is a transmitter that directly displays the transmission character request bit from the FIFO control unit 1-1 to the line common control unit 3, the reception character withdrawal request bit, and the transmission/reception interrupt from the line adapter 2-1. It consists of 5 bits: an interrupt request bit, a receive interrupt request via), and a peripheral interrupt request bit.
14-1 and if the transmission character request bit is on, TBP and transmission data are successively written into the 5-byte transmission FIFO memory 11-1. The transmission FIFO memory 11-1 includes TBP, TCROlTCRI, -1TC
Transmission data is written in the order of R3. When BO of TBP is on, it indicates that TCRO is a valid transmission character, and when BO is off, it indicates that TCRO is invalid data. Similarly, Bl and TCRl correspond, and B2
and TCR2 correspond to B3 and TCR3.

Next, from the line adapter 2-1 to the interrupt request line 500-1
Via F I F Oili? When the 21 section 1-1 receives an interrupt request, the status register of the line adapter 2-1 is read out and held in the LSTR 15-1. The status of line adapter 2-1 includes the transmission character request bit,
Receive character takeover request bit, transmission interrupt bit,
Consists of receive interrupt bits and peripheral interrupt bits.
The transmit interrupt bit, receive interrupt bit, and peripheral interrupt bit are read out to the FST at the same time as they are read to LSTR15-1.
It is also set in R14-1.

If 1 byte or more is stacked in the transmission FIFO memory 11-1 and a transmission character request bit is sent to the LSTR 15-1, the control circuit 18-1 reads 1 byte from the transmission FIFO memory 11-1 TBP.
If set to R16-1 and BO of TBP set to TBPR16-1 is on, transmit FIFO memory 1
One byte (TCRO) is generated one after another from 1-1 and written to the transmission character register of line adapter 2-1 via data bus 300-1, and the transmission character request bit of LST R15-1 is reset to start the transmission operation. finish. Here, if the TBP BO is off, the transmit FIFO
Performs an empty read of TCRO from memory 11-1 and sets TBP
If 81 is on, 1 byte TCRI is further read out and written to the transmission character register of line adapter 2-1. In this operation, BO to B3 of the TBP are checked sequentially, and up to TCRi-1 is read blankly so as to send TCRi corresponding to Bi turned on to the line adapter. Similarly, an interrupt request is sent from line adapter 2-1 to LST.
When read to R15-1, TCRi+1 is sequentially read from the transmission FIFO memory 11-1, and the transmission data is sent to the line adapter 2-1 until TCR3 is sent. When TCR3 is sent, TBP is then changed to TBPR16-1. is read out,
Repeat the above operation.

In this series of transmission operations, transmission characters are sequentially sent to the line adapter according to the TBP read in TBP R16-1, and if all of the TBPs from Bi to B3 are off, the characters from TCRI to TCR3 for Bi are not transmitted. A blank read is performed from the FIFO memory and removed from the transmit FIFO memo January 1-1.

Also, the EOC of TBP set to TBPR16~l
When Bift is on, after sending or empty reading the transmission characters from BO to B3 of TBP, sends a transmission end command to line adapter 2-1 via write lines 600-1 and 300-1. .

In addition, the control circuit also controls the transmitting FIF from the line common control unit 3.
The number of bytes written to O memo January 1-1, that is, "0" to "4", is counted, and this count value is rO
In the case of J, it is the timing when TBP is written to the transmission FIFO memory 11-1, and if the EOC bit of this TBP is checked and it is on, the above-mentioned transmission interrupt mask is turned on, and the 4 bytes following TBP are transmitted. Send data FIF
After writing to the O memory 11-1, the transmission request from the FIFO 9t control unit 1-1 to the line common control unit 3 is suppressed.

The interrupt mask for this transmission is, as described above, the write line 6
Sends the command to end transmission via 00-1 to line adapter 2.
It is cleared again when written to -1.

Next, the case of reception will be explained. Line common control unit 3
When commands for receiving unit initialization and reception control are written to the line adapter 2-1 via the bidirectional driver 13-1, the line adapter 2-1 becomes ready for reception.

When line adapter 2-1 receives one character, the PI
A processing request is made to the FOofIIJ control unit 1-1 via the interrupt request line 500-1. When the FIFO control unit 1-1 detects this interrupt, it reads and sets the status of the line adapter 2-1 in the LST R15-1, and if the received character takeover request bit in the status is on, the line adapter 2 One character is continuously outputted from the reception character register of -1 and stacked in the reception FIFO memory 12-1, and the reception character takeover request bit of LST R15-1 is reset. Thereafter, in the same way, line adapter 2-
Every time there is a request to pick up a received character from 1, the reception FIF
The characters are stacked in the O memory 12-1, and when 4 bytes (in this embodiment, the l character consists of 8 bits and is the same as 1 byte) are stacked, the control circuit 18-1 outputs the RB PR 17-1. Cent RBP to this R
The BP is stacked in the reception FIFO memory 12-1. Here, BO to B3 of RBP is the reception FIFO memory 1.
Received character RCRO or R stuck in 2-1
Each corresponds to CR3 and represents the valid/invalid state of RCRO to RCR3. That is, when BO to B3 are on, the corresponding RCRO to RCR3 are valid received data.

When 5 bytes including the RBP are stacked in the receive FIFO memory 12-1 in this way, the control circuit causes the F S
Turn on the received character takeover request bit of T R14-1, and send it to the line common control unit 3 via the interrupt line 400-1.
Make an interrupt request. When the line common control unit 3 detects that there is an interrupt request when scanning the FIFO control unit 1-1, it reads the FSTR 14-1 and sends the FST
Check each bit of R14-1, and if the receive character takeover request bit is on, the receive FIFO memory 12-
1 to 5 bytes are continuously output in the order of RCRO to RBP. The line common control unit 3 transfers only valid received characters to 8M5 according to this RBP. In addition, R.B.
The OE bit of P turns on when both the receive character takeover request high and receive interrupt bits are on in the status read by the interrupt request from the line adapter 2-1. That is, the fact that an overrun error has occurred in the line adapter 2-1 is reported to the line common control unit 3 using RBP.

When the character RCRi is stacked in the reception FIFO memory 12-1 and a reception interrupt request is received from the line adapter after that, dummy data is written to the characters RCRi+1 to RCR3, and the corresponding RBP is set to B.
Turn on O to Bi, turn off B i+1 to B3, and stack.

Transmission and reception have been explained above, but the transmission FIFO memory 11-1 and reception FIFO memory 12-1 have
If the number of remaining bytes in the IFO memory is empty, set TBP or TCR3 or RCRO or RBP to 1 each.
It is also possible to stack more than one pair. Furthermore, as described above, if the transmission interrupt bit, reception interrupt bit, and peripheral interrupt bit are on when the line common control unit 3 reads the FSTR 14-1, the line common control unit 3
reads the transmission interrupt cause register, reception interrupt cause register, and peripheral interrupt cause register from the line adapter 2-1 via the bidirectional driver 13-1, issues a processing request to MB2, and controls the line state.

Next, the operation of the second embodiment device will be explained based on FIGS. 1 and 5. IFC by starting from the host device
4 sequentially reads and decodes control words from its main memory, and transfers data from the main memory to 8M5 or from 8M5 to the main memory.

MB2 executes the microprogram on 8MS and
It accepts a processing request from the Fe2 or the line common control unit 3, and issues a control command to the IFC4 or the line common control unit 3. Further, MB2 manages the transmission/reception buffer area corresponding to each line provided on the 8MS. The line common control section 3 is activated by a control command from the MB2.

For sending, receive the command to prepare for sending and press F.
Initialize the IFO7td control unit Ll and the transmission unit of the line adapter 2-1, successively read and decode the control words set in advance on 8MS, and write the transmission data transfer start address and number of transfer bytes to the transmission DMA control register. Set. When the line common control unit 3 detects a transmission request from the FIFO control unit 1-1 during line kissing, it sends a DM for transmission.
A? tJ] 8M5 to 4 according to JTm register
A valid display flag is added to read the bytes to indicate whether they are valid or invalid, and 4 bytes are successively transferred one byte at a time to the FIFO control unit 1-1 via the data bus 200.
Update the MA control register and transfer byte count counter. Similarly, every time there is a transmission request, 4 bytes are sent to the FIF
Sends data to O control unit 1-1, and sends data to MB2 when transmission is completed.
Make a processing request to.

On the other hand, in the case of reception, when a reception preparation command is received from MB2, FIFO control unit 1-1 and line adapter 2
-1's receiving unit is initialized, the write start address of the receive buffer on the 8MS is requested from MB2, and the secured write start address is set in the receive DMA II control register. The line common control unit 3 uses FIFO during line scanning.
When a reception request is detected from the control unit 1-1, 4 bytes of reception data with a valid indication flag added are read out continuously from the FIFO control unit 1-1, and the reception data is transferred to 8M5 according to the reception DMA control register and the validity indication flag. Write, DMA control registers are updated. PIFO control unit 1
-1, the received data is accumulated on the 8MS while updating the DMA control register every time there is a reception request, and when the reception is completed, a processing request is made to the MP6.

That is, in the case of transmission, transmission data is temporarily stored in the 8M5 from the host device via the IFC 4, and is further transferred from the 8M5 to the FIFO control unit 1 by the line common control unit 3. In the case of reception, the received data from the FIFO control unit 1 is temporarily stored on 8MS by the line common control unit 3, and transferred to the upper main memory by the IFC 4.

Next, the FIFO control unit, which is a feature of the present invention, will be explained. FIG. 5 is a block diagram of the FIFO control section 1-1. This FIFO control unit 1-1 is a transmission FIFO memory 1.
1-1, the reception FIFO memory 12-1, the bidirectional driver 13-1, the status register (hereinafter referred to as FSTR) 14-1 of the FIFO control unit 1-1, and the status of the line adapter. A register to hold (hereinafter referred to as LSTR) 15-1 and a register to hold a transmission end command (hereinafter referred to as EOCR) 1
9-1, a control circuit 18-1, an interrupt request line 400-1 to the line common control unit 3, and an interrupt request line 500-1 from the line adapter 2-1.

Transmission data from the line common control unit 3 and reception data to the line common control unit 3 are stored in the transmission FIFO memory 11, respectively.
-1 and receive FIFO memory 12-1,
The transmission end command is held in the E OCR 19-1, but other than these; ν control information is stored in the bidirectional driver 13-1.
The line common control unit 3 directly reads or writes to the line adapter 2-1 via the line adapter 2-1.

First, the case of transmission will be explained. Line common control section 3
h'UF IFO? lj' data bus 2o to control unit 1-1;

When a transmission control command is sent out via the If the transmission interrupt mask is canceled by the control circuit and the number of remaining bytes in the transmission FIFO memo January 1-1 is 4 bytes or more, FST R14-
1's transmission character request bit is turned on (logical "IJ").The line common control section 3 is scanning the FIFO control sections 1-1 to 1-8, and when the FIFO control section 1-1 is scanned, an interrupt request is issued. When an interrupt is detected via the line 400-1, the line common control unit 3 reads the FSTR 14-1.The FSTR 14-1 contains a transmission character request bit and a reception character input from the FIFO control unit 1-1 to the line common control unit 3. The line common control unit 3 consists of 5 bits: a receive request bit, a send/receive interrupt request bit that directly displays the send/receive interrupt from the line adapter 2-1, a receive interrupt request bit, and a peripheral interrupt request bit.
14 to 1 are read and if the transmission character request bit is on, four hides of transmission data are successively written to the transmission FIFO memory 11-1 together with a valid display flag. Send F
IFO memo January 1-1 sends data from TCRO, TC
R1 and -1TCR3 are written in this order. When the valid display flag BO is on, it indicates that TCRO is a valid character, and when BO is off, it indicates that TCRO is invalid data. Similarly, B1 and TCR1 correspond, and B
2 corresponds to TCR2, and B3 corresponds to TCR3.

Next, from the line adapter 2-1 to the interrupt request line 500-1
When there is an interrupt request to the FIFO control unit 1-1 via
Read the status register of line adapter 2-1 LS
Maintain at TR15-1. The status of line adapter 2-1 consists of a transmit character request bit, a receive character takeover request bit, a transmit interrupt bit, a receive interrupt bit, and a peripheral interrupt bit, but the transmit interrupt bit, receive interrupt bit, and peripheral interrupt bit are LST.
When reading to R15-1, it is also sent to LSTR 14-1 at the same time.

If one byte or more is stacked in the transmit FIFO memory 11-1 and the transmit character request bit is set in the LSTR 15-1, the control circuit 18-1 stacks one byte (TCRO) from the transmit FIFO memory 11-1.
) is read, and if the valid display flag BO is on, it is written to the transmission character register of the line adapter 2-1 via the data bus 300-1, the transmission character request bit of LSTR 15-1 is reset, and the transmission operation ends. do. Here, if the valid display flag BO corresponding to TCRO is off, perform an empty read of TCRO from the transmission FIFO memory 1-1, and further read TC:R1, and if the corresponding valid display flag B1 is on, , line adapter 2-
Write to the transmit character register of 1. In this way, empty reading is performed until the valid display flag read from the transmission FIFO memory 11-1 turns on, and only valid transmission characters are transferred to the line adapter 2-1.

The same operation is repeated every time there is a transmission request from the line adapter 2.

Transmission characters are transferred as described above, and when the line common control unit 3 writes a transmission end command to the E OCR 19-1, the above-mentioned transmission interrupt mask is turned on, and the line common control unit 3 writes a transmission end command to the E OCR 19-1. A transmission request to the control unit 3 is suppressed, and transmission data is not written to the transmission FIFO memory 11-1.

Then, transmit (transmit all valid transmit characters stacked in the iFIFo memory 11-1 to the line adapter 2-
1, writes the EOCR19-1 transmission end command to the command register of line adapter 2-1,
At the same time, the transmission interrupt mask is released again, and the transmission data can be transferred from the line common control section 3 to the transmission FIFO memo 1-1.

Next, the case of reception will be explained. Line common control section 3
When commands for receiving unit initialization and reception control are written to the line adapter 2-1 via the bidirectional driver 13-1, the line adapter 2-1 becomes ready for reception. 1 with line adapter 2-1
When a character is received, a processing request is made to the PIF01111 unit 1-1 via the interrupt request line 500-1. FI
When the FO control unit 1-1 detects this interrupt, the FO control unit 1-1
15-1 to read and set the status of the line adapter, and if the received character takeover request bit in the status is on, one character is read from the receive character register of the line adapter 2-1, and the receive FIFO memory 12
-1 with the valid display flag turned on and stacked on LST
Reset the received character takeover request bit of R15-1. Thereafter, in the same way, each time there is a request for receiving a received character from the line adapter 2-1, the reception FIFO memory 12-
1 (.Here, receive FIFO memory 1
If the RCRi character is stacked in 2-1, and then there is a receive interrupt request from the line adapter, the RCRi
Dummy data is written in characters from +1 to RCR3, and the corresponding valid display flags are stacked with BO to Bi turned on and Bi+1 to B3 turned off. In this way, the reception FIFO memory 12
When a 4-byte received character is stacked on -1,
The control circuit 18-1 turns on the reception character takeover request bit of FST R14-1, and the interrupt line 40 is turned on.
An interrupt request is made to the line common control unit 3 via 0-1.

When the line common control unit 3 detects an interrupt request when scanning the FIFO control unit 1-1, the FSTR
14-1, examine each bit of FSTR14-1, and if the received character takeover request bit is on,
Continuously R 4 bytes from receive FIFO memory 12-1
Read out in order from CRO to RCR3.

The line common control unit 3 transfers only valid received characters to the BM 5 according to the valid display flag.

Transmission and reception have been explained above, but the transmission FIFO memory 11-1 and reception FIFO memory 12-1 have
If there is space in the remaining number of bytes of the IFO memory, it is also possible to stack TCRO to TCR3 or RCRO to RCR3 of 1 m or more each. Further, as described above, the line common control unit 3
If any of the transmission interrupt bit, reception interrupt bit, or peripheral interrupt bit is on when reading 1, the line common control unit 3 issues a transmission interrupt from the line adapter 2-1 via the bidirectional driver 13-1. It reads the cause register, reception interrupt cause register, and peripheral interrupt cause register, issues a processing request to MP6, and controls the line state.

Next, I will explain the line adapter. Figure 6 is HD
FIG. 2 is a block configuration diagram showing the configuration of a line adapter that transmits and receives LC procedures. The input/output control circuit 21-1 is a circuit that performs input/output control of readable or writable registers in the line adapter, and signals D0 and SIR are exchanged with the data bus 300-1, and addresses A0 and A2 are read registers. 22-1 or the address of the write register 22-1. The control line RD is a control line for instructing reading, and the control line WR is a control line for instructing writing. The write register 22-1 includes a command register, a reset/node register, and a transmission character register, the command register is a register that controls the operation of the line adapter, and the reset register is a register that sets the entire line adapter to an initial state. The transmission character register is a register into which transmission characters are written. The read register 22'-1 has six types of registers, among which the status register consists of five bits: a peripheral interrupt bit, a transmit character request bit, a transmit interrupt bit, a receive interrupt bit, and a receive character takeover request bit. An interrupt factor is set in the peripheral interrupt register, a write request is made to the transmit character register, an interrupt factor is set in the transmit interrupt register, an interrupt factor is set in the receive interrupt register, and the receive character register A request to retrieve received data from is displayed.

The peripheral status register indicates the status of peripheral input pins pH through PI5. INT (No. 8 is a signal obtained by ORing each bit of the status register, and indicates that there is an interrupt.

When transmission data is set in the transmission character register, the transmission/reception control circuit 24-1 sends the internal data bus 70.
The signal is written to the transmission shift register of the transmission circuit 25-1 via 0-1, undergoes parallel-to-serial conversion, and is sent to the line via the driver circuit 27-1.

The driver circuit 27-1 performs code conversion and level conversion of transmission data. At the time of reception, the receiver circuit 28-1
The data on the line is level-converted and code-converted by the transmitting/receiving control circuit 24-1, and shifted bit by bit to the receiving shift register of the receiving circuit 26-1. When l characters are received, the data is read via the internal data bus 700-1. It is set in the reception character register of register 22'-1, and the reception data takeover request bit of the status register is turned on to issue an interrupt request.

〔Effect of the invention〕

As explained above, the present invention provides a FIFO control section between a line common control section and a line adapter, and transfers data between the line common control section and the FIFO control section by continuously transmitting a predetermined number of bytes. By doing so, it is possible to minimize changes in the hardware of the line common control unit and make it possible to connect a large number of line adapters or high-speed line adapters.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the FIFO control section of the first embodiment. 3 and 4 are format diagrams of TBP and RBP. FIG. 5 is a block configuration diagram showing the configuration of the FIFO control section of the second embodiment. FIG. 6 is a block configuration diagram showing the configuration of the line adapter. 1... PIF, O control section, 2... Line adapter, 3
... line common control section, 4 ... interface control section (IFC), 5 ... buffer memory (BM), 6
...Microprocessor (MP), 11...Transmission FIFO memory, 12...Reception FFO memory, 13
...Bidirectional driver, 14...Status register (FSTR), 15...Register (LSTR), 1
6...Register (TBPR), 17...Register (
RBPR), 18... Control circuit, 19... Register (EOCR), 21... Input/output control circuit, 22...
・Write register, 22' ...Read register, 2
3... Interrupt control circuit, 24... Transmission/reception control circuit,
25... Transmission circuit, 26... Receiving circuit, 27...
Driver circuit, 28... Receiver circuit, 29... Peripheral input/output control circuit, 100... Processor bus, 20
0.300...database, 400.500...
Interrupt request line, 600... command write line for end of transmission, 700... internal data bus.

Claims (3)

[Claims] (1) Comprising line adapters (2-1 to 2-8) connected to each of a plurality of communication circuits, and a line common control unit (3) that sets a route between the host device and this line adapter. In the communication control device, a first memory (11) which is a first-in, first-out memory inserted in a transmission path between the line common control unit and the line adapter, and a first memory (11) between the line common control unit and the line adapter. A communication control device comprising: a second memory (12) which is a first-in, first-out memory inserted into a reception path of the device; and a control means for controlling the first and second memories. (2) The control means writes a predetermined number of characters of transmission data including a valid display flag for each character of the transmission data from the common control unit to the first memory, and writes the transmission data indicating that the validity flag is valid. means to transfer the received data character by character to the line adapter connected to this memory, and write the received data character by character to the second memory together with a valid display flag attached to each character of the received data, and and means for transmitting received data indicating that the valid display flag is valid character by character to the line common control unit when a predetermined number of characters are stacked in the second memory. The communication control device according to item 1). (3) The control means writes a predetermined number of characters of transmission data including one character of transmission control information from the line common control unit to the first memory, and writes one character of transmission data indicating that the transmission control information is valid. a means for transferring each character to a line adapter connected to this memory; and a means for writing received data character by character to the second memory, and when a predetermined number of characters are stacked in this second memory, one The communication control device according to claim 1, further comprising means for transferring received data including character reception control information to the line common control section.