JPS58120347A - Line adaptor - Google Patents

Abstract

PURPOSE:To improve the high speed of transmission data and the economy of the device, by avoiding a first-in first-out memory from being vacant, in a transmission line adaptor of a character buffer system. CONSTITUTION:A transmission character is given from a communication controller LC to a buffer register 1 and transmitted to a line while being sequentially stored in a first-in first-out memory 3. While the memory 3 is occupied, the buffer register 1 is vacant or the transmission character is set, after the required bit is subtracted by 1-bit, the transmission of the transmission data bit to the memory 3 is tentatively stopped, and when the memory 3 is vacant or the transmission character is set to the buffer register 3, a transmission control circuit 4 controls so that the transmission data bit is transferred to the memory 3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission line adapter using a character buffer method.

Generally, as a transmission data control method applied to a data communication system, a method is adopted in which a communication control device LC receives transmission data from a data processing device PU, decomposes it into pit serial data in a single line adapter LA, and then sends it out to a single line. has been done.

This system is schematically shown in Figure 1.

In this system, when the 9 communication control device LC receives a special transmission character, it may temporarily take a long time to process the transmission for that character. for example,
Addition of OLE when receiving DLE code in transparent transmission, ah. 6, in the case of generating a control field when receiving an address character in high data link control (HDLC) mode.

Even in such a case, the 2nd communication control device L is set so that the next character can be transmitted in time for the transmission speed of the
A two-line adapter with a plurality of character buffers provided, or a first-in/first-out shift memory provided with a two-line adapter that shortens the character processing time of C is being considered.

The method of shortening the character processing time has the disadvantage that if the transmission speed of one line is high, it becomes difficult to perform all the character processing in the nine communication control devices within the one character transmission time.

The method of providing a plurality of character buffers has the disadvantage that the circuit of the line adapter increases. For that reason, we are currently working as First In Faru. However, even if you use the first-in first-out shift ton mori, it will be 9
When there is not enough difference between the bit transmission speed of data sent to the line and the speed of data transferred from the shift register to the two-in/first-out shift memory.

Conventionally, when the transmit character buffer is empty, the first-in is used to prohibit input of transmit data bits from the transmit shift register to the first-in/first-out shift memory until a transmit character is set in the transmit character buffer from the communication control device. - There was a drawback that the first out shift memory lost the transmitted data.

An object of the present invention is to prevent the first-in first-out shift memory from becoming empty even when there is not a sufficient difference between the bit transmission speed of transmission data to one line and the speed at which the transmission data bits are stored in the first-in/first-out shift memory. To provide a line adapter for communication control that is capable of high-speed processing without causing problems.

According to the present invention, there are nine buffer registers that temporarily store transmission characters from a communication control device; a shift register that decomposes the transmission characters obtained from the buffer register into bit serials; and a first-in register that stores the output of the shift register. A first-out shift memory is provided, in which a transmission character is given to the buffer register from the communication control device, and is sequentially stored in the first-in/first-out shift memory via the shift register. Send the contents to the line, and check whether the first-in/first-out shift memory becomes "full" or not.
Alternatively, until the contents of the buffer register are transferred to the shift register and the buffer register becomes "empty" and a transmission character is set in the buffer register from the communication control device, the required number of bits minus 1 pit. and then temporarily suspending the transfer of the transmission data bits to the first-in/first-out shift memory;
Does the first-in/first-out shift memory become "empty"?

Alternatively, if a transmission character is set in the buffer register, a line adapter is obtained that controls the transmission data bits to be transferred to the first-in/first-out shift memory.

Next, 9 line adapters according to the present invention were conducted.

This will be explained in detail by giving an example and referring to nine drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment according to the present invention. In this figure, a transmission character from a communication controller 2 is received by a transmission buffer register 1. The transmission character of the transmission buffer register 1 is sent to the shift register 2, where it is decomposed into bit serial data, and then sent to the first-in/first-out shift memory 3. That is, as seen in the specific example of the first-in/first-out shift memory in FIG.
The transmission data accumulated in 1 is transferred to the next stage shift memory 3-2.
It will be moved there until it is empty. Thereafter, this transmission data is transferred to the n-th shift memory 3-n by the same operation.
move towards.

On the other hand, the contents of the first-in/first-out shift memory 3 are transmitted to the line under the control of the transmission control circuit 4 at a timing synchronized with the bit transmission rate of the line. Since the shift speed of first-in/first-out shift memories is usually faster than the bit transmission speed of a single line, transmission data is sequentially stored in these shift memories, and there are cases where there is no empty state in the shift memories. In such a case, the transmission control circuit 4 detects this state and prohibits the transfer of transmission data from the shift register 2 to the first-in/first-out shift memory 3 until the register becomes empty. Additionally, if the first-in/first-out shift memory 3 is empty and the transmission buffer register 1 is filled, the first-in/first-out shift memory
The contents of the shift register 2 are transferred to the first-out shift memory 3. Immediately after this, when the shift register 2 detects the completion of sending one character's worth of transmission data to the first-in/first-out shift register 3, the contents of the buffer register 1 are transferred to the shift register 2, and the first transmission character is transferred to the communication control device. The transmission control circuit 4 displays that the buffer register 1 is "empty" until it is set by the LC. The transmission control circuit 4 inhibits input of transmission data bits from the shift register 2 to the first-in/first-out shift memory 3 when the buffer register 1 is "empty" and the number of required bits minus one pit ff1K.

1 to explain the reason for prohibiting the input of transmission data bits to the first-in/first-out shift memory 3.
For example, the bit transmission rate of one line is 48 kbps, the speed of transferring transmission data bits from shift register 2 to first-in/first-out shift memory 3 is 64 kbps, the required number of bits is 8 bits, and buffer register 1 is "empty". 1 communication control device LC.
Assuming that the time it takes to set the transmission character in buffer register 1 is 10 μs, in the conventional method, 4
One character time is approximately 20.8μs at a speed of 8kbps
.

One character time is approximately 15.6 at a speed of 64 kbps.
It takes μs. From this, the buffer register 1 becomes "empty", the communication control device 9 sets the transmission character, and the transmission character currently set in the shift register 2 is transferred to the first-in/first-out shift memory 3. The time it takes for the transmission character to be transferred is approximately 25.6 μs, which is the time it takes for the communication control device to set the transmission character in the transmission buffer register and the time for one character at a speed of 64 kbps, which is the time for one character at a speed of 48 kbps. (approximately 20.8 μs) This is due to the existence of the first-in/first-out shift memory, even though the speed of input data is faster than the speed of output. This means that data cannot be stored in memory and not only cannot be saved from temporary peaks, but also cannot be transmitted at the bit rate of a single line even under normal conditions. On the other hand, according to the method of the present invention, under the above assumption, transmission data bits can be temporarily transferred from the shift register to the first-in/first-out shift memory in about 15.6 μs. Even if it is prohibited, it does not suffer from the drawbacks of the prior art.

Also, due to special character processing by communication control device 1, transmission characters from communication control device 9 cannot be sent on the line even if the buffer register is temporarily ``empty'' and the required number of bits minus 1 bit has passed. First in
The transmission data stored in the first-out shift register is transmitted correctly. Here, the reason why the elapsed time after the far register becomes empty is set as the required number of bits minus 1 bit is that the timing for transferring the transmission character from the buffer register to the shift register is automatically determined by the required number of bits. What to do.

Conventionally, the time it took for the buffer register to go from "full" to "empty" was the speed of transferring data from the shift register to the first-in/first-out shift memory x 8 pits (approximately 15.6 μs in the above example). This is to reduce the time to 1 pit (1.95 μs in the above example).

In the above embodiment, the first-in reference first-out shift memory is in an "empty" state.

Furthermore, if the shift register and buffer register are "empty", the transmitting side control circuit notifies the communication control device of the detection of an unrun error. First-in used
The pit capacity of the first outshift memory may be appropriately determined in relation to the difference between the pit transmission speed of one line and the processing speed of the communication control device.

As is clear from the above explanation, according to the present invention, the pit transmission speed and first-in speed of transmission data to the nine lines are
Even if the data speed stored in the first-out shift memory is not sufficiently different from the data speed, or even in normal cases, the first-in/first-out shift memory will not become empty, and the circuit configuration will be simplified. In terms of high speed of transmitted data and economy of equipment

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an outline of a general transmission data control method applied to conventional data communication systems, FIG. 2 is a blog diagram showing the configuration of an embodiment of the present invention, and FIG. FIG. 2 is a block diagram showing an example of the configuration of a first-in/first-out shift memory in FIG. In each figure, 1 is a buffer register for transmitting characters, 2 is a shift register for decomposing transmitting characters, 3 is a first-in/first-out shift memory, and 3-1 to
3-n each shift memory stage of the first-in/first-out shift memory. 4 is a transmission control circuit, PU is a data processing device, LC is a communication control device, and LA is a circuit adapter.

Claims (1)

[Claims] 18. A buffer register that temporarily stores transmission characters from a communication control device, a shift register that decomposes the transmission characters obtained from the buffer register into pid serial, and a first-in/first-out shift memory that stores the output of the shift register. 9. A transmission character is given to the buffer register from the communication control device, and the contents of the first-in/first-out shift memory are sent to the line while being sequentially stored in the first-in/first-out shift memory via the shift register. Then, either the first-in/first-out shift memory becomes "full" or the contents of the buffer register are transferred to the shift register, and the buffer register becomes "empty" and the communication control device Until the transmission character is set in the buffer or register, the transfer of the transmission data bits to the fast-in/first-out shift memory is temporarily stopped after the required number of pits minus 1 bit, and the transfer of the transmission data bits to the fast-in/first-out shift memory is suspended. Shift memory is "empty"
or when a transmission character is set in the buffer register, the line adapter controls to transfer transmission data bits to the first-in/first-out shift memory.