JPS5853255A - Circuit adaptor - Google Patents

Abstract

PURPOSE:To simplify the control for a bit buffer type circuit adaptor which stores the bit serial data in an FIFO shift memory and then transmits it, by storing the control signal of a MODEM, etc. into a bit buffer to perform a MODEM control. CONSTITUTION:A circuit adaptor LA holds a character (a) transmitted from a communication controller LC at a buffer register BFR and receives the control signal from a transmission control circuit CNT to transfer this signal to a shift register SFR. For the contents of the SFR, the character (a) is converted into a bit serial data (b) and stored in a first-in/first-out shift memory FIFO1 to be fed to a circuit. An external device controller DCEC stores the control signal (c) of the MODEM MD given from the controller LC into an FIFO2 and then feeds it to the MD synchronously with the transmission of the data (b). In such way, a control is possible so as to transmit the signal (c) of the MD at a time point when the data (b) corresponding to the character (a) given from the controller LC is transmitted from the register SFR.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a line adapter, and more particularly to a line adapter of a character buffer type in a communication control device and having a pit buffer.

Generally, a line adapter is connected to a data processing device via a communication control device when transmitting characters from the data processing device to the line.

FIG. 1 is a system configuration diagram of a data communication system including the present invention and a conventional line adapter.

As shown in FIG. 1, the communication control device LC receives transmission characters from the data processing device PU and connects the line adapter LA.
It decomposes it into P1-serial data and sends it to the line via modem MD.

Conventional line adapters convert transmission galactors into bit serial data using a shift register, store this data in a first-in-first-out shift memory, and sequentially output it to the line in synchronization with the transmission speed of the line.

In conventional line adapters such as , the control signals used to control the modem and the like directly output instructions from the higher-level communication control device.

For this reason, with conventional line adapters, if a control signal is supplied following the supply of transmission characters, at the end of transmission, even though data has accumulated in the pit buffer, the modem etc. is controlled to terminate transmission. There is a risk of doing so.

Therefore, since the control signal must be supplied to the line adapter after the bit serial data is output, it is necessary to control the modem and the like after confirming that all have been output.

For this reason, conventional line adapters differ in control between line adapters with pit buffers and line adapters with pit buffers. It is necessary to supply a control signal from a control device, which has the disadvantage of complicating control.

SUMMARY OF THE INVENTION An object of the present invention is to provide a line adapter that can perform the same control regardless of the presence or absence of a pit buffer, thereby simplifying the control.

That is, an object of the present invention is to provide a bit buffer type line adapter that stores bit serial data in a first-in-first-out shift memory and transmits the data.
To provide a line adapter and a control frame which can control a modem etc. in the same way as a line adapter which does not use a pit buffer by storing control signals of the modem etc. in a pit buffer.

The line adapter of the present invention includes a buffer register that holds transmission characters supplied from a communications system, a shift register that converts the transmission characters into bit serial data to generate bit serial data, and a shift register that converts the transmission characters into bit serial data to generate bit serial data. a first first-in-first-out shift memory that stores and outputs the data to the line in synchronization with the transmission speed of the line; and a first first-in-first-out shift memory that has the same configuration as the first first-in first-out shift memory and that transmits the data from the communication control device. and a second first-in-first-out shift memory which stores a control signal for controlling the modem supplied after the character is supplied and outputs it after the bit serial data is output.

In other words, the line adapter of the present invention includes a buffer register that holds transmission characters from a higher-level communication control device, a shift register that converts them into bit serial data, and a shift register that stores the outputs of the shift registers and synchronizes them with the transmission speed of the seven lines. A line adapter that has a first-in-first-out shift memory to output, a transmission control circuit to control these, and an external device control circuit to control and monitor modems, etc. stores the output of the shift register and synchronizes it with the transmission speed of the line. By providing a first-in-first-out shift memory that outputs data and a separate first-in-first-out shift memory that stores and sends control signals for the modem, etc., data on the line and control signals for the modem, etc. can be transferred to the communication control device. The configuration is made so that the timing is the same as the instruction from .

In other words, the line adapter of the present invention supports upper communication system #1.
A buffer register that holds the transmission characters sent from the device, a shift register that converts the characters into bit serial data, a transmission control circuit that controls these various registers, and an external device that monitors and controls the modem, etc. In a line adapter having a control circuit, the output of a shift register that converts to bit serial,
The control signals of the modem, etc. are stored in each first-in-first-out shift memory in synchronization with the transmission of bit-serial data, and these are output to the modem, etc. in synchronization with the transmission speed of the line. The control signal is configured to be synchronized with a control signal of a modem or the like.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

Line adapter LA shown in FIG. 2 is supplied with transmission character a from communication control device LC. This line adapter LA holds the transmission character a in the buffer register BFR, and transfers it to the shift register 5FR1 under control from the transmission control circuit CNTγ. The shift register SFR shifts the transmission character one bit at a time under the control of the transmission side circuit CNT to generate bit-serial data b.
Convert to This bit serial data b is the first-in first-out shift memo IJ F I F
It is stored in O1 and sent out to the line in synchronization with the transmission speed of the line.

The external device control circuit DCEC is instructed to control the modem MD by a control signal C from the communication control device &'LC, and outputs this as a control signal d to the modem MD.

Modem control signal transmission request) (The state of 7S is synchronized with the storage of bit-serial data in the first-in first-out shift memories F I and F 01 and is first-in-first-out shift similar to the first-in first-out shift memory t4 FIFOI. Memory F
Accumulate in IFO2. The control signal d is output to the modem MD in synchronization with the transmission of the bit serial data b to the line. The transmission request RS output to the modem MD is the transmission request R8 at the time when the 7-bit serial data b output to the ML at the same time is stored from the shift register SIi''Rμ to the first-in-first-out shift memo IJ F I F 01. be.

The status signal transmission enable C8 from the modem MD is input to the external device control circuit DCEC without going through the first-in-first-out shift memory.

In this way, the control signal C to be supplied to the modem MD is transferred to the first-in-first-out shift memory FIFO2'f.
Bit serial data b is output in correspondence with transmission character a from the higher-level communication control device LC by being transmitted as a control signal d to the modem MD.
It is possible to perform control such that the data is transmitted at the time when the signal is transmitted from the shift register SF'R of the line adapter LA.

Note that this is also possible at the same timing at the end of transmission.

By adding a second first-in-first-out shift memory having the same configuration as the first first-in-first-out shift memory that stores and outputs bit serial data to the line adapter of the present invention, the supply of control signals is possible. Since the signal supplied after outputting the bit serial data can be supplied to the supply edge of the transmission character, there is an effect that the signal for supplying the control signal can be simplified.

That is, the line adapter of the present invention stores control signals for the modem, etc., in the first-in-first-out shift memory, so that the line adapter is the same as a line adapter that does not have the first-in-first-out shift memory. l
This has the advantage that it is possible to perform i'l tflll.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data communication system including the present invention and a conventional line adapter, and FIG. 2 is a block diagram showing an embodiment of the present invention. P TJ −= =. Data processing equipment, LC/old...Communication control equipment, LA...Line adapter Mν'...
・・Buffer register, S]'i”It・・・Shift 1 register, CNT・・・Transmission control circuit, J)
C E C・・・External reinforcement” discount 1 circuit, FIF
OI, I"IFO2...First Infa9
- One strike out shift memory, a...Transmission character, b...Bit serial-101

Claims (1)

[Claims] A buffer register that holds transmission characters supplied from a communication control device, a shift register that converts the transmission characters into bit serial data and generates bit serial data, and a shift register that stores the bit serial data and synchronizes it with the transmission speed of the line. a first first-in-first-out shift memory that outputs the transmission character to the line; and a modem that has the same configuration as the first first-in-first-out shift memory and that is supplied after the transmission character is supplied from the communication control device. A second control signal that accumulates the final control signal and outputs it after outputting the bit serial data.
a first-in first-out shift memory;