JPS6070845A - Communication control equipment - Google Patents

Abstract

PURPOSE:To increase the hardware of a communication controller by inserting a temporary storage circuit of the required minimum degree of the first-in and first-out only to a character decomposing section. CONSTITUTION:The constitution of serial input data applied from a line is discriminated, a signal representing that input data to be transferred to a high-order device 1 is constituted is fed to a character decomposing control circuit 4 converting the data into serial output data to the line, and the transfer interval is prolonged by slowing down the transfer time of a parallel input data to the first-in first-output temporary storage circuit 2 from the high-order device than normal speed while the serial input data to be transferred to the high-order device 1 is constituted. The required time of parallel input data required by a character decomposing circuit 3 is delayed by slowing down the start time of character decomposition than normal time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication control device, and particularly to a communication control device in which a control signal on a receiving side is input to a control circuit on a transmitting side.

A conventional communication control device consists of a character decomposition part that converts parallel input data from a host device into serial output data to the 1-mail address, and a character assembly part that converts serial input data from a line into parallel output data to the host device. It consists of p, and character disassembly and assembly are processed independently and in parallel. However, if the processing capacity of the host device for data transfer is large, there is no problem, but if it is small, a first-in, first-out system is required in both the disassembly and assembly sections to prevent overrun and underrun errors. However, there was a drawback that the amount of hardware increased, which was difficult to deal with by inserting a temporary memory circuit or the like.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks by inserting the minimum required number of first-in, first-out temporary storage circuits only in the character decomposition section, and to provide communication control equipment that requires little increase in hardware.

According to the present invention, there is a character assembly circuit that receives bit serial input data from one line and converts it into parallel output data, and a character assembly circuit that receives the output of the character assembly circuit and transfers the data currently being assembled to a host device. a character assembly control circuit that performs control to determine whether or not the data is transferred to the host device, and a character assembly control circuit that performs data transfer control with the host device; and a character assembly control circuit that indicates that received characters are being assembled to ensure data transfer with the host device A character disassembly control circuit that controls the time at which transmission characters are transferred to the host device when a signal is received and the start time of decomposition of the data sent from the host device fk, and parallel input data from the host device is processed in a first-in, first-out manner. and a character decomposition circuit that decomposes parallel input data from the host device into bit-serial output data to the line, and the character assembly control circuit and the character assembly circuit decompose the parallel input data from the host device into bit serial output data. During the input of serial data that requires data transfer, the polarity of the signal line from the character assembly control circuit to the character disassembly control circuit is set to a positive state, and the character disassembly control circuit determines the migration of the character disassembly control circuit. A reverse communication control system is obtained, which is characterized in that it controls the transfer time of the transmitted characters to the character disassembly circuit and the start time of decomposition of the transmitted data to the character disassembly circuit.

Next, the present invention will be explained in detail with reference to the drawings.

The figure is a block diagram showing an embodiment of the communication control device of the present invention. In the figure, the communication control device connected to the host device b-1 includes a first-in, first-out temporary storage circuit 21, a character disassembly circuit 39, a character disassembly control circuit 4, a character assembly control circuit 5. It is configured to include a received character storage circuit 62 and a character assembly circuit 7.

The character assembly circuit 7 assembles the bit serial data input from the line through the connection line 17 into parallel data, and in the case of received data other than synchronous characters, it assembles the received data to the character assembly control circuit 5 via the connection line 19. Report completion. When the received character storage circuit 6 is instructed to accept data from the character assembly control circuit 5 via the connection line 20, it stores the received characters from the character assembly circuit 7 via the connection line 16. When the character assembly control circuit 5 receives a report of the completion of assembling the received data other than synchronous characters through the connection #j19, it instructs the host device 1 through the connection line 14 to take over and confirm the received characters. After this, the received character storage circuit 6 is instructed via the connection line 20 to output the received data to the connection line 15. The character decomposition control circuit 4 inquires of the host device 1 via the connection line 13 whether there is any data to be transmitted to the line, and the host device #1 inquires whether there is any data to be transmitted to the line, and if there is data to be transmitted for the alignment, the host device #1 A character transmission instruction is issued via the connecting line 13, and parallel data is placed on the connecting lineman 0. The first-in, first-out temporary storage circuit 2 receives data input/output instructions from the character separation control circuit 4 via the connection line 21, temporarily stores the transmission data input via the connection line 10 in a first-in, first-out manner, and stores the transmitted data in parallel on the connection line 11. Put it on. Until the character decomposition circuit 3 receives an instruction to start character decomposition from the character decomposition control circuit 4 via the connection line 22, the character decomposition circuit 3 converts synchronous characters into
Also, after receiving this instruction, the transmission data from the connection line 11 (
(parallel data) is decomposed into bit serial data and transmitted to the line via the connection line 12. The connection line 18 is a signal line that transmits a signal indicating that the character assembly circuit 7 is receiving data other than synchronous characters from the character assembly control circuit 5 to the character disassembly control circuit 4.

Next, the transition of the transmission/reception status of synchronization characters and data in this embodiment will be explained.

The character decomposition control circuit 4 learns the state of the character assembly control circuit 5 through the connection line 18, and thereby prevents overruns and underruns from occurring even if the host device 1 lacks processing capacity in accordance with the procedure described below. That is, when the character assembly control circuit 5 indicates a synchronous character reception state and there is a transmission instruction from the host device 1, the transmission data of several characters is sent at intervals equal to or less than the time required to transmit one character to the line. The data is stored in the first-in, first-out temporary storage circuit 2, and after the storage is completed, a transition is made to the data transmission state. Also, when the character assembly control circuit 5 indicates the data reception state, if there is a transmission instruction from the host device 1,
When it is safe to send several characters of data to a line +
'=" is stored in the first-in-first-out temporary storage circuit 2 at intervals several times as large as '=", and then the data is transferred to the data transmission state. A signal indicating that the input data to be processed is being assembled is supplied to the character decomposition control circuit 4, which transfers parallel input data from the host device 1 and converts it into serial output data to the line. During data assembly, the time for transferring parallel input data from the host device to the first-in, first-out temporary storage circuit 2 is delayed, thereby increasing the transfer interval.
In addition, by setting the start time of character decomposition later than usual, control is performed to delay the safe time of parallel input data, which the character decomposition circuit 3 can use, later than usual.

As is clear from the above explanation, according to the communication control device of the present invention, a temporary memory circuit of a first-in, first-out type with a minimum of peace of mind is inserted only in the character disassembly section, and the one-character assembly control circuit and the character assembly circuit are connected to the host device. By setting the polarity of the signal line from the character assembly control circuit to the AiJ character disassembly control circuit to a specific state during serial data input to ensure safe data transfer, the character disassembly control circuit determines the polarity and sends it to the host device. Since the transfer time of the parallel input data and the start time of character decomposition into the character decomposition circuit are controlled, there is an effect that hardware processing can be reduced.

[Brief explanation of drawings]

The figure is a block diagram showing an embodiment of the communication control device of the present invention.

Claims (1)

[Claims:] A character assembly circuit that receives bit serial input data from a line and converts it into parallel output data. a character assembly control circuit that receives the output of the character assembly circuit and performs control to determine whether or not the data currently being assembled should be transferred to a higher-level device and data transfer control with the higher-level device; When receiving a signal indicating that a received character that requires data transfer with a higher-level device is being assembled, the transfer display time of the transmitted character to the higher-level device and the start of disassembling the transmitted data from the higher-level device a character decomposition control circuit that controls time; a circuit that temporarily stores parallel input data from the host device on a first-in, first-out basis; and a character decomposition circuit that decomposes the parallel input data from the host device into serial output data to the line. the character assembly control circuit and the character assembly circuit specifying the polarity of a signal line from the character assembly control circuit to the character disassembly control circuit during serial data input that announces data transfer to the host device; By setting the character decomposition control circuit to the state, the character decomposition control circuit determines the polarity and controls the transfer dispersion time of the transmission character to the host device and the decomposition start time of the transmission data to the character decomposition circuit. Communication control device.