JPS63197132A - Data processing system - Google Patents

Abstract

PURPOSE:To prevent missing of data at production of a fault by outputting an enable signal in a faster timing than a timing reading a data from a buffer by a microprocessor unit to a terminal station equipment and writing a fault data into the buffer. CONSTITUTION:An MPU 1 of a PCM terminal station equipment and a terminal station equipment 9 are connected by a buffer register 20 to transmit/receive data DATAS or DATAR and an enable signal EN is outputted to the terminal equipment 9 in a timing faster than the clock timing to read the data by the microprocessor unit 1 from the buffer register through the additional circuit 10. That is, the microprocessor unit 1 sends the clock 2 advanced by an optional clock than the clock to read the data from the buffer register 20 from the circuit 10, it is detected by the MPU 1 in advance to send an enable EN signal, it is kept till the trailing of the next clock 1, a fault processing data by one byte is read completely, and sent to the terminal equipment 9 synchronously with a high speed clock 2. Thus, the loss of transmission data is prevented.

Description

[Detailed Description of the Invention] [Summary] When a PCM terminal device is provided with a terminal device and a microprocessor unit, and data transmission and reception of the terminal device is controlled by the microprocessor unit, data loss occurs when a failure occurs. In order to prevent this, a buffer is provided between the terminal device and the microprocessor unit, and an enable signal is output to the terminal device at a timing earlier than the timing at which the microprocessor unit reads data from the buffer, so that the faulty data is written to the buffer. This is what I did.

[Industrial application field]

FIG. 4 shows an overview of the system configuration of the PCM terminal equipment.

Conventionally, a centralized monitoring device 3 is installed in the PCM master station device in order to centralize monitoring of failures in the terminal device 9 in the PCM terminal device.
0 is installed, and the failure of each terminal device 9 is monitored in a polling or cyclic manner. When the number of terminal equipment is small, it is possible to quickly monitor faults in the centralized monitoring equipment, but as the number of terminal equipment increases, the range of centralized fault monitoring processing also expands, and failures in the terminal equipment become more difficult to monitor. A problem has arisen that requires time to understand the occurrence in a timely manner. Therefore, it has become necessary to increase the data transfer speed of failures in order to promptly respond to failures in terminal equipment.

On the other hand, with the miniaturization and increase in efficiency of microprocessors in PCM terminal equipment itself, a method has been adopted in which a microcomputer is built into the PCM terminal equipment to control transmission and reception in the terminal equipment. Here, a method has been adopted in which fault monitoring data is also serially inserted into the transmitted and received data to monitor the occurrence of faults in the terminal equipment. Therefore, if the grasp of fault monitoring data is delayed,
A situation has arisen in which the failure monitoring of the central monitoring device 30 is delayed, and the failure response of the terminal equipment is also delayed.

The present invention is a method for improving the timing of transmission and reception of faulty data between a terminal device and an MPU in order to speed up the serial transfer of faulty data within a PCM terminal device.

[Conventional technology]

MPU (microprocessor) of conventional PCM terminal equipment
FIG. 3(a) shows a block diagram and a transmission/reception timing chart between the terminal equipment and the terminal equipment.

Shown in (b).

DATAS also transfers data from MPUI to terminal equipment 9.
AT^'R indicates data from the terminal device 9 to the MPUI, which is serially transferred via the latch circuit 2, shift register 6 or shift register 7.3 state buffer 3, and is transferred in synchronization with the clock at 64. 1 byte (8 bits)
This shows the status of transmitting or receiving data. That is, 1 byte of data is sent from the falling edge of the clock at 8 to the next falling edge of the clock at 8. 8, the clock is sent from the terminal device 9 to the buffer register 20 and M
The clock is supplied to the PUI and monitored by the MPU.

[Problem that the invention seeks to solve]

By the way, if the falling edge of 8 is delayed, 1 byte of data is missing, and if this data is failure data, the failure monitoring data cannot be completely grasped, and it takes time until the next failure monitoring data is transferred. This has led to delays in troubleshooting.

In the present invention, when fault monitoring data is sent, the next fault monitoring data is reliably grasped so that one byte of data is not lost even if the falling edge of step 8 is delayed. This is a circuit system that allows failure processing to be performed without waiting until the data is transferred.

[Means for solving problems]

FIG. 1 shows a principle diagram of the PCM terminal equipment of the present invention. PC
The MPUI of the M terminal device and the terminal device 9 are connected by a buffer register 20, and the data DATAS or DATA
The additional circuit 10 outputs the enable signal BN to the terminal device 9 at a timing earlier than the clock for the microprocessor unit 1 to read data from the buffer register 20.

[Effect]

In the present invention, the microprocessor unit 1 from the additional circuit 10 sends out a clock 2 which is an arbitrary number of clocks ahead of the clock for reading data from the buffer register 20, which is detected in advance by the MPU 1 and sent out as an enable signal. The clock 1 is held until the next fall of the clock 1, and 1 byte of fault processing data is completely read and sent to the terminal device 9 in synchronization with the high speed clock 2.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2(a) shows a specific block diagram of a PCM terminal device according to an embodiment of the present invention, and FIG. 2(b) shows a transmission/reception timing chart between the MPU and the terminal device. show.

In FIG. 2(a), ■ indicates an MPU (microprocessor unit) for processing data of the terminal equipment, 2 and 5 are latch circuits, 3 is a three-state buffer, and 6, 7, and 8 are shift registers. , 9 indicates a PCM terminal device. Further, a circuit 10 surrounded by a dotted line is an additional circuit of the present invention, and 20 is a conventional shift register circuit. In this embodiment, the shift register 8 and latch circuit 5 are circuits added according to the present invention. In this circuit, shift register 6
A terminal Q of the shift register 7 is a data sending section to the terminal device 9, a terminal A of the shift register 7 is a data receiving section from the terminal device, and a terminal EN of the terminal device 9 is connected to the latch circuit 5.

In Fig. 2 <a) and (b), data for 1 byte (8 bits) starts to be sent from the falling edge of the clock at 8 to the next 8K, but due to the shift register 8, 2.5 Input the fast Q8K to MPU1. The MPU detects this and lowers the enable EN to 'L' (next 8, it lowers the enable EN to 'L' until the middle of the falling edge of the clock).
) and in the LD, the shift register 6 is the latch circuit 2
One byte worth of data stored in is read out and sent to the terminal device 9 in synchronization with the clock at 64.

Reception is the reverse operation of transmission, and like transmission, the rising edge of clock 98 is detected by MPtJl, and the enable signal EN is lowered before the falling edge of clock 98.

The device side 9 transmits one byte of data to the shift register 7 at the fall of the enable signal EN. The MPUI calculates the time from the next rising edge of 98 to the falling edge of 8, and reads the data.

〔Effect of the invention〕

According to the present invention, in order to increase the speed of MPU processing, the clock is used at 08, which is an arbitrary clock ahead of the clock at 8, and can be transmitted by the next clock at 8, thereby preventing the loss of transmitted data. Ensure that data on troubleshooting that can be prevented and that is urgent is understood.
It is possible to handle faster failure processing.

[Brief explanation of the drawing]

Figure 1 is a principle diagram of the PCM terminal equipment of the present invention, and Figure 2 (
a) and (b) are block diagrams and transmission/reception timing charts of the embodiment of the present invention, and FIGS.
b) shows a program diagram and a transmission/reception timing chart of the conventional example, and FIG. 4 shows a schematic diagram of the system configuration of the PCM terminal equipment. In the figure, 1 is an MPU, 2.5 is a latch circuit, 3 is a three-speed buffer, 6, 7.8 is a shift register, and 9 is a terminal device. Further, 10 indicates an additional circuit, 20 indicates a puffer register, and 30 indicates a central monitoring device. Fig. 1 is a principle diagram of the PCM terminal equipment of the present invention. Fig. 4 is a schematic diagram of the system configuration of the PCM terminal equipment.

Claims (1)

[Claims] In a data processing method in which data transmission and reception of a terminal device (9) is controlled by processing of a microprocessor unit (1), the timing of transmission and reception of faulty data in the terminal device (9) is fast. In order to achieve the
a buffer register (20) for latching data from the microprocessor unit (1), and an enable signal (E
A data processing method characterized in that an additional circuit (10) that outputs a signal (N) is provided, and data is written from the terminal device (9) to the buffer register (20) in response to the enable signal (EN).