CN114911736A - Master-slave machine system - Google Patents
Master-slave machine system Download PDFInfo
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- CN114911736A CN114911736A CN202210487355.2A CN202210487355A CN114911736A CN 114911736 A CN114911736 A CN 114911736A CN 202210487355 A CN202210487355 A CN 202210487355A CN 114911736 A CN114911736 A CN 114911736A
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- 230000005540 biological transmission Effects 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 abstract description 7
- 230000008023 solidification Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention discloses a master-slave machine system, which comprises a host, a plurality of slave machines, a clock line and a data line, wherein the host is provided with a data sending end, a data receiving end and a clock port; the data line is led out from the data sending end of the host, is connected to the data input end of the slave, is connected to the data input end of the next slave from the data output end of the slave, and is sequentially connected to the last slave in series. The system has high data transmission rate; the number of the used signal wires is small, and the wiring is simple; the pin configuration address, the software solidification address and the special address instruction sending distribution address are not needed; the method does not depend on the duration of high and low levels, does not need to set check bits for data packets, does not need a special coding mode, and reduces MCU resources.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a cascaded master-slave system.
Background
The data communication in the master-slave system can adopt a parallel communication bus or a serial communication bus, and the parallel communication bus has high transmission speed, but the number of signal lines is large, so that the wiring is not facilitated; the serial communication bus is adopted, the wiring is simple, but address information of the slave machines needs to be compiled, when the master machine is communicated with each slave machine, data sent by the master machine is output in a serial mode, the slave machines receive data corresponding to addresses of the slave machines according to different address information, at the moment, the addresses of the slave machines need to be solidified by software, or coding is carried out before communication, or IO pin configuration is adopted, so that the flexibility of the slave machines in a system is limited, the slave machines cannot be plugged and pulled out at any time, the slave machines are replaced, namely the addresses are accessed and distributed, and the serial communication bus is too dependent on the address information, so that the serial communication bus is not suitable for the plug-and-play slave machines. In addition, for a single bus, the coding form of data is complex, data 1 and data 0 depend on the lengths of high and low levels, the main control MCU occupies more resources when coding the data, the slave determines that the data is complex, and the transmission rate is low.
Disclosure of Invention
In order to overcome the defects, the invention provides a master-slave system, which comprises a master machine and a plurality of slave machines, wherein a data bus which can be used for cascade connection is adopted and comprises a clock line and a data line, the clock line is led out from a clock port of the master machine and is connected to a clock input end of each slave machine in parallel; the data line is led out from the data sending end of the host computer, is connected to the data input end of the slave computer, is connected to the data input end of the next slave computer through the data output end of the slave computer, and is sequentially connected to the last slave computer in series; the number of used signal wires is small, and the wiring is simple; the pin configuration address, the software solidification address and the special address instruction sending distribution address are not needed; the method does not depend on the duration of high and low levels, does not need to set check bits for data packets, does not need a special coding mode, and reduces MCU resources.
In order to achieve the purpose, the invention adopts the following technical scheme:
a master-slave machine system comprises a master machine, a plurality of slave machines, a clock line and a data line, wherein the master machine is provided with a data sending end, a data receiving end and a clock port, the slave machines are provided with a data input end, a data output end and a clock input end, and the clock line is led out from the clock port of the master machine and is connected to the clock input end of each slave machine in parallel; the data line is led out from a data sending end of the host, is connected to a data input end of the slave, is connected to a data input end of the next slave from a data output end of the slave, and is sequentially connected to the last slave in series. The invention provides a cascaded master-slave machine system, which comprises a master machine and a plurality of slave machines, wherein a data bus which can be used for cascading is adopted and comprises a clock line and a data line, the clock line is led out from a clock port of the master machine, the clock port (clock input end) of the slave machine is connected on the clock line in parallel, the data line is led out from a data sending end of the master machine, the data port (comprising a data input end and a data output end) of the slave machine is connected on the data line in series, and specifically, the clock line is led out from the clock port of the master machine and is connected to the clock input end of each slave machine in parallel; the data line is led out from the data sending end of the host machine, is connected to the data input end of the slave machine, is connected to the data input end of the next slave machine from the data output end of the slave machine, and is sequentially connected to the last slave machine in series, and the data output end of the last slave machine can be suspended or connected to the data receiving end of the host machine. The system adopts the data bus which can be used for cascade connection, not only ensures the rapid transmission of data, but also does not depend on the duration time of high and low levels, so that a series of data can be transmitted, the corresponding data can be processed according to the sequence accessed by the slave in the system, and the host can monitor the data passing through the slave, namely the host is allowed to receive and verify the data transmitted to the slave. The invention does not need pin configuration address, software solidified address, sending special address instruction to distribute address, the address is only determined according to the position of the slave in the system; the connection mode is simple, the transmission rate is high, and the reliability is high; the host is provided with a data receiving end, so that whether the data is correct or not can be monitored, check bits do not need to be set in data packets, a special coding mode is not needed, and the resources of the MCU are reduced.
Preferably, the data output end of the last slave is connected to the data receiving end of the master through a data line. The host is provided with a data receiving end, the data output end of the last slave is connected to the data receiving end of the host to monitor whether the data is correct, namely, the host is allowed to receive and check the data transmitted to the slave, so that a check bit is not required to be set in a data packet, a special coding mode is not required, and the resources of the MCU are reduced.
Preferably, the data output end of the last slave is suspended. The data output end of the last slave can be suspended except for being connected to the data receiving end of the host.
Preferably, the host comprises a data sending module and a host data decoding module. The data packet is sent out by a data sending module of the host through a data sending end; the host data decoding module checks whether the data in the data packet in the transmission process is correct or not according to the received data, and if the data in the data packet in the transmission process is incorrect, the data sending module resends the correct data of the current address.
Preferably, the slave includes a slave data decoding module. And a corresponding slave data decoding module is arranged in each slave and is used for identifying the address bit and the data bit of the data packet, processing the corresponding address information on the data line, and subtracting 1 from the addresses of other slaves to prepare for the next slave to process data. The transmitted data packet comprises N address bits and N data bits which are transmitted, the slave machine only determines the address according to the sequence in the access system, then processes the corresponding data, processes the address information of other slave machines at the same time, and does not process the data which does not belong to the slave machine.
Therefore, the invention has the advantages that:
(1) the data transmission rate is high, the reliability is high, the number of used signal lines is small, and the wiring is simple;
(2) the slave machine only determines the address according to the sequence in the access system without the need of pin configuration address, software solidification address and special address instruction distribution address transmission;
(3) the method does not depend on the duration of high and low levels, a data packet does not need to be provided with check bits, a special coding mode is not needed, and MCU resources are reduced.
Drawings
Fig. 1 is a schematic structural diagram of a master-slave system according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a host in an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a slave in the embodiment of the present invention.
1. The system comprises a host 2, a slave 3, a data sending module 4, a host data decoding module 5, a slave data decoding module 6, a clock line 7 and a data line.
Detailed Description
The invention is further described with reference to the following detailed description and accompanying drawings.
The first embodiment is as follows:
a master-slave machine system comprises a master machine 1, a plurality of slave machines 2, a clock line 6 and a data line 7, wherein the master machine 1 is provided with a data sending end, a data receiving end and a clock port, the slave machines 2 are provided with a data input end, a data output end and a clock input end, and the clock line 6 is led out from the clock port of the master machine 1 and is connected to the clock input end of each slave machine 2 in parallel; the data line 7 is led out from the data transmitting end of the master 1, connected to the data input end of the slave 2, connected to the data input end of the next slave 2 from the data output end of the slave 2, and sequentially connected to the last slave 2 in series. The embodiment provides a cascaded master-slave system, which comprises a master 1 and a plurality of slaves 2, as shown in fig. 2, the master 1 is provided with a data transmitting end, a data receiving end and a clock port, the master 1 is internally provided with a data transmitting module 3 and a master data decoding module 4, as shown in fig. 3, the slaves 2 are provided with a data input end, a data output end and a clock input end, and the slaves 2 are internally provided with slave data decoding modules 5, the system adopts a data bus which can be used for cascading, as shown in fig. 1, comprising a clock line 6 and a data line 7, the clock line 6 is led out from the clock port of the master 1, the clock port (clock input end) of the slave 2 is connected in parallel to the clock line 6, the data line 7 is led out from the data transmitting end of the master 1, the data ports (including the data input end and the data output end) of the slaves 2 are connected in series to the data line 7, specifically, a clock line 6 is led out from a clock port of the master machine 1 and is connected to a clock input end of each slave machine 2 in parallel; the data line 7 is led out from the data sending end of the host 1, connected to the data input end of the slave 2, connected to the data input end of the next slave 2 from the data output end of the slave 2, and sequentially connected to the last slave 2 in series, and the data output end of the last slave 2 may be suspended or connected to the data receiving end of the host 1.
Example two:
a master-slave machine system is shown in figure 1 and comprises a master machine 1, a 0# slave machine and a 1# slave machine … N # slave machine, wherein the clock input end of each slave machine 2 is connected to the clock line 6 of the master machine 1 in parallel, a data line 7 is connected to the data input end of the 0# slave machine from the data transmitting end of the master machine 1, is led out from the data output end of the 0# slave machine, is connected to the data input end of the 1# slave machine and is sequentially connected, and the data output end of the last slave machine (N # slave machine) can be connected to the data receiving end of the master machine 1 or can be suspended.
The data packet is sent by a data sending module of a host computer through a data sending end according to a corresponding communication protocol, the first sent data is data operated on a 0# slave computer, the data format is that a first Byte is a start bit, a second Byte is an address bit, a third Byte is a high 8 bit of the data length, a fourth Byte is a low 8 bit of the data length, and the next N bytes are a data bit and a check bit; the data to be sent is data operated on a 1# slave, the data format is that the first Byte is a start bit, the second Byte is an address bit, the third Byte is the upper 8 bits of the data length, the fourth Byte is the lower 8 bits of the data length, the next N bytes are data bits and check bits, and so on.
The slave data decoding module of the 0# slave detects data at the data input end, identifies a start bit, and starts to judge whether the data which is next to the start bit is the data corresponding to the slave or the data of other slaves according to the address bit, if the data is the data of the slave, the corresponding data is processed according to the data length, if the data is the data of other slaves, the addresses in the serial data packet sent by the master data sending module are all reduced by 1, and the data are sequentially sent from the data output end of the 0# slave.
The slave data decoding module of the 1# slave detects the start bit and operates as the slave data decoding module of the 0# slave.
The data decoding module of the N # slave detects the start bit, and the data output end of the N # slave can also be suspended in the same operation as the slave data decoding module of the 0# slave. When the data output end of the N # slave machine is connected to the data receiving end of the host machine, the host machine data decoding module of the host machine checks whether the data in the data packet in the transmission process is correct or not according to the received data, and if the data in the data packet is incorrect, the data sending module of the host machine resends the correct data of the current address.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (6)
1. A master-slave machine system is characterized by comprising a master machine, a plurality of slave machines, a clock line and a data line, wherein the master machine is provided with a data sending end, a data receiving end and a clock port; the data line is led out from a data sending end of the host, is connected to a data input end of the slave, is connected to a data input end of the next slave from a data output end of the slave, and is sequentially connected to the last slave in series.
2. A master-slave system according to claim 1, wherein the data output of the last slave is connected to the data receiving end of the master via a data line.
3. A master-slave system according to claim 1, wherein the data output of the last slave is floating.
4. A master-slave system according to claim 1, wherein the master comprises a data transmission module and a master data decoding module.
5. The master-slave system according to claim 1, wherein the slave comprises a slave data decoding module.
6. A master-slave system according to claim 5, wherein the slave data decoding module is adapted to identify data belonging to the slave's own address.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210487355.2A CN114911736A (en) | 2022-05-06 | 2022-05-06 | Master-slave machine system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210487355.2A CN114911736A (en) | 2022-05-06 | 2022-05-06 | Master-slave machine system |
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| CN114911736A true CN114911736A (en) | 2022-08-16 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103454996A (en) * | 2013-08-23 | 2013-12-18 | 广州视睿电子科技有限公司 | Master-slave computer system and control method thereof |
| CN113572674A (en) * | 2021-09-26 | 2021-10-29 | 北京芯格诺微电子有限公司 | Chain connection communication method of single-wire bus |
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- 2022-05-06 CN CN202210487355.2A patent/CN114911736A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103454996A (en) * | 2013-08-23 | 2013-12-18 | 广州视睿电子科技有限公司 | Master-slave computer system and control method thereof |
| CN113572674A (en) * | 2021-09-26 | 2021-10-29 | 北京芯格诺微电子有限公司 | Chain connection communication method of single-wire bus |
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