CN112800001A

CN112800001A - High-performance Internet of things hardware platform and method based on ARM platform architecture

Info

Publication number: CN112800001A
Application number: CN202110391603.9A
Authority: CN
Inventors: 陈先良; 周玲; 冯志刚; 刘喜峰
Original assignee: Beijing Leyan Technology Co ltd
Current assignee: Beijing Leyan Technology Co.,Ltd.
Priority date: 2021-04-13
Filing date: 2021-04-13
Publication date: 2021-05-14
Anticipated expiration: 2041-04-13
Also published as: CN112800001B

Abstract

The invention provides a high-performance Internet of things hardware platform and a method based on an ARM platform architecture. The scheme comprises a CN9130 chip, a first type interface, a first Switch chip, a second type interface, a MCI interface, a 88F8215 bridge chip, an SPI interface, a NOR FLASH chip, a first 1G SERDES interface, a second 1G SERDES interface, a 10G SERDES interface and a second Switch chip, wherein the CN9130 chip is provided with the first type interface, an interface communicated with the first Switch chip, the second type interface and the MCI interface, the MCI interface is electrically connected with the 88F8215 bridge chip, and the 88F8215 bridge chip is provided with the SPI interface, an interface used for communicating with the NOR FLASH chip, the first 1G SERDES interface, the second 1G SERDES interface, the 10G SERDES interface and an interface used for communicating with the second Switch chip. According to the scheme, by setting multi-level interface communication expansion and combining a transmission working method of classification, higher transmission efficiency and lower load rate can be realized.

Description

High-performance Internet of things hardware platform and method based on ARM platform architecture

Technical Field

The invention relates to the technical field of electronic circuit products, in particular to a high-performance Internet of things hardware platform and a method based on an ARM platform architecture.

Background

The internet of things is used for acquiring any object or process needing monitoring, connection and interaction in real time and acquiring various required information of sound, light, heat, electricity, mechanics, chemistry, biology, position and the like through various devices and technologies such as various information sensors, radio frequency identification technologies, global positioning systems, infrared sensors, laser scanners and the like. With the continuous development of power electronic technology, the transmission speed and the transmission capacity of electronic equipment are also continuously upgraded, the performance requirements of a control chip used in the internet of things are also continuously upgraded, and the hardware design of the internet of things is performed by using an ARM platform, so that the low cost and the high efficiency are the current mainstream mode.

However, the existing hardware architecture scheme of the internet of things based on the ARM platform architecture has the following defects: although the cost is low, the number of external interfaces expanded at the same time is relatively small, and the total data transmission amount of the internet of things is directly influenced by communication interfaces such as gigabit network ports and optical ports. In addition, the problem of transmission efficiency needs to be overcome when the transmission capacity is expanded, the resource load rate of the ARM chip is ensured to be at a lower level, and the safe and stable operation of the equipment is ensured.

Disclosure of Invention

In view of the above problems, the invention provides a high-performance internet of things hardware platform based on an ARM platform architecture and a method thereof, which can realize higher transmission efficiency and lower load rate by setting multi-level interface communication extension and combining a transmission working method of classification.

According to the first aspect of the embodiment of the invention, a high-performance Internet of things hardware platform based on an ARM platform architecture is provided.

The high-performance Internet of things hardware platform based on the ARM platform architecture comprises a CN9130 chip, a first interface, a first Switch chip, a second interface, an MCI interface, an 88F8215 bridge chip, an SPI interface, a NOR FLASH chip, a first 1G SERDES interface, a second 1G SERDES interface, a 10G SERDES interface and a second Switch chip, wherein the first interface, an interface communicated with the first Switch chip, the second interface and the MCI interface are arranged on the CN9130 chip, the MCI interface is electrically connected with the 88F8215 bridge chip, the 88F8215 bridge chip is provided with the SPI interface, an interface used for communicating with the FLASH NOR chip, the first 1G SERDES interface, the second 1G SERDES interface, the 10G SERDES interface and an interface used for communicating with the second Switch chip, and the first Switch chip is in communication with 2 SFP + megawatt communication interfaces, 8 RJ45 gigabit net ports are electrically connected.

In one or more embodiments, preferably, the second Switch chip is electrically connected to 2 SFP + tera optical communication interfaces and 6 RJ45 gigabit ports.

In one or more embodiments, preferably, the SERDES interface of the first 1G and the SERDES interface of the second 1G are electrically connected to 1 RJ45 kilo optical communication interface, respectively.

In one or more embodiments, preferably, the first type of interface includes 1 UDIMM memory slot supporting DDR4, 1 embedded memory of 8GB, 2 XFI interfaces of 10G, 1 USB2.0 interface, 1 USB3.0 interface, 1 COM debug interface, 1 RS485 interface, 1 RS232 interface, 8 GPIO interfaces, and 2 SATA interfaces.

In one or more embodiments, preferably, the second type interface is electrically connected with 8 RJ45 interface gigabit ports and 2 SFP + interface gigabit ports.

According to a second aspect of the embodiment of the invention, a working method of a high-performance internet of things hardware platform based on an ARM platform architecture is provided.

The working method of the high-performance Internet of things hardware platform based on the ARM platform architecture specifically comprises the following steps:

reading first query data, second query data and third query data by using the CN9130 chip;

acquiring a transmission data type according to the first query data, and storing the transmission data type as a transmission data header;

acquiring a data transmission protocol type according to the second query data, and storing the data as the internet of things data after protocol conversion;

and acquiring a data sending interface according to the third query data, and sending the Internet of things data after protocol conversion and the transmission data head from the data sending interface.

In one or more embodiments, preferably, the reading, by using the CN9130 chip, the first query data, the second query data, and the third query data specifically includes:

reading received internet of things data by using the CN9130 chip, wherein the internet of things data comprises a data header, a data protocol identifier, a layered code and internet of things transmission data;

acquiring a data head in the data of the Internet of things and storing the data head as the first query data;

acquiring a data protocol identifier in the data of the internet of things, and storing the data protocol identifier as the second query data;

and acquiring layered codes in the data of the Internet of things, and storing the layered codes as the third query data.

In one or more embodiments, preferably, the obtaining a transmission data type according to the first query data and storing the transmission data type as a transmission data header specifically includes:

the CN9130 chip reads a data mapping table in the memory, wherein the data mapping table comprises a data header mapping table, a data protocol mapping table and a layered coding relationship;

inquiring the data head mapping table by using the first inquiry data to obtain the transmission data type;

and saving the transmission data type as the transmission data header.

In one or more embodiments, preferably, the obtaining a data transmission protocol type according to the second query data, and storing the data as the internet of things data after protocol conversion specifically includes:

inquiring the data protocol mapping table by using the second inquiry data to obtain the data transmission protocol type;

and performing data conversion according to the type of the data transmission protocol, and storing the data as the Internet of things data after protocol conversion.

In one or more embodiments, preferably, the obtaining a data sending interface according to the third query data, and sending the internet of things data converted by the protocol and the transmission data header from the data sending interface includes:

querying the hierarchical coding relationship by using the third query data to obtain the data sending interface, where the data sending interface includes one or more interfaces of the first class interface, the first Switch chip, the second class interface, the MCI interface, the 88F8215 bridge chip, the SPI interface, the NOR FLASH chip, the SERDES interface of the first 1G, the SERDES interface of the second 1G, the SERDES interface of the 10G, the second Switch chip, the XFI interfaces of 2 10G, the 1 USB2.0 interface, the 1 USB3.0 interface, the 1 COM debugging interface, the 1 RS485 interface, the 1 RS232 interface, the 8 GPIO interfaces, and the 2 SATA interfaces;

and transmitting the Internet of things data converted by the protocol and the transmission data head through the data transmitting interface according to a preset sequence.

The technical scheme provided by the embodiment of the invention can have the following beneficial effects:

1) the embodiment of the invention improves the peripheral data transmission capability of the original CN9130 chip by connecting the 88F8215 bridge chip through the MCI interface, improves the number of the optical communication interfaces and the network communication interfaces of the peripheral and improves the original communication speed.

2) According to the embodiment of the invention, by setting the corresponding working method, the time for data query, protocol conversion and data transmission is reduced in the data communication process of the Internet of things, the efficiency of single data processing is improved while the communication data interface is improved, and the load rate of a CN9130 chip is reduced.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a structural diagram of a high-performance internet of things hardware platform based on an ARM platform architecture according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a hardware architecture of a high-performance internet of things hardware platform based on an ARM platform architecture according to an embodiment of the present invention.

Fig. 3 is a flowchart of a working method of a high-performance internet of things hardware platform based on an ARM platform architecture according to an embodiment of the present invention.

Fig. 4 is a flowchart of reading first query data, second query data, and third query data by using the CN9130 chip in the working method of the high-performance internet of things hardware platform based on the ARM platform architecture according to an embodiment of the present invention.

Fig. 5 is a flowchart of obtaining a transmission data type according to the first query data and storing the transmission data type as a transmission data header in the working method of the high-performance internet of things hardware platform based on the ARM platform architecture according to an embodiment of the present invention.

Fig. 6 is a flowchart of obtaining a data transmission protocol type according to the second query data and storing the data as the internet of things data after protocol conversion in the working method of the high-performance internet of things hardware platform based on the ARM platform architecture according to an embodiment of the present invention.

Fig. 7 is a flowchart of obtaining a data sending interface according to the third query data, and sending the internet of things data after the protocol conversion and the transmission data header from the data sending interface in the working method of the high-performance internet of things hardware platform based on the ARM platform architecture according to an embodiment of the present invention.

Detailed Description

In some of the flows described in the present specification and claims and in the above figures, a number of operations are included that occur in a particular order, but it should be clearly understood that these operations may be performed out of order or in parallel as they occur herein, with the order of the operations being indicated as 101, 102, etc. merely to distinguish between the various operations, and the order of the operations by themselves does not represent any order of performance. Additionally, the flows may include more or fewer operations, and the operations may be performed sequentially or in parallel. It should be noted that, the descriptions of "first", "second", etc. in this document are used for distinguishing different messages, devices, modules, etc., and do not represent a sequential order, nor limit the types of "first" and "second" to be different.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The internet of things is used for acquiring any object or process needing monitoring, connection and interaction in real time and acquiring various required information of sound, light, heat, electricity, mechanics, chemistry, biology, position and the like through various devices and technologies such as various information sensors, radio frequency identification technologies, global positioning systems, infrared sensors, laser scanners and the like. With the continuous development of power electronic technology, the transmission speed and transmission capacity of electronic equipment are also continuously upgraded, and the performance requirements of control chips used in the internet of things are also continuously upgraded. The hardware design of the internet of things is carried out by utilizing the ARM platform, so that the current mainstream mode is low in cost and high in efficiency.

However, the existing hardware architecture scheme of the internet of things based on the ARM platform architecture has the following defects: although the cost is low, the number of the external interfaces expanded at the same time is relatively small, the total data transmission amount of the internet of things is directly influenced by communication interfaces such as a gigabit network port and an optical port, in addition, the difficult problem of transmission efficiency needs to be overcome when the transmission capacity is expanded, the resource load rate of an ARM chip is ensured to be at a low level, and the safe and stable operation of equipment is ensured.

The embodiment of the invention provides a high-performance Internet of things hardware platform and a method based on an ARM platform architecture. According to the scheme, by setting multi-level interface communication expansion and combining a transmission working method of classification, higher transmission efficiency and lower load rate can be realized.

In a first aspect of the embodiments of the present invention, a high-performance internet of things hardware platform based on an ARM platform architecture is provided.

As shown in fig. 1, in one or more embodiments, preferably, the high-performance internet of things hardware platform based on the ARM platform architecture includes: CN9130 chip 101, first interface 102, first Switch chip 103, second interface 104, MCI interface 105, 88F8215 bridge 106, SPI interface 107, NOR FLASH chip 108, first 1G SERDES interface 109, second

1G SERDES interface

110, 10G SERDES interface 111, and second Switch chip 112, wherein the CN9130 chip 101 is provided with the first interface 102, an interface for communicating with the first Switch chip 103, the second interface 104, and the MCI interface 105, the MCI interface 105 is electrically connected with the 88F8215 bridge 106, the 88F8215 bridge 106 is provided with the SPI interface 107, an interface for communicating with the NOR FLASH chip 108, the first 1G SERDES interface 109, the second 1G SERDES interface 110, the 10G SERDES interface 111, and a des interface for communicating with the second Switch chip 112, the first Switch chip 103 is in communication with the SFP chip + SFP chip 112, and the first Switch chip 103 is in communication with the SFP chip + SFP chip 112 8 RJ45 gigabit net ports are electrically connected.

The SERDES is an abbreviation of an english SERializer, and is a mainstream time division multiplexing and point-to-point serial communication technology. That is, at the transmitting end, the multi-path low-speed parallel signals are converted into high-speed serial signals, and finally, at the receiving end, the high-speed serial signals are converted into low-speed parallel signals again through the transmission medium. The point-to-point serial communication technology fully utilizes the channel capacity of a transmission medium, reduces the number of required transmission channels and device pins, and improves the transmission speed of signals, thereby greatly reducing the communication cost.

In the embodiment of the invention, data transmission and processing of the first type interface and the second type interface are firstly carried out through the CN9130 chip, and in addition, in order to expand more interfaces and carry out data transmission on data of the CN9130 chip through the 88F8215 bridge chip through the MCI interface, on one hand, the number of optical communication interfaces is expanded, on the other hand, the number of network communication interfaces is also expanded, and meanwhile, the CN9130 chip is ensured not to waste resources.

As shown in fig. 2, in one or more embodiments, the second Switch chip 112 is preferably electrically connected to 2 SFP + tera optical communication interfaces and 6 RJ45 gigabit ports.

In the embodiment of the invention, 2 trillion optical communication interfaces and 6 giga Ethernet communication interfaces perform data interaction with the 88F8215 bridge chip through the second SWITCH chip, so that the 88F8215 external data transmission interfaces are further enriched.

In one or more embodiments, preferably, the SERDES interface 109 of the first 1G and the SERDES interface 110 of the second 1G are electrically connected to 1 RJ45 kilo optical communication interface, respectively.

In the embodiment of the invention, 2 gigabit communication structures are connected with 2 1G SERDES interfaces, so that all 88F8215 bridge chip peripheral communication interfaces can be completely utilized.

In one or more embodiments, preferably, the first type interface 102 includes 1 UDIMM memory slot supporting DDR4, 1 embedded memory of 8GB, 2 XFI interfaces of 10G, 1 USB2.0 interface, 1 USB3.0 interface, 1 COM debug interface, 1 RS485 interface, 1 RS232 interface, 8 GPIO interfaces, and 2 SATA interfaces.

In the embodiment of the invention, 1 UDIMM memory slot supporting DDR4 and 1 embedded memory of 8GB are arranged for the CN9130 chip; 2 XFI interface, 1 USB2.0 interface, 1 USB3.0 interface, 1 COM debug interface, a series of interfaces such as RS485 interface of 10G, guaranteed that the peripheral interface of CN9130 chip is sufficient on the one hand, on the other hand, also guaranteed that CN9130 chip does not appear the waste of resource.

In one or more embodiments, the second type interface 104 is preferably electrically connected to 8 RJ45 interface gigabit ports and 2 SFP + interface gigabit ports.

In the embodiment of the invention, the first Switch chip is accessed with 8 gigabit network ports of RJ45 interfaces and 2 gigabit network ports of SFP interfaces, so that the transmission efficiency and the transmission total amount of the peripheral interfaces of the whole CN9130 chip are further improved.

In a second aspect of the embodiments of the present invention, a working method of a high-performance internet of things hardware platform based on an ARM platform architecture is provided.

As shown in fig. 3, in one or more embodiments, preferably, the working method of the high-performance internet of things hardware platform based on the ARM platform architecture includes:

s301, reading first query data, second query data and third query data by using the CN9130 chip 101;

s302, acquiring a transmission data type according to the first query data, and storing the transmission data type as a transmission data header;

s303, acquiring a data transmission protocol type according to the second query data, and storing the data as the Internet of things data after protocol conversion;

s304, obtaining a data sending-out interface according to the third query data, and sending the Internet of things data after protocol conversion and the transmission data head out of the data sending-out interface.

In the embodiment of the invention, data query is carried out according to the CN9130 chip, a transmission data header is obtained in a data mapping mode, data protocol conversion is carried out, and data of the Internet of things are transmitted to a corresponding preset transmission interface for data transmission.

As shown in fig. 4, in one or more embodiments, preferably, the reading, by using the CN9130 chip 101, the first query data, the second query data, and the third query data specifically includes:

s401, reading received Internet of things data by using the CN9130 chip 101, wherein the Internet of things data comprises a data header, a data protocol identifier, layered codes and Internet of things transmission data;

s402, acquiring a data header in the Internet of things data, and storing the data header as the first query data;

s403, acquiring a data protocol identifier in the data of the Internet of things, and storing the data protocol identifier as the second query data;

s404, acquiring the hierarchical codes in the data of the Internet of things, and storing the hierarchical codes as the third query data.

In the embodiment of the invention, the data is classified and inquired firstly, and the data is stored as three different types of inquiry data including the first inquiry data, the second inquiry data and the third inquiry data, thereby laying a foundation for later data analysis and transmission.

As shown in fig. 5, in one or more embodiments, preferably, the obtaining a transmission data type according to the first query data, and storing the transmission data type as a transmission data header specifically includes:

s501, reading a data mapping table in a memory by the CN9130 chip 101, wherein the data mapping table comprises a data header mapping table, a data protocol mapping table and a hierarchical coding relationship;

s502, inquiring the data head mapping table by using the first inquiry data to obtain the transmission data type;

s503, saving the transmission data type as the transmission data header.

In the embodiment of the invention, a data table preset in the memory is further inquired aiming at the first inquiry data, and the data transmission type can be rapidly acquired through the table and is used as a data head when the data is sent.

As shown in fig. 6, in one or more embodiments, preferably, the obtaining a data transmission protocol type according to the second query data, and storing the data as the internet of things data after protocol conversion specifically includes:

s601, the CN9130 chip 101 reads a data mapping table in a memory, wherein the data mapping table comprises a data header mapping table, a data protocol mapping table and a hierarchical coding relationship;

s602, querying the data protocol mapping table by using the second query data to obtain the data transmission protocol type;

and S603, converting data according to the type of the data transmission protocol, and storing the converted data as the Internet of things data.

In the embodiment of the invention, a table of a data protocol preset in the memory is further queried aiming at the second query data, and the table can quickly realize the conversion of the data protocol and convert the corresponding data of the internet of things into the required data type.

As shown in fig. 7, in one or more embodiments, preferably, the obtaining a data sending interface according to the third query data, and sending the internet of things data after protocol conversion and the transmission data header from the data sending interface specifically includes:

s701, reading a data mapping table in a memory by the CN9130 chip 101, wherein the data mapping table comprises a data header mapping table, a data protocol mapping table and a hierarchical coding relationship;

s702, querying the hierarchical coding relationship by using the third query data, and obtaining the data sending interface, where the data sending interface includes one or more interfaces of the first type interface 102, the first Switch chip 103, the second type interface 104, the MCI interface 105, the 88F8215 bridge 106, the SPI interface 107, the NOR FLASH chip 108, the first 1G SERDES interface 109, the second 1G SERDES interface 110, the 10G SERDES interface 111, the second Switch chip 112, the 2 10G XFI interfaces, the 1 USB2.0 interface, the 1 USB3.0 interface, the 1 COM debugging interface, the 1 RS485 interface, the 1 RS232 interface, the 8 GPIO interfaces, and the 2 SATA interfaces;

and S703, transmitting the Internet of things data converted by the protocol and the transmission data head through the data transmitting interface according to a preset sequence.

In the embodiment of the invention, a data sending interface table preset in the memory is further inquired aiming at the third inquired data, and the data can be quickly sent out from the interface of the hardware platform of the internet of things through the table, so that the conversion, inquiry and data sending of all the data of the internet of things are quickly realized, and the occupation of memory resources is reduced.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. The utility model provides a high performance thing networking hardware platform based on ARM platform architecture which characterized in that includes: a CN9130 chip (101), a first interface (102), a first Switch chip (103), a second interface (104), an MCI interface (105), an 88F8215 bridge (106), an SPI interface (107), a NOR FLASH chip (108), a first 1G SERDES interface (109), a second 1G SERDES interface (110), a 10G SERDES interface (111), and a second Switch chip (112), wherein the CN9130 chip (101) is provided with the first interface (102), an interface communicating with the first Switch chip (103), the second interface (104), and the MCI interface (105), the MCI interface (105) is electrically connected with the 88F8215 bridge (106), the 88F8215 bridge (106) is provided with the NOR interface (107), an interface communicating with the FLASH chip (108), the first 1G SERDES interface (109), and the second 1G SERDES interface (110), The SERDES interface (111) of 10G, the interface that is used for communicating with the second Switch chip (112), the first Switch chip (103) with 2 SFP + tera optical communication interface, 8 RJ45 giga net mouths electricity connect.

2. The ARM platform architecture based high performance Internet of things hardware platform as claimed in claim 1, wherein the second Switch chip (112) is electrically connected to 2 SFP + tera optical communication interfaces and 6 RJ45 gigabit ports.

3. The ARM platform architecture-based high-performance Internet of things hardware platform as claimed in claim 1, wherein the SERDES interface (109) of the first 1G and the SERDES interface (110) of the second 1G are electrically connected to 1 RJ45 kilo optical communication interface respectively.

4. The ARM platform architecture-based high-performance Internet of things hardware platform is characterized in that the first type of interface (102) comprises 1 UDIMM memory slot supporting DDR4, 1 embedded memory of 8GB, 2 XFI interfaces of 10G, 1 USB2.0 interface, 1 USB3.0 interface, 1 COM debugging interface, 1 RS485 interface, 1 RS232 interface, 8 GPIO interfaces and 2 SATA interfaces.

5. The ARM platform architecture-based high-performance Internet of things hardware platform is characterized in that the second type of interface (104) is electrically connected with 8 RJ45 interface gigabit ports and 2 SFP + interface gigabit ports.

6. An operation method of the hardware platform of the high-performance internet of things based on the ARM platform architecture, according to claim 4, is characterized in that the operation method includes:

reading first query data, second query data and third query data by using the CN9130 chip (101);

7. The working method of the ARM platform architecture-based high-performance internet-of-things hardware platform according to claim 6, wherein the reading of the first query data, the second query data, and the third query data by using the CN9130 chip (101) specifically includes:

reading received internet of things data by using the CN9130 chip (101), wherein the internet of things data comprises a data header, a data protocol identifier, layered codes and internet of things transmission data;

8. The working method of the ARM platform architecture-based high-performance internet-of-things hardware platform of claim 6, wherein the obtaining of the type of the transmission data according to the first query data and saving as the transmission data header specifically comprises:

the CN9130 chip (101) reads a data mapping table in the memory, wherein the data mapping table comprises a data header mapping table, a data protocol mapping table and a hierarchical coding relationship;

and saving the transmission data type as the transmission data header.

9. The working method of the ARM platform architecture-based high-performance internet-of-things hardware platform of claim 6, wherein the obtaining of the data transmission protocol type according to the second query data and storing as the protocol-converted internet-of-things data specifically comprises:

10. The method for operating the high-performance internet of things hardware platform based on the ARM platform architecture of claim 6, wherein the obtaining of the data sending interface according to the third query data and the sending of the internet of things data converted by the protocol and the transmission data header from the data sending interface specifically include:

querying the hierarchical coding relationship by using the third query data to obtain the data sending interface, where the data sending interface includes one or more interfaces among the first class interface (102), the first Switch chip (103), the second class interface (104), the MCI interface (105), the 88F8215 bridge chip (106), the SPI interface (107), the NOR FLASH chip (108), the first 1G SERDES interface (109), the second 1G SERDES interface (110), the 10G SERDES interface (111), the second Switch chip (112), the 2 10G XFI interfaces, the 1 USB2.0 interface, the 1 GPIO 3.0 interface, the 1 COM debugging interface, the 1 RS485 interface, the 1 RS232 interface, the 8 SATA interfaces, and the 2 SATA interfaces;