CN203658995U - Serial data transmission system - Google Patents
Serial data transmission system Download PDFInfo
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- CN203658995U CN203658995U CN201320877596.4U CN201320877596U CN203658995U CN 203658995 U CN203658995 U CN 203658995U CN 201320877596 U CN201320877596 U CN 201320877596U CN 203658995 U CN203658995 U CN 203658995U
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Abstract
The utility model discloses a serial data transmission system comprising a host and a plurality of slave computers. The host comprises a main serial transceiver, a main CRC checker, a bus controller and a main memory all connected in a serial way, wherein each slave computer is formed by a slave serial transceiver, a slave CRC checker, a data processor and a slave memory; the main serial transceiver is connected with the slave serial transceivers via data bus in a serial bus; and the bus controller enables a signal line and a wrong signal line to be connected with the data processors via an address but in the serial bus. Data transmission between any nodes can be conducted via the serial data transmission system; slave nodes can be expanded; an independent control signal set and a transceiver are provided for data transmission and reception; full duplex data transmission can be achieved; and the serial data transmission system possesses high data transmission efficiency, simple hardware structure, great security, low cost and strong anti-disturbing capability.
Description
Technical field
The utility model belongs to technical field of data transmission, more specifically, relates to a kind of serial data transmission system.
Background technology
Along with motion control is to high-speed high-precision future development, design the factor that a set of high performance motion control system need to consider and need information to be processed also more and more, in most of the cases, only rely on a board to be difficult to all work.In multiprocessor precise motion control architecture, each board has been responsible for corresponding information processing, and reaches data interaction and comprehensive object by interconnected between board.Now, the data transmission system between plate is most important to whole motion control system.
Data transfer mode is divided into two kinds of parallel and serials.Parallel transmission can once transmit long numeric data on many parallel channels, and single volume of transmitted data is large like this, but channel is many, to take resource many and because interchannel signal cross-talk has limited the speed of parallel transmission.Serial transmission can only once be transmitted a data on a channel, although the data volume of single transmission is little, its transmission speed is faster than parallel transmission speed, and channel is few, and cost is low, is easy to realize.
At present, reach in the system of Gbps in interconnected speed, high speed serialization technology replaces rapidly traditional concurrent technique, becomes industry main flow.High speed serialization technology not only can be brought higher performance, lower cost and the design of more simplifying, but also has overcome parallel speed bottle-neck, has also saved I/O resource, makes the wiring of printed board simpler.But, existing Gbps stage speed serial transmission system is the middle FPGA+ high speed fibre that adopts mostly, which can realize data transmission between node far away, reliability is high, but need special serial data transceiver, for data transmission closely, hardware complexity, cost are higher, the most important thing is to realize between multinode and communicate by letter.
Utility model content
For above defect or the Improvement requirement of prior art, the utility model provides a kind of serial data transmission system, support the data transmission between arbitrary node, can expand from node, data send and receive has independently control signal collection and transceiver, can realize full-duplex data transmission, data transmission rate is high, and hardware configuration is simple, good confidentiality, cost is low, and antijamming capability is strong.
For achieving the above object, the utility model provides a kind of serial data transmission system, it is characterized in that, comprises main frame and multiple slave, described main frame comprises successively main serial transceiver, main CRC check device, bus controller and the primary memory of serial connection, described in each slave comprise serial connection successively from serial transceiver, from CRC check device, data processor with from storer, described main serial transceiver connects respectively from serial transceiver by the data bus in universal serial bus, and described bus controller is connected each data processor by the address bus in universal serial bus, enable signal line and rub-out signal line, described main serial transceiver is used for receiving the packet data bus with each from serial transceiver, also for sending packet to data bus, described main CRC check device is used for obtaining the CRC check code of valid data to be sent and being added corresponding Frame from CRC check device with each, the valid data that also receive for verification, described primary memory and be respectively used for storing valid data from storer, described bus controller is used for the data processing of controlling the operation of described serial data transmission system and completing host side, each data processor is for coordinating described main frame to complete the data processing of slave end according to the control signal of described bus controller.
Preferably, described data bus comprises transmission data bus and receives data bus, described address bus comprises transmission address bus and receiver address bus, described enable signal line comprises transmission enable signal line and reception enable signal line, and described rub-out signal line comprises transmission rub-out signal line and reception rub-out signal line; Described transmission data bus, described transmission address bus, described transmission enable signal line and described transmission rub-out signal line belong to transmission bus, described reception data bus, described receiver address bus, described reception enable signal line and described reception rub-out signal line belong to reception bus, and described transmission bus and described reception bus are separate.
Preferably, described main serial transceiver is the inner integrated high speed serialization transceiver of FPGA with each from serial transceiver.
In general, the above technical scheme of conceiving by the utility model compared with prior art, has following beneficial effect:
(1) main serial transceiver and be respectively the inner integrated high speed serialization transceiver of FPGA from serial transceiver, can make full use of FPGA internal logic resource, and hardware configuration is simple, and good confidentiality, cost are low; Serial transmission, takies I/O mouth few, and wiring is simple.
(2) support the data transmission between arbitrary node, host node with from relying on universal serial bus directly to transmit between node, respectively from realizing and transmitting using host node as terminal between node.
(3) can expand from node, respectively have independent node address from node, new node is mounted in bus and be equipped with new node address and can realize.
(4) data send and receive has independently control signal collection and transceiver, can realize full-duplex data transmission, and data transmission rate is high.
(5) differential lines transmission, antijamming capability is strong.
Accompanying drawing explanation
Fig. 1 is the structural representation of the serial data transmission system of the utility model embodiment;
Fig. 2 is the data transmission sequential chart of the serial data transmission system of the utility model embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.In addition,, in each embodiment of described the utility model, involved technical characterictic just can combine mutually as long as do not form each other conflict.
As shown in Figure 1, the serial data transmission system of the utility model embodiment comprise main frame and multiple slave (slave 1 ..., slave n, n be more than or equal to 1 and n be integer).Wherein, main frame comprises main serial transceiver, main CRC check device, bus controller and primary memory, and main serial transceiver, main CRC check device, bus controller and primary memory are connected in series successively.Each slave includes from serial transceiver, from CRC check device, data processor with from storer, from serial transceiver, from CRC check device, data processor be connected in series successively from storer.Main serial transceiver connects respectively from serial transceiver by the data bus in universal serial bus, and bus controller is connected each data processor by the address bus in universal serial bus, enable signal line and rub-out signal line.
This serial data transmission system can complete any internodal data transmission, wherein, data interaction between slave and main frame can directly rely on main serial transceiver and complete from serial transceiver, and need be through main frame transfer from internodal data interaction, although increased the data transmission time delay from node, greatly simplified bus structure.
Main serial transceiver and from serial transceiver for receiving packet data bus, also for sending packet to data bus.Packet comprises alignment of data symbol, some Frames (being made up of valid data and check code) and end mark.Main CRC check device and from CRC check device for obtaining the CRC check code of valid data to be sent and added corresponding Frame, also for the main serial transceiver of verification and the valid data that receive from serial transceiver.Bus controller is for controlling the operation of whole serial data transmission system and the data processing of host side.Primary memory and from storer the valid data for storage host and slave.Data processor is for completing the data processing of slave end according to the Signal cooperation main frame of bus controller.
Along with the continuous progress of integrated circuit technology, field programmable gate array (FPGA) chip internal is integrated can realize conventional data transmission platform (the General Data Transfer Platform that high-speed data is received and dispatched, GTP) transceiver module is the low-risk solution cheaply that provides connected in series.In the serial data transmission system of the utility model embodiment, main serial transceiver and be respectively the inner integrated high speed serialization transceiver of FPGA from serial transceiver.
Fig. 2 is the data transmission sequential chart of the serial data transmission system of the utility model embodiment, and send and receive bus is separate.
Process of transmitting: in the time sending enable signal TEn and be high level, main CRC check device draws the CRC check code of valid data to be sent, and be added in packet Valid TData and send through main serial transceiver in corresponding Frame.The transmission enable signal TEn of each data processor testbus controller output, sends address signal TAddr by corresponding slave addresses coupling effectively time, and the slave that the match is successful prepares to receive packet Valid TData.When slave completes after comma alignment, from CRC check device, Frame is carried out to CRC check, verification is by representing that the valid data that receive are correct, drag down and send rub-out signal TErr, and valid data are deposited in from storer, otherwise represent the valid data mistake receiving, draw high and send rub-out signal TErr, notice main frame resends previous frame data, and main frame drags down transmission enable signal TEn after sending packet, and this data transmission procedure finishes.
Receiving course: in the time that reception enable signal REn is high level, main frame prepares to receive packet ValidRData, the reception enable signal REn of each data processor testbus controller output, effectively time, corresponding slave addresses is mated to receiver address signal RAddr, the slave that the match is successful draw the CRC check code of valid data to be received from CRC check device, and be added in packet Valid RData in corresponding Frame through sending from serial transceiver.When main frame completes after comma alignment, main CRC check device carries out CRC check to Frame, verification is by representing that the valid data that receive are correct, drag down and receive rub-out signal RErr, and deposit valid data in primary memory, otherwise represent the valid data mistake receiving, draw high and receive rub-out signal RErr, notice slave resends previous frame data, and main serial transceiver drags down reception enable signal REn after receiving end mark, and this DRP data reception process finishes.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection domain of the present utility model.
Claims (3)
1. a serial data transmission system, is characterized in that, comprises main frame and multiple slave;
Described main frame comprises successively main serial transceiver, main CRC check device, bus controller and the primary memory of serial connection, described in each slave comprise serial connection successively from serial transceiver, from CRC check device, data processor with from storer;
Described main serial transceiver connects respectively from serial transceiver by the data bus in universal serial bus, and described bus controller is connected each data processor by the address bus in universal serial bus, enable signal line and rub-out signal line;
Described main serial transceiver is used for receiving the packet data bus with each from serial transceiver, also for sending packet to data bus, described main CRC check device is used for obtaining the CRC check code of valid data to be sent and being added corresponding Frame from CRC check device with each, the valid data that also receive for verification, described primary memory and be respectively used for storing valid data from storer, described bus controller is used for the data processing of controlling the operation of described serial data transmission system and completing host side, each data processor is for coordinating described main frame to complete the data processing of slave end according to the control signal of described bus controller.
2. serial data transmission system as claimed in claim 1, it is characterized in that, described data bus comprises transmission data bus and receives data bus, described address bus comprises transmission address bus and receiver address bus, described enable signal line comprises transmission enable signal line and reception enable signal line, and described rub-out signal line comprises transmission rub-out signal line and reception rub-out signal line;
Described transmission data bus, described transmission address bus, described transmission enable signal line and described transmission rub-out signal line belong to transmission bus, described reception data bus, described receiver address bus, described reception enable signal line and described reception rub-out signal line belong to reception bus, and described transmission bus and described reception bus are separate.
3. serial data transmission system as claimed in claim 1 or 2, is characterized in that, described main serial transceiver is the inner integrated high speed serialization transceiver of FPGA with each from serial transceiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320877596.4U CN203658995U (en) | 2013-12-27 | 2013-12-27 | Serial data transmission system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320877596.4U CN203658995U (en) | 2013-12-27 | 2013-12-27 | Serial data transmission system |
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| CN203658995U true CN203658995U (en) | 2014-06-18 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103744811A (en) * | 2013-12-27 | 2014-04-23 | 华中科技大学 | Serial data transmission system and method |
| CN105512070A (en) * | 2015-12-02 | 2016-04-20 | 中国电子科技集团公司第四十一研究所 | Control system based on serial bus |
-
2013
- 2013-12-27 CN CN201320877596.4U patent/CN203658995U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103744811A (en) * | 2013-12-27 | 2014-04-23 | 华中科技大学 | Serial data transmission system and method |
| CN105512070A (en) * | 2015-12-02 | 2016-04-20 | 中国电子科技集团公司第四十一研究所 | Control system based on serial bus |
| CN105512070B (en) * | 2015-12-02 | 2018-07-06 | 中国电子科技集团公司第四十一研究所 | A kind of control system based on universal serial bus |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140618 Termination date: 20141227 |
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| EXPY | Termination of patent right or utility model |