CN106502932B - Method based on interconnecting interface and its write operation and read operation between layered - Google Patents

Abstract

The invention discloses a kind of methods based on interconnecting interface and its write operation and read operation between layered.Wherein, the interface includes: transaction layer, it is configured as carrying the data of read or write from memory, and parse by data link layer transmitting Lai data, and when data link layer carries out write operation to data buffer zone, data are read from data buffer zone, and in enabled CRC check and correct verification, read data from data buffer zone；Data link layer is configured as carrying out the fractionation of parallel data between transaction layer and physical layer and combine, the assembly and parsing of control code, and according to physical channel number, is grouped to the data of read or write；Physical layer is configured as being grouped read or write data according to physical channel, and handles the data between data link layer and physical link.Solves the technical issues of how realizing low latency, high bandwidth and scalability strong transmission through the embodiment of the present invention.

Description

Method based on interconnecting interface and its write operation and read operation between layered

Technical field

The present embodiments relate to processor interconnection technique fields, are based on SerDes serial transmission skill more particularly, to one kind Art, between the piece of point-to-point interconnection architecture in data transmission procedure based on interconnecting interface and its write operation between layered With the method for read operation.

Background technique

With the development of information age, traditional Moore's Law, i.e., every 18 to 24 months, processor clock frequency turns over one Kind, have been converted to being doubled for the number of processor, Thread Count and other parallel algorithm performances.In order to meet the high property of information age Energy demand, computer system gradually develop from monokaryon to multicore, from multicore to multi-disc.Therefore, interconnection has become computer between piece The hot issue in architectural study field.

Multi-disc interconnection, is supplied to the mode of chip chamber information sharing, is greatly promoted to large-scale data calculation procedure Processing capacity.At a high speed, efficiently, and guarantee that the communication of chip chamber can be effectively reduced in interconnecting interface between the piece of data correctness Delay promotes the effective time ratio that processor carries out operation program, thus the processing capacity of effectively lifting system.

The interconnecting interface agreement between design high speed, efficient, reliable piece currently, industry is just spared no effort, however, due to existing There are design object, the direction of agreement different, under the high application scenarios of real-time, bandwidth requirement, cannot effectively play respectively Advantage.

In view of this, the present invention is specifically proposed.

Summary of the invention

How interconnecting interface between the embodiment of the present invention provides a kind of realizes low latency, high band at least to be partially solved The technical issues of wide and strong scalability transmission；A kind of interconnecting interface between piece is utilized to carry out write operation and reading in addition, additionally providing The method of operation.

To achieve the goals above, on the one hand, provide following technical scheme:

One kind being used for processor based on interconnecting interface between layered, the processor respectively with memory and object It manages link and data buffer zone is connected；The interface includes:

Transaction layer, be configured as from memory carry read or write data, and parse by data link layer transmitting Lai Data, and the data link layer to the data buffer zone carry out write operation when, from the data buffer zone read number According to, and in enabled CRC check and correct verification, data are read from the data buffer zone；

The data link layer is configured as carrying out the fractionation and group of parallel data between the transaction layer and physical layer It closes, the assembly and parsing of control code, and according to physical channel number, the data of the read or write is grouped；

The physical layer is configured as being grouped the read or write data, and locate according to the physical channel Manage the data between the data link layer and the physical link.

Further, the transaction layer specifically includes:

Configuration module is configurable to generate configuration data, so that the processor is deposited by bus access far-end address Device, local address register, transmission mode register, enabled register and status register；

High-speed read-write data module is configured as after the enabled register issues enable signal, in the memory The read or write of data is carried out between data packet management module；

Data packet management module is configurable to generate operation requests packet, and matches according to configuration module generation It sets data generation to write or read operation packet header control word, obtains the write operation data from the high-speed read-write data module, and raw At CRC redundancy check code, the data buffer zone is written into the CRC redundancy check code.

Further, the high-speed read-write data module, is specifically configured to: as the write operation and reading behaviour When the first transmitting terminal made, it is sent to the data packet management module from the memory read data, and by the data, CRC and CRC redundancy is enabled as the first receiving end of the write operation and the read operation and in the transmission mode register Code check module verifies in correct situation, and institute is written from the data packet management module read data packet, and by the data State memory；

The data packet management module has the second transmitting terminal and the second receiving end, and be specifically configured to its described the Two transmitting terminals generate write operation requests packet, read operation request packet and the data packet and its described second receiving end is counted According to parsing；

The data link layer specifically includes:

The CRC redundancy check module is configured as in the processor by transmitting mould described in the bus configuration Formula register enables CRC, and in the case where the high-speed read-write data module is as first receiving end, receives the height Fast reading writes the packet header information of data module generation and is determined whether to carry out CRC check, and root according to the header packet information CRC check response bag is generated according to check results；

Control word management module is configured as the data packet of the data packet management module and path management module generation Add control word；

The path management module has third transmitting terminal and third receiving end, and is configured as its described third and sends The configuration information generated according to the configuration module is held, the data of the data buffer zone are distributed to the physical layer, and Its described third receiving end is configured according to the physical channel number, is added to control for what the control word management module generated The allocation of packets of word is inserted into data instruction flag code into each physical channel, and from each physical channel Data are received, and data are aligned, obtain effective data packets and the effective data packets are sent to the control word pipe Manage module.

Further, the physical layer specifically includes:

Physical Coding Sublayer module, comprising:

Data encoding decoder module has the 4th transmitting terminal and the 4th receiving end, and is configured as its 4th transmission Clock signal is embedded in the data between the data link layer and the physical link and its described 4th receiving end by end Clock signal is extracted from the data received between the data link layer and the physical link, and parses significant figure According to；

Data scrambling descrambling module is configured as handling the data by after data encoding decoder module coding；

Physics Jie's additional sub-layer module, comprising:

Serial data neutralizing string module, has the 5th transmitting terminal and the 5th receiving end, and is configured as its 5th transmission End by first at a slow speed parallel data string turn to the first high-speed serial data and its described 5th receiving end for the second high speed serialization Data are converted into the second parallel data at a slow speed.

To achieve the goals above, on the other hand, it also provides a kind of above-mentioned based on layered using at least two Between the interconnecting interface method that carries out write operation, the write operation includes:

First executes following operation based on interconnecting interface between layered:

The packet header control word of write operation is generated according to the transmission mode register, and the packet header control word is sent to The physical channel, and write operation is carried out based on the processing result that interconnecting interface between layered is fed back according to second；

Described second executes following operation based on interconnecting interface between layered:

The packet header control word is received from the physical channel and is parsed, and obtains packet header control information, and according to institute It states packet header control information to carry out enabled or do not enable CRC read operation, the processing result is sent to described first based on layering Interconnecting interface between the piece of structure.

Further, the method for the write operation specifically includes:

First executes following operation based on interconnecting interface between layered:

1A: the data packet management module generates write operation packet header control word according to the configuration module, and the number is written According to buffer area；

1B: the data buffer zone is written in high-speed read-write data module read operation data from local address；

1C: judge whether enabled CRC, if so, the data packet management module generates CRC redundancy check code, and institute is written State data buffer zone；Otherwise, step 1D is executed；

1D: transmitting the data between the transaction layer and the data link layer, receives second by the physical link Based on the CRC check response bag that interconnecting interface between layered is fed back, and in the transaction layer to the data buffer zone When carrying out write operation, the data link layer is made to read data from the data buffer zone；

1E: the control word management module is that the data packet adds control word；

1F: the path management module is configured according to the physical channel number, and the control word management module is generated Data be assigned in each physical channel, and be inserted into the data command identity code；

1G: the clock signal is inserted into data flow by the data encoding decoder module, and is arranged again data Sequence；

1H: each parallel slow data in physical channel is carried out string by the serial data neutralizing string module, is assigned to institute It states in physical link；

Described second executes following operation based on interconnecting interface between layered:

2I: the serial data neutralizing string module reads data from the physical link, and high-speed serial data is carried out Parallelization；

2J: the data scrambling descrambling module goes back the data between the data link layer and the physical link Origin operation；

2K: the control word management module removes control code information according to the data command identity code, extracts the number According to packet；

2L: the path management module receives data from each physical channel, and the data are aligned, and obtains Effective data packets；

2M: the CRC redundancy check module receives the data packet that the high-speed read-write data module generates, and analyzes packet header Information, and in the case where enabled CRC check carries out CRC check to the data packet, and by the data in addition to cyclic redundancy check It is written data buffer zone, and the CRC check response bag is generated according to CRC redundancy check result, and by the CRC check Response bag feeds back to described first based on interconnecting interface between layered；

2N: transmission data link layer to the data between transaction layer；

2O: the data packet management module separates packet header and the Data payload of the data packet；

2P: the high-speed read-write data module reads data from the data packet management module, and the memory is written.

To achieve the goals above, it also provides a kind of above-mentioned based on interconnecting interface between layered using at least two The method for carrying out read operation, the read operation include:

First executes following operation based on interconnecting interface between layered:

The packet header control word of read operation is generated according to the transmission mode register, and the packet header control word is sent to The physical channel, and read operation is carried out based on the processing result that interconnecting interface between layered is fed back according to second；

Described second executes following operation based on interconnecting interface between layered:

The packet header control word is received from the physical channel and is parsed, and obtains packet header control information, and according to institute It states packet header control information to carry out enabled or do not enable CRC read operation, the processing result is sent to described first based on layering Interconnecting interface between the piece of structure.

Further, the method for the read operation specifically includes:

First executes following operation based on interconnecting interface between layered:

3A: the data packet management module generates read operation packet header control word according to the configuration module, and the number is written According to buffer area；

3B: the data buffer zone is written in high-speed read-write data module read operation data from local address；

3C: judge whether enabled CRC, if so, the data packet management module generates CRC redundancy check code, and institute is written State data buffer zone；Otherwise, step 3D is executed；

3D: transmitting the data between the transaction layer and the data link layer, receives second by the physical link Based on the CRC check response bag that interconnecting interface between layered is fed back, and in the transaction layer to the data buffer zone When carrying out read operation, the data link layer is made to read data from the data buffer zone；

3E: the control word management module is that the data packet adds control word；

3F: the path management module is configured according to the physical channel number, and the control word management module is generated Data be assigned in each physical channel, and be inserted into the data command identity code；

3G: the clock signal is inserted into data flow by the data encoding decoder module, and is arranged again data Sequence；

3H: each parallel slow data in physical channel is carried out string by the serial data neutralizing string module, is assigned to institute It states in physical link；

Described second executes following operation based on interconnecting interface between layered:

4I: the serial data neutralizing string module reads data from the physical link, and high-speed serial data is carried out Parallelization；

4J: the data scrambling descrambling module goes back the data between the data link layer and the physical link Origin operation；

4K: the control word management module removes control code information according to the data command identity code, extracts the number According to packet；

4L: the path management module receives data from each physical channel, and the data are aligned, and obtains Effective data packets；

4M: the CRC redundancy check module receives the data packet that the high-speed read-write data module generates, and analyzes packet header Information, and in the case where enabled CRC check carries out CRC check to the data packet, and by the data in addition to cyclic redundancy check It is written data buffer zone, and the CRC check response bag is generated according to CRC redundancy check result, and by the CRC check Response bag feeds back to described first based on interconnecting interface between layered；

4N: transmission data link layer to the data between transaction layer；

4O: the data packet management module separates packet header and the Data payload of the data packet；

4P: the data packet management module is written from the memory read data in the high-speed read-write data module.

Interface is divided into transaction layer, data link layer and physical layer by the embodiment of the present invention, wherein transaction layer is configured as The data of read or write are carried from memory, and parse by data link layer transmitting Lai data, and in data link layer pair When data buffer zone carries out write operation, data are read from data buffer zone, and in enabled CRC check and correct verification, from Read data in data buffer zone；Data link layer be configured as between transaction layer and physical layer carry out parallel data fractionation and Combination, the assembly and parsing of control code, and according to physical channel number, the data of read or write are grouped；Physical layer quilt It is configured to be grouped read or write data, and handle between data link layer and physical link according to physical channel Data.Carried out data transmission by being taken based on " packet ", so extra load is small；Support two kinds of " principal and subordinate " and " equity " point-to-point Communication mode；Between the piece of point-to-point interconnection architecture in data transmission procedure, it is strong to realize low latency, high bandwidth and scalability Transmission.

Detailed description of the invention

Fig. 1 is the physical link schematic diagram according to the embodiment of the present invention；

Fig. 2 is the structural schematic diagram according to interconnecting interface between the piece of the embodiment of the present invention；

Fig. 3 is the schematic diagram for being applied to SoC system on chip according to interconnecting interface between the piece of the embodiment of the present invention；

Fig. 4 is according to the write operation requests of the embodiment of the present invention and the structural schematic diagram of data packet；

Fig. 5 is the structural schematic diagram according to the read operation request packet of the embodiment of the present invention；

Fig. 6 is the structural schematic diagram according to interconnecting interface between the piece of another embodiment of the present invention；

Fig. 7 is between the local Link and distal end Link for not enabled CRC write operation according to the embodiment of the present invention Data interaction schematic diagram；

Fig. 8 is the number between the local Link and distal end Link for enabling CRC write operation according to the embodiment of the present invention According to interaction schematic diagram；

Fig. 9 is between the local Link and distal end Link for not enabled CRC read operation according to the embodiment of the present invention Data interaction schematic diagram；

Figure 10 is the number between the local Link and distal end Link for enabling CRC read operation according to the embodiment of the present invention According to interaction schematic diagram；

Figure 11 is the application scenarios schematic diagram based on interconnecting interface between layered according to the embodiment of the present invention.

Specific embodiment

The present invention will be described in detail with specific embodiment with reference to the accompanying drawing.In the absence of conflict, the present invention is real Each technical characteristic applied in example can be combined with each other or split and forms technical solution.Based on the embodiment in the application, ability Domain those of ordinary skill without creative efforts, all other equivalent or obvious variant the embodiment obtained It falls within the scope of protection of the present invention.

The embodiment of the present invention is based on SerDes (Serializer (serializer)/Deserializer (deserializer) abbreviation) Serial transfer techniques using data transfer mode end to end, and apply the data between the piece of point-to-point interconnection architecture to be transmitted across Cheng Zhong.Wherein, both ends include sending logic module (TX namely transmitting terminal) and reception logic (RX namely receiving end) module.

It is local Link, abbreviation L1 that regulation, which initiates the interface of reading and writing operational order, herein；Regulation receives physical link (such as Shown in Fig. 1) the reading and writing request of transmitting, the passive interface for carrying out corresponding operating is distal end Link, abbreviation L2；SoC is System On Chip, i.e. system on chip；Provide that system locating for L1 is SoC1, system locating for L2 is SoC2.Bus includes that data and address are believed Breath, system data bit wide is respectively referred to system address bit wide in text: in system on chip, data bit width that Interface & Bus connect With address bit wide.

Here, " local " and " distal end " is an opposite concept.Interface module in each SoC is either local Link is also possible to distal end Link, this is depended on whether as operational order promoter.

Link write operation refers to that L1 reads the data in SoC1 address field, and SoC2 address field is then written.Read operation Refer to that L1 reads the data of SoC2 address field to SoC1 address field.Reading and writing operation can choose whether to carry out the school CRC It tests.Relationship between " local address ", " far-end address ", " Link write operation " and " Link read operation " is as shown in Table 1:

Table one:

Action type	Data source address	Data destination address
			Link write operation	Local address	Far-end address
Link read operation	Far-end address	Local address

In order to meet the needs of application field is to real-time, high bandwidth and high scalability, the embodiment of the present invention proposes one kind Based on interconnecting interface between layered, it is used for processor, processor to be slow with memory and physical link and data respectively Rush Qu Xianglian；As shown in Fig. 2, the interface 10 may include: transaction layer 12, data link layer 14 and physical layer 16.Wherein, affairs Layer 12 be configured as from memory carry read or write data, and parse by data link layer transmitting Lai data, and When data link layer carries out write operation to data buffer zone, data are read from data buffer zone, and in enabled CRC check and school When testing correct, data are read from data buffer zone.Data link layer 14 is configured as carrying out simultaneously between transaction layer and physical layer The fractionation and combination of row data, the assembly and parsing of control code, and according to physical channel number, the data of read or write are carried out Grouping.The physical layer 16 is configured as being grouped read or write data, and handle data link according to physical channel Data between layer and physical link.

Wherein, since the working frequency of transaction layer is different from the working frequency of data link layer.Transaction layer and data link The transmitting of data can be carried out between layer by buffer area.It preferably, can be to send data buffer zone by setting buffers The reception data buffer and.Buffer area can use both-end RAM.The data bit width of buffer area is consistent with system data bit wide, and Depth is consistent with the maximum packet length that valid data load.The interface message of buffer area includes:

Clock signal；

Write enable bit: its high and low level respectively represents read-write operation；

Address bit wide: it is the depth of buffer area, i.e. the long required bit wide of maximum data packet；

Data input and data output: its bit wide is consistent with system data bit wide.

Fig. 3 schematically illustrates being applied to based on interconnecting interface between layered for proposition of the embodiment of the present invention The schematic diagram of SoC system on chip.The embodiment of the present invention realizes low latency, height between processor by using above-mentioned technical proposal Bandwidth, high scalability point-to-point serial interconnection technical effect.

In an alternative embodiment, above-mentioned transaction layer can specifically include: configuration module, high-speed read-write data module And data packet management module.Wherein, configuration module is configurable to generate configuration data, so that processor passes through bus access distal end Address register, local address register, transmission mode register, enabled register and status register.High-speed read-write data Module is configured as after enabled register issues enable signal, and data are carried out between memory and data packet management module Read or write.Data packet management module is configurable to generate operation requests packet, and the configuration data generated according to configuration module Generation writes or read operation packet header control word, obtains write operation data from high-speed read-write data module, and generate CRC redundancy check Data buffer zone is written in CRC redundancy check code by code.

In the above-described embodiments, configuration module provides functional configuration interface for processor, and processor can be visited by bus Ask following register: far-end address register, local address register, transmission mode register, enabled register and state are posted Storage.Wherein, bit wide Yu system (system herein for example can be SoC system on chip) address bit of far-end address register It is wide consistent, store write operation destination address or read operation source address；In transmission process, by write operation destination address or read to grasp Receiving end is sent to as source address, and receiving end is according to transmission operation requests, from read operation source address read requests data or toward writing Operate destination address write operation data.The bit wide of local address register is consistent with system address bit wide, stores write operation source Address or read operation destination address；In transmission process, transmitting terminal is read according to transmission operation requests from read operation destination address Operation data, or data are returned toward write operation source address write-read.Needed in the bit wide and practical application scene of transmission mode register Maximum transmission data length it is related, need alignment data bit width；And it is responsible for configuration this transmission selection physical channel number, behaviour Make type (read/write), type of data packet (operation requests packet/CRC response bag), valid data length, whether enabled CRC (is recycled Redundancy check) hardware check function etc..The bit wide of enabled register is consistent with system data bit wide, and it is logical to be responsible for configuration physics Transmission speed, link reset and the operation transmission in road are enabled.Required state number in the bit wide and practical application of status register Correlation, such as: operation start-stop flag bit, the working condition of each module, transmission wait overtime interrupt state, the excessive shape of number of retransmissions State etc.；Processor configuration far-end address register, local address register, transmission mode register and enabled register terminate Afterwards, the operation outside operation data memory can not be influenced, if you need to judge whether the operation is correctly finished, shape can be inquired State register, such as: can inquire error of transmission state, transmission progress, this operation whether normal termination etc..Status register Also the status information that can recorde each module can be additionally configured to location of mistake and debugging after sending failure.It is above-mentioned High-speed read-write data module starts to operate after transmission operation is enabled, using the bus protocol that high-speed read-write can be supported to operate.

In an alternative embodiment, above-mentioned high-speed read-write data module specifically can be additionally configured to as write behaviour When making the first transmitting terminal with read operation, from memory read data, and data packet management module is sent data to, in conduct First receiving end of write operation and read operation and transmission mode register enable CRC and CRC redundancy check module verification just In the case where really, from data packet management module read data packet, and write data into.Above-mentioned data packet management module tool There are the second transmitting terminal and the second receiving end, and specifically can be additionally configured to its second transmitting terminal and generate write operation requests packet, read Operation requests packet and data packet and its second receiving end carry out data parsing.Above-mentioned data link layer can specifically include: CRC redundancy check module, control word management module and path management module.Wherein, CRC redundancy check module is configured as CRC is enabled by bus configuration transmission mode register in processor, and in high-speed read-write data module as the first receiving end In the case where, it receives the packet header information that high-speed read-write data module generates and determines whether to carry out according to header packet information CRC check, and CRC check response bag is generated according to check results.Control word management module is configured as managing mould for data packet The data packet that block and path management module generate adds control word.There is path management module third transmitting terminal and third to receive End, and be configured as the configuration information that its third transmitting terminal is generated according to configuration module, by the data of data buffer zone distribute to Physical layer, and its third receiving end is configured according to physical channel number, is added to control for what control word management module generated The allocation of packets of word is inserted into data instruction flag code into each physical channel, and receives data from each physical channel, And data are aligned, effective data packets are obtained and effective data packets are sent to control word management module.

In the above-described embodiments, if high-speed read-write data module is the transmitting terminal of write operation and read operation, the module Data are read from system storage gives data packet management module；If high-speed read-write data module is write operation and read operation Receiving end, (if enabled CRC check, CRC redundancy check module check results are correct), then the module manages mould from data packet Block reads data, and is written to destination address.If data packet management module generates write operation requests sum number as transmitting terminal According to packet, read operation request packet；If data packet management module as receiving end, is responsible for parsing operation requests packet and data packet Content.Fig. 4 schematically illustrates the structural schematic diagram of write operation requests and data packet.Fig. 5 schematically illustrates reading behaviour Make the structural schematic diagram of request packet.Wherein, packet header control word includes: that far-end address and this transmission mode configuration information (that is: are matched Set the data in the far-end address register and transmission mode register in module), this transmission select physical channel number, operation Type (read/write operation), type of data packet (operation requests packet/CRC response bag), valid data length and whether enabled CRC Hardware check function etc..

Packet header control word field definition is as shown in Table 2.

Table two:

Wherein, each field meanings are as follows:

Far-end address: if write operation requests, which is to write destination address, and if read operation request, which is to read Take source address.

Valid data length: indicating that read-write operation transmits data amount check, and data bit width is identical as system data bit wide, Depth is determined by the length of maximum data packet in practical application scene.Assuming that data bit width is 32, maximum wraps a length of 4KB, then The field accounts for 10, and M is equal to N+10, wherein it is the whole of system data bit wide that numerical value of N, which is configured as alignment packet header control word width, Several times.

Number of active lanes: it indicates the enabled physical transmission channel number of transmission, supports the moulds such as X1, X4, X8, X16 and X32 Formula.Digital representation number of active lanes after X, for example, X4 is represented in transmission process, enabling number of active lanes is 4.

Reserved field N:8, can selected part position give over to technology innovation.

Type of data packet: show that data packet is that operation requests packet, the correct response bag of CRC check or CRC check mistake are rung It should wrap.

Transmission command type: expression is transmitted as write operation or read operation request.

1 reserved field gives over to technology extension.

The Data payload illustrated in Fig. 3 is write operation data, and bit wide is system data bit wide, length For the valid data length configured in the control word of packet header.The CRC illustrated in Fig. 3 is the selection of redundancy check code, according to Depending on the requirement in practical application to data transmission accuracy, it is configured as supplement invalid bit, with alignment data bit width.

In the above-described embodiments, after above-mentioned CRC redundancy check module receives data as receiving end, according to data packet head Information decides whether to carry out CRC check.If enabled CRC check, CRC redundancy check module has been arranged in transmission mode register CRC redundancy check is carried out to received data, and generates CRC check response bag according to check results.Specifically, according to verification As a result it generates CRC check response bag and is divided into two kinds of situations:

If a) check errors, according to received data, CRC check errored response packet is generated, only includes packet header control Word information processed, type of data packet are designated as CRC response bag, and transmitting terminal (such as: high-speed read-write data module) is waited to be retransmitted Operation.Exceed fixed threshold if waiting and retransmitting data time, interrupts this operation, corresponding error of transmission flag bit is set, then Processor is fed back to, and determines link failure；If transmitting terminal number of retransmissions exceeds retransmission threshold value, this operation is interrupted, phase is set Error of transmission flag bit is answered, feeds back to processor, and determine link failure；

If b) verification is correct, high-speed read-write data module writes the data information in reception data buffer toward purpose Address.

In the above-described embodiments, above-mentioned control word management module is the definition of the control word of data packet addition referring to table three:

Table three:

Control word management module is that data packet adds beginning flag code, idle marker code etc., and being conducive to receiving end in this way will Effective data packets are separated from the received data of physical layer.Wherein, IDL code mark physical link is currently without operation requests； When physical link resets, the alignment of data at physical link both ends is carried out, by COM code to guarantee that physical link can be correctly received Data；PAD code is in transmission process, when physical link transmission speed is slower than physical channel transmission speed, to guarantee information Correctness and integrality, and to physical link add invalid data；STP code and END code carry out synchronizing information, indicate respectively The starting and end of data packet.

In the above-described embodiments, information of the transmitting terminal of above-mentioned path management module according to configuration module configuration, will send The data of buffer area are assigned to physical layer.Information of the receiving end of above-mentioned path management module according to physical layer, by data information It reconfigures as system data bit wide, and control word management module is transferred to be analyzed.If waiting time or the CRC of data to be received Response bag exceeds fixed threshold, then interrupts this operation, corresponding error of transmission flag bit is arranged, and feed back to processor, determines object Manage link failure；If transmitting terminal, which receives crc error response bag number, exceeds fixed threshold, this operation is interrupted, corresponding pass is set It inputs accidentally flag bit by mistake, and feeds back to processor, determine physical link failure.

The embodiment of the present invention is based on " packet " by adopting the above technical scheme and carries out data transmission, and extra load is small.

In an alternative embodiment, above-mentioned physical layer can specifically include: Physical Coding Sublayer module and physics are situated between Additional sub-layer module.Wherein, Physical Coding Sublayer module includes: data encoding decoder module and data scrambling descrambling module.Number There is the 4th transmitting terminal and the 4th receiving end according to coding and decoding module, and be configured as its 4th transmitting terminal and be embedded in clock signal In data between data link layer and physical link and its 4th receiving end from receive data link layer and physical link it Between data in extract clock signal, and parse valid data.Data scrambling descrambling module is configured as processing by data encoding Data after decoder module coding.Physics Jie's additional sub-layer module includes serial data neutralizing string module, serial data neutralizing string module With the 5th transmitting terminal and the 5th receiving end, and it is configured as its 5th transmitting terminal and will turns to high speed serialization by parallel data string at a slow speed Converting high-speed serial is turned to parallel data at a slow speed by data and its 5th receiving end.

In the above-described embodiments, data scrambling descrambling module resequences to data, in this way can the company of reduction " 0 " and The even number of " 1 ".

Fig. 6 schematically illustrates another structural schematic diagram based on interconnecting interface between layered.

Data link layer and physical layer are grouped operation data, every group may include: according to port number is supported

Parallel data: its bit wide is determined by used PCS layers of coding mode, not necessarily identical as system data bit wide；It is logical Road management module spells efficient data distribution to each physical channel, or by the valid data enabled in physical channel It connects；

Data command identity code: it indicates that present parallel data is control word or valid data information；

Send idle marker: it indicates whether present physical channel is currently being used；

Physical channel transmission speed: it is such as can be set to 5GT/s, 8GT/s；

Ready state mark: the configuration of physical link transmission speed needs the regular hour, after transmission speed is stablized, passes through The flag bit feeds back to data link layer, indicates the transmission that can start to carry out data packet.

Description through the above technical solution will be in different working conditions it is found that Link executes different operations.Root According to above-mentioned " local/distal end ", " Link write operation/Link read operation " and whether CRC check function is enabled, co-exists in 4 pairs, is total to 8 kinds of different working conditions, as shown in Table 4:

Table four:

Wherein, for not enabling CRC write operation, i.e. Case1 in table two, the data between local Link and distal end Link Interaction scenario is as shown in fig. 7, the wherein direction of arrows show data flow.The operation applied field more stable for physical link Write operation requests and data packet are only sent to receiving end by scape, transmitting terminal, do not need to carry out handshake communication, efficiency of transmission is high.

For enabling CRC write operation, i.e. Case2 in table four, the data interaction feelings between local Link and distal end Link Condition is as shown in figure 8, the wherein direction of arrows show data flow.The operation promotes transmission reliability by handshake communication.If in figure CRC response bag be errored response packet, then L1 can retransmit write operation requests and data packet, and CRC check is waited correctly to respond Packet.In transmission process, if it is more than threshold value that L1, which waits the time of CRC response bag, abandons this time operating, corresponding pass is set It inputs accidentally flag bit by mistake, feeds back to processor, and determine link failure；If number of retransmissions is greater than fixed threshold, L1 abandons this Secondary operation, and corresponding error of transmission flag bit is set；If check errors number is greater than fixed threshold, L2 abandons this time grasping Make, and corresponding error of transmission flag bit is set.

For not enabling CRC read operation, i.e. Case3 in table four, the data interaction between local Link and distal end Link Situation is as shown in figure 9, the wherein direction of arrows show data flow.In this operation, if L1 waits read operation data time to exceed Fixed threshold then interrupts this operation, and corresponding error of transmission mark is arranged, feeds back to processor, and determine link failure.

For enabling CRC read operation, i.e. Case4 in table four, the data interaction feelings between local Link and distal end Link Condition is as shown in Figure 10, the direction of arrows show data flow.In this operation, if L1 waits read operation data time to exceed fixed threshold Value, then interrupt this operation, and corresponding error of transmission flag bit is arranged.If the CRC response bag in figure is errored response packet, L2 Write operation requests and data packet can be retransmitted, the correct response bag of CRC check is waited, if the number of transmissions is greater than fixed threshold, Then L2 abandons this time operating, and corresponding error of transmission flag bit is arranged；If it is more than threshold value, L2 that L2, which waits the CRC response bag time, It abandons this time operating, and corresponding error of transmission flag bit is set.

Figure 11 schematically illustrates the application provided in an embodiment of the present invention based on interconnecting interface between layered Schematic diagram of a scenario.Wherein, provided through the embodiment of the present invention between three SoC (i.e. SoC0, SoC1 and SoC2) based on layering Interconnecting interface between the piece of structure, carries out data transmission via physical link.

It should be noted that provided by the above embodiment carried out data transmission based on interconnecting interface between layered When, only the example of the division of the above functional modules, in practical applications, it can according to need and by above-mentioned function Distribution is completed by different functional modules, i.e., the module in the embodiment of the present invention is decomposed or combined again.

The embodiment of the present invention also provides a kind of method for carrying out write operation using interconnecting interface between sheet above, and this method can be with It is executed by interconnecting interface embodiment between sheet above.This method may include:

First executes following operation based on interconnecting interface between layered: writing behaviour according to the generation of transmission mode register The packet header control word of work, and packet header control word is sent to physical channel, and the place fed back according to interconnecting interface between second It manages result and carries out write operation.

Second executes following operation based on interconnecting interface between layered: receiving packet header control word simultaneously from physical channel It is parsed, obtains packet header control information, and information is controlled according to packet header and carries out enabled or not enabled CRC read operation, will handle As a result interconnecting interface between being sent to first.

The embodiment of the present invention data can be transmitted across by using above-mentioned technical proposal between the piece of point-to-point interconnection architecture Cheng Zhong realizes the strong data transmission of low latency, high bandwidth, scalability.

In an alternative embodiment, the method for above-mentioned write operation can specifically include:

First executes following operation based on interconnecting interface between layered:

1A: data packet management module generates write operation packet header control word according to configuration module, and data buffer zone is written；

1B: data buffer zone is written in high-speed read-write data module read operation data from local address；

1C: judging whether enabled CRC, if so, data packet management module generates CRC redundancy check code, and it is slow that data are written Rush area；Otherwise, step 1D is executed；

1D: the data between transmission transaction layer and data link layer, interconnecting interface between receiving second by physical link The CRC check response bag of feedback, and when transaction layer carries out write operation to data buffer zone, make data link layer from data buffering Read data in area；

1E: control word management module is that data packet adds control word；

1F: path management module is configured according to physical channel number, and the data that control word management module generates are assigned to In each physical channel, and it is inserted into data instruction flag code；

1G: clock signal is inserted into data flow by data encoding decoder module, and is resequenced to data；

1H: the parallel slow data in each physical channel is carried out string by serial data neutralizing string module, is assigned in physical link；

Second executes following operation based on interconnecting interface between layered:

2I: serial data neutralizing string module reads data from physical link, and high-speed serial data is carried out parallelization；

2J: data scrambling descrambling module carries out restoring operation to the data between data link layer and physical link；

2K: control word management module removes control code information according to data command identity code, extracts data packet；

2L: path management module receives data from each physical channel, and data are aligned, and obtains effective data packets；

2M:CRC redundancy check module receives the data packet that high-speed read-write data module generates, and analyzes header packet information, and In the case where enabled CRC check, CRC check is carried out to data packet, and data buffering is written into the data in addition to cyclic redundancy check Area, and CRC check response bag is generated according to CRC redundancy check result, and CRC check response bag is fed back between first Interconnecting interface；

2N: transmission data link layer to the data between transaction layer；

2O: the packet header of data packet management module Separation of the packets and Data payload；

2P: high-speed read-write data module reads data from data packet management module, and memory is written.

Carry out the data transmission stream journey of the present invention will be described in detail embodiment with a preferred embodiment below.

The data transmission stream journey is based on interconnecting interface embodiment between sheet above.Wherein, transaction layer complete data carry and The generation of CRC redundant code；The generation and detection and the verification of CRC redundant code of data link layer completion control code retransmit；Physics Layer completes valid data encoding and decoding and string neutralizing string.

Configure the far-end address register of L1 and L2, local address register, transmission mode register, enabled register and Status register.Transmission mode is configured if first time, needs to configure the transmission channel number and transmission speed of L1, and configure L2's Transmission speed.If you need to change transmission speed or transmission channel number, then need to carry out L1 and L2 reset operation, then carry out port number With the configuration of transmission speed, to guarantee that physical link is in the state of configuration requirement.Buffer area include send data buffer zone and Reception data buffer.

Write operation method may include:

A: data packet management module generates packet header control word according to the information of configuration module configuration, and it is slow that transmission data are written Rush area；

B: by high-speed read-write data module from local address read operation data, and be written send data buffer zone；

C: if this operates enabled CRC, data packet management module generates CRC redundancy check code, and transmission number is written According to buffer area；

D: if this operation is not enabled on CRC, step c is not executed, that is, skips and writes CRC redundant code generation phase；

E: sending data buffer zone is data transmission interface of the transaction layer to data link layer, in transaction layer to transmission data When buffer area carries out write operation, data link layer can read data from the transmission data buffer zone simultaneously；

F: control word management module, which sends data after Phy reset and is set to, resets link initial value COM；Do not sending out When sending data packet, it is set to idle state IDL；If receiving write operation order or receiving CRC check errored response packet, it is first set to starting Indicate STP, then, starts to send data packet, if transaction layer writing buffer speed is slower than data link layer in transmission process Reading buffer speed, then be inserted into PAD in valid data；After data are sent, it is set to END；

G: path management module is configured according to physical channel number, and the data that control word management module generates are assigned to In each physical channel, and it is inserted into data instruction flag code, receives data bit control code or valid data herein with mark；If this Enabled CRC check is operated, then after sending the packet within, starts timing, if waiting the CRC response bag time is more than threshold value, This operation is then interrupted, and corresponding error of transmission flag bit is set；

H: clock information is inserted into data flow using coding modes such as 8b10b or 128b130b by data encoding decoder module In；Data scrambling descrambling module resequences to data；

I: by each physical channel, input data carries out string to serial data neutralizing string module at a slow speed parallel, and is assigned to physics In link；

J: serial data neutralizing string module reads data from physical link, and high-speed serial data is carried out parallelization；

K: data scrambling descrambling module carries out restoring operation to data；When data encoding decoder module is extracted from data flow Clock information and data information, and data link layer is passed to by each physical channel with physical layer interface；

L: control word management module removes control code information according to data command identity code, and extracts data packet；

M: path management module receives data from each physical channel, and data are aligned, really effective to obtain Data packet；

It is docked if detecting this operates enabled CRC check n:CRC redundancy check module analysis header packet information position It receives data packet and carries out CRC check, while reception data buffer is written into the data in addition to cyclic redundancy check；

O: if CRC redundancy check result is correct, generating the correct response bag of CRC check, the step f executed by L2 L1 is fed back to step i, executes step s；If check results mistake, CRC check errored response packet is generated, and pass through L2's The step f to step i of execution feeds back to L1, and L1 is waited to carry out retransmission operation, if check errors number is more than threshold value, interrupts this Operation, the corresponding error of transmission flag bit of juxtaposition；

P: if receiving the correct response bag of CRC, L1, which sets this transmission operation, to be terminated；If receiving crc error response bag, Then counter adds 1, and re-executes since step f to step p, when counter reaches predetermined threshold, then interrupts this operation, The corresponding error of transmission flag bit of juxtaposition；If L1 does not receive CRC response bag for a long time, this operation is interrupted, juxtaposition passes accordingly Input accidentally flag bit by mistake；

Q:CRC redundancy check module analysis header packet information position, if detecting this operation is not enabled on CRC check, directly It connects and writes data into reception data buffer；

R: reception data buffer is data transmission interface of the data link layer to transaction layer, if being not enabled on CRC check, Then when data link layer is to data buffer zone progress write operation is sent, transaction layer reads number from transmission data buffer zone simultaneously According to；If enabled CRC check, transaction layer is read after CRC redundancy check result is correct from sending in data buffer zone Number；

S: data packet management module analyzes the data information in reception data buffer, and it is effectively negative to separate packet header and data It carries；

T: high-speed read-write data module reads data from data packet management module, and is written in destination address.

In addition, the embodiment of the present invention also provides a kind of method for carrying out read operation using interconnecting interface between sheet above, the party Method can be executed by interconnecting interface embodiment between sheet above.This method may include:

First executes following operation based on interconnecting interface between layered: generating according to transmission mode register and reads behaviour The packet header control word of work, and packet header control word is sent to physical channel, and the place fed back according to interconnecting interface between second It manages result and carries out read operation.

Second executes following operation based on interconnecting interface between layered: receiving packet header control word simultaneously from physical channel It is parsed, obtains packet header control information, and information is controlled according to packet header and carries out enabled or not enabled CRC read operation, will handle As a result interconnecting interface between being sent to first.

In an alternative embodiment, the method for above-mentioned read operation can specifically include:

First executes following operation based on interconnecting interface between layered:

3A: data packet management module generates read operation packet header control word according to configuration module, and data buffer zone is written；

3B: data buffer zone is written in high-speed read-write data module read operation data from local address；

3C: judging whether enabled CRC, if so, data packet management module generates CRC redundancy check code, and it is slow that data are written Rush area；Otherwise, step 3D is executed；

3D: the data between transmission transaction layer and data link layer, interconnecting interface between receiving second by physical link The CRC check response bag of feedback, and when transaction layer carries out read operation to data buffer zone, make data link layer from data buffering Read data in area；

3E: control word management module is that data packet adds control word；

3F: path management module is configured according to physical channel number, and the data that control word management module generates are assigned to In each physical channel, and it is inserted into data instruction flag code；

3G: clock signal is inserted into data flow by data encoding decoder module, and is resequenced to data；

3H: the parallel slow data in each physical channel is carried out string by serial data neutralizing string module, is assigned in physical link；

Second executes following operation based on interconnecting interface between layered:

4I: serial data neutralizing string module reads data from physical link, and high-speed serial data is carried out parallelization；

4J: data scrambling descrambling module carries out restoring operation to the data between data link layer and physical link；

4K: control word management module removes control code information according to data command identity code, extracts data packet；

4L: path management module receives data from each physical channel, and data are aligned, and obtains effective data packets；

4M:CRC redundancy check module receives the data packet that high-speed read-write data module generates, and analyzes header packet information, and In the case where enabled CRC check, CRC check is carried out to data packet, and data buffering is written into the data in addition to cyclic redundancy check Area, and CRC check response bag is generated according to CRC redundancy check result, and CRC check response bag is fed back between first Interconnecting interface；

4N: transmission data link layer to the data between transaction layer；

4O: the packet header of data packet management module Separation of the packets and Data payload；

4P: data packet management module is written from memory read data in high-speed read-write data module.

Read operation is similar with write operation operating process, the difference is that the reading behaviour that data packet management module generates in L1 transmitting terminal Make request packet, this time request of packet header action type explanation is read request, the step a in execution write operation method embodiment to step It is read request that s, L2, which analyze receiving end this action type, turns to transmitting terminal, generates write operation requests and data packet, step later Suddenly identical to step t as the step b in write operation method embodiment.

The data transmission stream journey of read operation is described in detail with a preferred embodiment below.Wherein, buffer area includes sending Data buffer zone and reception data buffer.

The read operation method may include:

Step 1:L1 transaction layer generates the header packet information of read operation according to the register of configuration module configuration, and is stored in transmission Data buffer zone；

Step 2:L1 data link layer reads data from transmission data buffer zone, and header packet information is assigned to each physics number Control code is inserted into according to channel, and according to data packet format；If L1 does not receive reading data packet for a long time, this operation, juxtaposition are interrupted Corresponding error of transmission flag bit；

The packet header control information that the parsing of step 3:L2 data link layer receives, and it is sent to transaction layer；

Step 4:L2 transaction layer carries out enabled or does not enable CRC write operation according to packet header control information；

After step 5:L1 is properly received data, operation is completed.

Although each step is described in the way of above-mentioned precedence in above-described embodiment, this field Technical staff is appreciated that the effect in order to realize the present embodiment, executes between different steps not necessarily in such order, It (parallel) execution simultaneously or can be executed with reverse order, these simple variations all protection scope of the present invention it It is interior.

" first ", " second " being related in text do not represent sequence, only distinguished name, are not construed as to the present invention The improper restriction of protection scope.

It shall also be noted that language used in this specification primarily to readable and introduction purpose and select, Rather than in order to explain or defining the subject matter of the present invention and select.

Present invention is not limited to the embodiments described above, and without departing substantially from substantive content of the present invention, this field is common Any deformation, improvement or the replacement that technical staff is contemplated that each fall within protection scope of the present invention.

Claims (7)

1. one kind based on interconnecting interface between layered, is used for processor, the processor respectively with memory and physics Link and data buffer zone are connected；It is characterized in that, the interface includes:

Transaction layer, be configured as from memory carry read or write data, and parse by data link layer transmitting Lai number According to, and when the data link layer carries out write operation to the data buffer zone, data are read from the data buffer zone, with And in enabled CRC check and correct verification, data are read from the data buffer zone；

The data link layer, be configured as between the transaction layer and physical layer carry out parallel data fractionation and combine, The assembly and parsing of control code, and according to physical channel number, the data of the read or write are grouped；

The physical layer is configured as being grouped the read or write data, and handle institute according to the physical channel State the data between data link layer and the physical link；

Wherein, the transaction layer specifically includes:

Configuration module is configurable to generate configuration data, so that the processor passes through bus access far-end address register, sheet Way address register, transmission mode register, enabled register and status register；

High-speed read-write data module is configured as after the enabled register issues enable signal, in the memory and number According to the read or write for carrying out data between packet management module；

Data packet management module is configurable to generate operation requests packet, and the configuration number generated according to the configuration module It is write according to generation or read operation packet header control word, obtains the write operation data from the high-speed read-write data module, and generate CRC The data buffer zone is written in the CRC redundancy check code by redundancy check code.

2. interconnecting interface between according to claim 1, which is characterized in that

The high-speed read-write data module, is specifically configured to: sending as the first of the write operation and the read operation When end, it is sent to the data packet management module from the memory read data, and by the data, is writing behaviour as described Make to enable CRC and CRC redundancy check module school with the first receiving end of the read operation and in the transmission mode register It tests in correct situation, the memory is written from the data packet management module read data packet, and by the data；

The data packet management module has the second transmitting terminal and the second receiving end, and is specifically configured to its second hair Sending end generates write operation requests packet, read operation request packet and the data packet and its described second receiving end carries out data solution Analysis；

The data link layer specifically includes:

The CRC redundancy check module is configured as posting in the processor by transmission mode described in the bus configuration Storage enables CRC, and in the case where the high-speed read-write data module is as first receiving end, receives the high fast reading It writes the packet header information of data module generation and is determined whether to carry out CRC check according to the header packet information, and according to school It tests result and generates CRC check response bag；

Control word management module is configured as the data packet addition for the data packet management module and path management module generation Control word；

The path management module, have third transmitting terminal and third receiving end, and be configured as its described third transmitting terminal according to According to the configuration information that the configuration module generates, the data of the data buffer zone are distributed to the physical layer, and its institute It states third receiving end to configure according to the physical channel number, is added to control word for what the control word management module generated Allocation of packets is inserted into data instruction flag code into each physical channel, and receives from each physical channel Data, and data are aligned, effective data packets are obtained and the effective data packets are sent to the control word management mould Block.

3. interconnecting interface between according to claim 2, which is characterized in that the physical layer specifically includes:

Physical Coding Sublayer module, comprising:

Data encoding decoder module has the 4th transmitting terminal and the 4th receiving end, and being configured as its described 4th transmitting terminal will Clock signal is embedded in the data between the data link layer and the physical link and its described 4th receiving end is from connecing It receives in the data between the data link layer and the physical link and extracts clock signal, and parse valid data；

Data scrambling descrambling module is configured as handling the data by after data encoding decoder module coding；

Physics Jie's additional sub-layer module, comprising:

Serial data neutralizing string module, has the 5th transmitting terminal and the 5th receiving end, and being configured as its described 5th transmitting terminal will First at a slow speed parallel data string turn to the first high-speed serial data and its described 5th receiving end for the second high-speed serial data It is converted into the second parallel data at a slow speed.

4. a kind of method for carrying out write operation using interconnecting interface between piece as claimed in claim 3, which is characterized in that described to write behaviour Work includes:

First executes following operation based on interconnecting interface between layered:

The packet header control word of write operation is generated according to the transmission mode register, and the packet header control word is sent to described Physical channel, and write operation is carried out based on the processing result that interconnecting interface between layered is fed back according to second；

Described second executes following operation based on interconnecting interface between layered:

The packet header control word is received from the physical channel and is parsed, and obtains packet header control information, and according to the packet Head control information carries out enabled or does not enable CRC read operation, and the processing result is sent to described first based on layered structure Piece between interconnecting interface.

5. the method for write operation according to claim 4, which is characterized in that the method for the write operation specifically includes:

First executes following operation based on interconnecting interface between layered:

1A: the data packet management module generates write operation packet header control word according to the configuration module, and it is slow that the data are written Rush area；

1B: the data buffer zone is written in high-speed read-write data module read operation data from local address；

1C: judge whether enabled CRC, if so, the data packet management module generates CRC redundancy check code, and the number is written According to buffer area；Otherwise, step 1D is executed；

1D: transmitting the data between the transaction layer and the data link layer, receives second by the physical link and is based on The CRC check response bag that interconnecting interface is fed back between layered, and the data buffer zone is carried out in the transaction layer When write operation, the data link layer is made to read data from the data buffer zone；

1E: the control word management module is that the data packet adds control word；

1F: the path management module is configured according to the physical channel number, the number that the control word management module is generated According to being assigned in each physical channel, and it is inserted into the data command identity code；

1G: the clock signal is inserted into data flow by the data encoding decoder module, and is resequenced to data；

1H: each parallel slow data in physical channel is carried out string by the serial data neutralizing string module, is assigned to the object It manages in link；

Described second executes following operation based on interconnecting interface between layered:

2I: the serial data neutralizing string module reads data from the physical link, and high-speed serial data is carried out parallel Change；

2J: the data scrambling descrambling module carries out reduction behaviour to the data between the data link layer and the physical link Make；

2K: the control word management module removes control code information according to the data command identity code, extracts the data packet；

2L: the path management module receives data from each physical channel, and the data are aligned, and obtains effective Data packet；

2M: the CRC redundancy check module receives the data packet that the high-speed read-write data module generates, analysis packet header letter Breath, and in the case where enabled CRC check, CRC check is carried out to the data packet, and the data in addition to cyclic redundancy check are write Enter data buffer zone, and the CRC check response bag is generated according to CRC redundancy check result, and the CRC check is rung It should wrap and feed back to described first based on interconnecting interface between layered；

2N: transmission data link layer to the data between transaction layer；

2O: the data packet management module separates packet header and the Data payload of the data packet；

2P: the high-speed read-write data module reads data from the data packet management module, and the memory is written.

6. a kind of method for carrying out read operation using interconnecting interface between piece as claimed in claim 3, which is characterized in that the reading behaviour Work includes:

First executes following operation based on interconnecting interface between layered:

The packet header control word of read operation is generated according to the transmission mode register, and the packet header control word is sent to described Physical channel, and read operation is carried out based on the processing result that interconnecting interface between layered is fed back according to second；

Described second executes following operation based on interconnecting interface between layered:

The packet header control word is received from the physical channel and is parsed, and obtains packet header control information, and according to the packet Head control information carries out enabled or does not enable CRC read operation, and the processing result is sent to described first based on layered structure Piece between interconnecting interface.

7. the method for read operation according to claim 6, which is characterized in that the method for the read operation specifically includes:

First executes following operation based on interconnecting interface between layered:

3A: the data packet management module generates read operation packet header control word according to the configuration module, and it is slow that the data are written Rush area；

3B: the data buffer zone is written in high-speed read-write data module read operation data from local address；

3C: judge whether enabled CRC, if so, the data packet management module generates CRC redundancy check code, and the number is written According to buffer area；Otherwise, step 3D is executed；

3D: transmitting the data between the transaction layer and the data link layer, receives second by the physical link and is based on The CRC check response bag that interconnecting interface is fed back between layered, and the data buffer zone is carried out in the transaction layer When read operation, the data link layer is made to read data from the data buffer zone；

3E: the control word management module is that the data packet adds control word；

3F: the path management module is configured according to the physical channel number, the number that the control word management module is generated According to being assigned in each physical channel, and it is inserted into the data command identity code；

3G: the clock signal is inserted into data flow by the data encoding decoder module, and is resequenced to data；

3H: each parallel slow data in physical channel is carried out string by the serial data neutralizing string module, is assigned to the object It manages in link；

Described second executes following operation based on interconnecting interface between layered:

4I: the serial data neutralizing string module reads data from the physical link, and high-speed serial data is carried out parallel Change；

4J: the data scrambling descrambling module carries out reduction behaviour to the data between the data link layer and the physical link Make；

4K: the control word management module removes control code information according to the data command identity code, extracts the data packet；

4L: the path management module receives data from each physical channel, and the data are aligned, and obtains effective Data packet；

4M: the CRC redundancy check module receives the data packet that the high-speed read-write data module generates, analysis packet header letter Breath, and in the case where enabled CRC check, CRC check is carried out to the data packet, and the data in addition to cyclic redundancy check are write Enter data buffer zone, and the CRC check response bag is generated according to CRC redundancy check result, and the CRC check is rung It should wrap and feed back to described first based on interconnecting interface between layered；

4N: transmission data link layer to the data between transaction layer；

4O: the data packet management module separates packet header and the Data payload of the data packet；

4P: the data packet management module is written from the memory read data in the high-speed read-write data module.