CN104572537B - A kind of fault-tolerant master-slave synchronisation serial communication system based on FPGA - Google Patents
A kind of fault-tolerant master-slave synchronisation serial communication system based on FPGA Download PDFInfo
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Abstract
The present invention provides a kind of fault-tolerant master-slave synchronisation serial communication system based on FPGA, including a master station module, one or more slave station modules and two serial communication links, each serial communication link includes synchronised clock passage and data channel, master station module utilizes the synchronised clock of synchronised clock channel transfer with slave station module, realizes the synchronous reception for the serialized data that data channel is transmitted and synchronous transmission.Fault-tolerant master-slave synchronisation serial communication system provided by the invention based on FPGA, using the fault-tolerant communication of dual link, improve the reliability of serial communication system；Realize that the synchronous of serialized data receives and the synchronous efficiency of transmission for sending, improving serial communication system using synchronised clock；Channel selecting module selects a serial communication link to be used to receive data, while detects the communication state of another serial communication link in real time, it is achieved thereby that the real-time detection of the communication state of serial communication link, the failure no-harass switch of serial communication link.
Description
Technical field
Fault-tolerant communication in being applied the present invention relates to industry spot, more particularly to a kind of fault-tolerant master-slave synchronisation based on FPGA
Serial communication system.
Background technology
In industrial control field, with the continuous improvement of technical merit, various field bus techniques are developed, such as
PROFIBUS, CAN etc., but principal and subordinate's bus based on RS485 is still widely adopted because it is simple ripe.
RS485 both threads, using differential signal negative logic ,+2V~+6V represents " 0 ", and -6V~-2V represents " 1 ".Based on master
From the topological structure of daisy chain form shown in the serial communication link of bussing technique design generally use Fig. 1, the topological structure
There is a host node, from node, it is simultaneous to depend on transmission range, transmission rate, cable quality and electromagnetism from node number with multiple
Hold the factors such as environment.
The corresponding relation of master-Slave Protocol and the layer protocols of ISO/OSI seven is as shown in figure 1, seven layers of Fig. 1 master-Slave Protocols and ISO/OSI
The graph of a relation of agreement uses the agreements of EIA/TIA 485 in physical layer.Data link layer is defined by serial data link protocol, serially
SDL is master-Slave Protocol.
Self-defined application layer protocol is located at the 7th layer of ISO/OSI, there is provided the C/ being connected between each equipment in bus
S communicates.Client corresponds to host node, and server is corresponding from node.Master-Slave Protocol serial data link protocol is master-Slave Protocol, only
One host node is connected in a bus simultaneously with one or more from node, and host node is responsible for the initiation of order, from node
Receive and order and respond, can just respond when host node order is only received from node, can not be in communication with each other between node.
In typical case as shown in Figure 2, it is characterized in carrying out asynchronous serial communication, topology knot using single communication link
Structure advantage is simply to be easily achieved, and shortcoming is that reliability is low, efficiency of transmission is low.
In industry spot application, reliability and real-time are a very important indexs, how to be improved using RS485
The reliability and real-time of serial communication link, it is the important content for needing to study.
Fig. 3 is asynchronous serial communication data transfer schematic diagram, and main website is sent between data and the response data for receiving slave station
Time interval t be to include multiple clock cycle, time interval t is Millisecond.In the event of time-out, time interval t will more
It is long, thus cause the data transmission efficiency of asynchronous serial communication very low.
Those skilled in the art are directed to providing a kind of communication system using RS485 serial communication links, and this is serial logical
It is high to interrogate system reliability, and efficiency of transmission is high.
The content of the invention
The shortcomings that reliability is low, efficiency of transmission is low, is had based on the mono- communication links of RS485 for conventional, the present invention carries
A kind of fault-tolerant master-slave synchronisation serial communication system based on FPGA is gone out, its outstanding feature is：With fault-tolerant dual link, dual link
Automatic detection, automatic switchover, improve the reliability of serial communication system；Using synchronous serial communication, serial communication system is improved
Efficiency of transmission.
Fig. 4 is synchronous serial communication data transfer schematic diagram, the data that main website is sent and the data of the response of reception slave station
Between time interval t be a clock cycle, can accomplish it is several delicate, with the asynchronous serial communication data transfer in Fig. 3
Millisecond stage time interval compare, the efficiency of transmission of communication system can be effectively improved.
In the fault-tolerant master-slave synchronisation serial communication system based on FPGA of the present invention, each link includes two passages, and one
Individual to be used to transmit synchronised clock, one is used to transmit data, and the physical layer of each passage uses RS485, and data link layer uses
Serial data transmission.
Fault-tolerant another outstanding feature of master-slave synchronisation serial communication system based on FPGA of the present invention is to use logic core
Piece FPGA realizes that above-mentioned institute is functional.
FPGA indoor designs channel selecting module is selected dual serial communication link, selects a serial communication chain
Road is used to receive data, while detects the communication state of another serial communication link in real time.Once for receiving the serial of data
Communication link breaks down, and the communication of another serial communication link is normal, automatic to carry out serial communication link switching, so as to realize
The real-time detection of the communication state of serial communication link, the failure no-harass switch of serial communication link.
The present invention provides a kind of fault-tolerant master-slave synchronisation serial communication system based on FPGA, and the fault-tolerant principal and subordinate based on FPGA is same
Step serial communication system includes a master station module, one or more slave station modules and two serial communication links, main website mould
Block is connected with two serial communication links respectively with slave station module, and each serial communication link includes synchronised clock passage and data
Passage, master station module utilize the synchronised clock of synchronised clock channel transfer with slave station module, realize the serial of data channel transmission
Change the synchronous of data to receive and synchronously send, master station module also includes being used to provide synchronised clock synchronous generator.
Further, slave station module includes channel selecting module, and channel selecting module is used to select two serial communication chains
It is one in road, synchronous to receive serialized data and/or synchronous transmission serialized data.
The first serial communication link of acquiescence selection when channel selecting module is initial, if the first serial communication link receives just
Often, the first serial communication link of selection is received；It is serial logical according to first if the reception of the first serial communication link is abnormal
Interrogate the communication state testing result of link, it is determined whether need to switch.
Further, slave station module includes the first receiving module and the second receiving module, the first receiving module is used to receiving,
The data that verification is sent with storage master station module, the second receiving module are used for the communication state for detecting serial communication link.
Further, the data channel for the serial communication link that the first receiving module is chosen with channel selecting module is connected,
To receive, verify the data sent with storage master station module.
Further, the data channel of the second receiving module and the unchecked serial communication link of channel selecting module connects
Connect, so as to the communication state of the unchecked serial communication link of sense channel selecting module.
Fault-tolerant master-slave synchronisation serial communication system provided by the invention based on FPGA, the choosing of the second receiving module receiving channel
The data of the data channel transmission of the unchecked serial communication link of module are selected, and CRC check is carried out to the data of reception, if
Verification passes through, it is believed that the unchecked serial communication link communication of channel selecting module is normal, otherwise it is assumed that channel selecting module is not
The serial communication link communication abnormality chosen.
Further, the first receiving module does not receive valid data within the time of setting, if the second receiving module is examined
When the communication state of the survey unchecked serial communication link of channel selecting module is normal, channel selecting module carries out serial communication
Link switching.
Fault-tolerant master-slave synchronisation serial communication system provided by the invention based on FPGA, when the first receiving module is in setting
Valid data are can not receive in time, current serial communication link communication abnormality are represented, at this moment if the second receiving module detects
The communication of another serial communication link is normal, that is, when the unchecked serial communication link communication of channel selecting module is normal,
The serial communication link of channel selecting module selection changes into another serial communication link, that is, link switching is carried out, so as to ensure
Communication is normally carried out, and improves the reliability of the fault-tolerant master-slave synchronisation serial communication system of the present embodiment.
Further, the first receiving module and the data channel for the serial communication link chosen after channel selecting module switching
Connection, the data channel of unchecked serial communication link is connected after the second receiving module switches with channel selecting module.
Further, slave station module also includes address offset computing module, based on the offset address of data storage areas
Calculate.
Further, slave station module also includes sending module, and serialized data is sent for synchronous.
Compared with prior art, the fault-tolerant master-slave synchronisation serial communication system provided by the invention based on FPGA has following
Beneficial effect：
(1) master station module is connected with two serial communication links respectively with slave station module, using the fault-tolerant communication of dual link, is carried
The reliability of high serial communication system；
(2) channel selecting module is selected dual serial communication link, selects a serial communication link to be used to connect
Data are received, while detect the communication state of another serial communication link in real time.Once the serial communication link for receiving data
Break down, and the communication of another serial communication link is normal, it is automatic to carry out serial communication link switching, it is achieved thereby that serial logical
Interrogate the real-time detection of the communication state of link, the failure no-harass switch of serial communication link；
(3) synchronous receive for realizing serialized data using synchronised clock sends with synchronous, improves serial communication system
Efficiency of transmission.
Brief description of the drawings
Fig. 1 is the graph of a relation of master-Slave Protocol and the layer protocols of ISO/OSI seven；
Fig. 2 is the topology diagram of serial communication system daisy chain form in the prior art；
Fig. 3 is asynchronous serial communication data transfer schematic diagram；
Fig. 4 is synchronous serial communication data transfer schematic diagram；
Fig. 5 is the topology diagram of the fault-tolerant master-slave synchronisation serial communication system of one embodiment of the present of invention；
Fig. 6 is the functional block diagram of the master station module of the fault-tolerant master-slave synchronisation serial communication system shown in Fig. 5；
Fig. 7 is the functional block diagram of the slave station module of the fault-tolerant master-slave synchronisation serial communication system shown in Fig. 5；
Fig. 8 is the user equipment of the slave station module of the fault-tolerant master-slave synchronisation serial communication system shown in Fig. 5；
Fig. 9 is the function of the first receiving module of the slave station module of the fault-tolerant master-slave synchronisation serial communication system shown in Fig. 5
Block diagram；
Figure 10 is the function of the second receiving module of the slave station module of the fault-tolerant master-slave synchronisation serial communication system shown in Fig. 5
Block diagram；
Figure 11 is the functional block diagram of the slave station module sending module of the fault-tolerant master-slave synchronisation serial communication system shown in Fig. 5；
Figure 12 is the transmission state machine of the slave station module of the fault-tolerant master-slave synchronisation serial communication system shown in Fig. 5；
Figure 13 is the address offset computing module of the slave station module of the fault-tolerant master-slave synchronisation serial communication system shown in Fig. 5
Functional block diagram.
Embodiment
As shown in figure 5, the fault-tolerant master-slave synchronisation serial communication system based on FPGA of one embodiment of the present of invention, including
One master station module, one or more slave station modules and two serial communication links, master station module and slave station module respectively with
The connection of two serial communication links, each serial communication link include synchronised clock passage and data channel, master station module and from
Module of standing utilizes the synchronised clock of synchronised clock channel transfer, realize data channel transmission serialized data it is synchronous receive and
It is synchronous to send.
Using master-slave communication mode, master station module and slave station module are connected with two communication links respectively, every communication link
The physical layer on road is to be based on RS485, and the serially-transmitted data link layer of master station module and slave station module is all realized using FPGA.
Master station module configuring redundancy serial communication link, each serial communication link include two passages, and a passage is
Synchronised clock passage, for transmitting synchronised clock, another passage is serialized data passage.
As shown in fig. 6, each serial communication link is functionally, including 1 sending module, 1 receiving module, reading
Control module and synchronous generator are write, read/write control module realizes the read-write operation to dual port RAM；Synchronised clock is sent out
Raw device is used to provide synchronised clock for the serialized transport of data, and the synchronizing clock signals are received and made by all slave station modules
With.
Due to for all slave station modules, being serialized using a synchronised clock, and by synchronised clock
The reception and transmission of data, serialized data Asynchronous Reception and the time interval sent are reduced, improve the efficiency of communication.
The design of slave station module is the core of the present invention, because Diagnosis of Links, synchrodata send and receive, data school
Test, the function such as link switching is all to realize on that module.
As shown in fig. 7, slave station module is connected with dual serial communication link, mould is received comprising the first receiving module, second
Block, sending module, channel selecting module, synchronous signal receiver module, RAM module and address offset computing module etc..
First receiving module of slave station module is used to receive, verifies the serial communication chain selected with memory channel selecting module
The data of the data channel transmission on road.
Second receiving module of slave station module is used for the communication state for detecting another serial communication link, judges at another
Whether communication link has effective data communication to occur, if valid data communication is occurring, then represent in addition
One communication link structural integrity, function are normal.
The channel selecting module of slave station module is used to select one in two serial communication links, synchronous to receive serialization
Data and/or synchronous transmission serialized data.Using the synchronizing clock signals of the main website received, receive serialized data and deposit
Storage the data read-out in dual port RAM and carries out synchronous serial transmission in dual port RAM.
Synchronous signal receiver module is used for the synchronised clock for receiving synchronised clock channel transfer, so that each module uses, its
Annexation is not shown in FIG. 7.
Fig. 8 is the user equipment of the slave station module of the fault-tolerant master-slave synchronisation serial communication system of the present embodiment, including 8
State：
(1) when the receiving module of the first receiving module/second is not detected by start bit, in " free time " state, when first
When receiving module detects start bit, it is changed into " receiving state 1 " from " free time " state；
The receiving module of (2) first receiving modules/second " receive state 1 " and receive 8 data, when receiving full 1 byte,
" receive state 1 " and be changed into " inspection state 0 "；
The receiving module of (3) first receiving modules/second " inspection state 0 " checks stop position, after checking stop position, by
" inspection state 0 " is changed into " initial state 1 "；
The receiving module of (4) first receiving modules/second " initial state 1 ", check start bit, after checking start bit,
From " initial state 1 " is changed into " reception state 1 "；
The receiving module of (5) first receiving modules/second " reception state 1 " receives 8 data, when receiving full 1 byte,
From " reception state 1 " is changed into " inspection state 1 "；
The receiving module of (6) first receiving modules/second " inspection state 1 " checks stop position, after checking stop position, by
" inspection state 1 " is changed into " initial state 0 "；
The receiving module of (7) first receiving modules/second " initial state 0 ", detect start bit, when start bit is correct,
From " initial state 0 " is changed into " reception state 0 "；When being not detected by wrong in start bit or original state, by " initial state
0 " is changed into " waiting " state；
The receiving module of (8) first receiving modules/second waits a clock cycle, is changed into " free time " in " wait " state
State.
First receiving module is completed to connect from data channel as shown in figure 9, under the scheduling of the user equipment shown in Fig. 8
The functions such as function decoding, CRC check, data receiver, address offset calculating and the RAM accesses of data of the data of receipts；Function
Code output function data are solved, are sent to address offset computing module, are calculated for address offset；CRC check module output data
Effective marker position, is sent to channel selecting module, for walking the selection of communication link.
Second receiving module is as shown in Figure 10, under the scheduling of the user equipment shown in Fig. 8, completes to connect from verification passage
The function decoding and CRC check of the data of receipts, output data effective marker position.
When the first receiving module can not receive valid data within the regular hour, expression Current communications link is abnormal, at this moment
If the second receiving module detects that another communication link is normal, link switching is carried out, so as to ensure that communication is normally carried out, is carried
The high reliability of the fault-tolerant master-slave synchronisation serial communication system of the present embodiment.
The sending module of slave station module is as shown in figure 11, and it runs under the scheduling for sending state machine shown in Figure 12.
Figure 12 is the transmission state machine of the slave station module of the fault-tolerant master-slave synchronisation serial communication system of the present embodiment, including 8
Individual state：
(1) when sending module, which is not detected by transmission, enables effective, in " free time " state, when sending module detects hair
When sending enabled effective, it is changed into " waiting " from " free time " state；
(2) sending module is delayed a clock cycle, is changed into " initial state 0 " in " wait " state；
(3) sending module " initial state 0 ", is sending start bit and is being loaded into data, from " initial state 0 " is changed into " sending
The state of state 0 "；
(4) sending module " is sending state 0 " and is sending 8 data, when having sent 1 byte, " sending state 0 " to be changed into
" halted state 0 "；
(5) sending module is in " the transmission stop position of halted state 0 ", from " halted state 0 " is changed into " initial state 1 "；
(6) sending module is in " the transmission start bit of initial state 1 ", from " initial state 1 " is changed into " sending state 1 "；
(7) sending module " is sending state 1 " and is sending 8 data, when having sent 1 byte, from " reception state 1 " is changed into
" halted state 1 "；
(8) sending module is in " the transmission stop position of halted state 1 " a, if frame data are sent, by " halted state 1 "
It is changed into " free time "；If continue to send the remaining data of present frame, from " halted state 1 " is changed into " initial state 1 ".
First receiving module does not receive valid data within the time of setting, it is believed that the communication state of communication link is different
Often, if the communication state that the second receiving module detects another serial communication link is normal, channel selecting module selection
Serial communication link changes into another serial communication link.
The slave station module of slave station module also includes address offset computing module, as shown in figure 13, for data storage areas
Offset address calculate.
Because different performance datas has different data structure and length, address offset computing module is first by function
Data buffer storage, type of the decoding module according to performance data is then combined, calculate the first address skew of performance data.
Fault-tolerant master-slave synchronisation serial communication system provided by the invention based on FPGA, master station module are distinguished with slave station module
It is connected with two serial communication links, using the fault-tolerant communication of dual link, improves the reliability of serial communication system；Channel selecting mould
Block is selected dual serial communication link, selects a serial communication link to be used to receive data, while detection is another in real time
The communication state of one serial communication link.Once broken down for the serial communication link for receiving data, and it is another serial logical
It is normal to interrogate link communication, it is automatic to carry out serial communication link switching, it is achieved thereby that the reality of the communication state of serial communication link
When detect, the failure no-harass switch of serial communication link；The synchronous reception and synchronization of serialized data are realized using synchronised clock
Send, improve the efficiency of transmission of serial communication system.
Preferred embodiment of the invention described in detail above.It should be appreciated that the ordinary skill of this area is without wound
The property made work can makes many modifications and variations according to this design of the invention.Therefore, all technology people in the art
Member passes through logic analysis, reasoning or the limited technical side to obtain on the basis of existing technology according to the design of this present invention
Case, all should be in the protection domain being defined in the patent claims.
Claims (3)
- A kind of 1. fault-tolerant master-slave synchronisation serial communication system based on FPGA, it is characterised in that the fault-tolerant master based on FPGA Include a master station module, one or more slave station modules and two serial communication links, institute from synchronizing serial communication system State master station module to be connected with two serial communication links respectively with the slave station module, each serial communication link bag Synchronised clock passage and data channel are included, the master station module utilizes the synchronised clock channel transfer with the slave station module Synchronised clock, realize that the synchronous of serialized data of the data channel transmission receives and synchronously sent, the master station module is also Including for providing the synchronised clock synchronous generator；The slave station module includes channel selecting module, and the channel selecting module is used to select two serial communication links In one, it is synchronous to receive serialized data and/or synchronous send serialized data；The slave station module includes the first receiving module and the second receiving module, and first receiving module is used to receive, verify The data sent with storing the master station module, second receiving module are used for the communication state for detecting serial communication link；The data channel for the serial communication link that first receiving module is chosen with the channel selecting module is connected, to connect Receive, the data that verification is sent with storing the master station module；Second receiving module is connected with the data channel of the unchecked serial communication link of the channel selecting module, so as to Detect the communication state of the unchecked serial communication link of the channel selecting module；First receiving module does not receive valid data within the time of setting, if described in second receiving module detection When the communication state of the unchecked serial communication link of channel selecting module is normal, the channel selecting module is serially led to Interrogate link switching；The data channel for the serial communication link that first receiving module is chosen after switching with the channel selecting module is connected, The data channel of unchecked serial communication link is connected after second receiving module switches with the channel selecting module.
- 2. the fault-tolerant master-slave synchronisation serial communication system based on FPGA as claimed in claim 1, it is characterised in that the slave station Module also includes address offset computing module, and the offset address for data storage areas calculates.
- 3. the fault-tolerant master-slave synchronisation serial communication system based on FPGA as claimed in claim 1, it is characterised in that the slave station Module also includes sending module, and serialized data is sent for synchronous.
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| CN107632554B (en) * | 2017-10-20 | 2024-07-05 | 江苏汉武智能科技有限公司 | Master-slave control circuit for personnel channel |
| CN112653734B (en) * | 2020-12-11 | 2023-09-19 | 邦彦技术股份有限公司 | Real-time master-slave control and data synchronization system and method for server cluster |
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| EP1229677A2 (en) * | 2000-12-11 | 2002-08-07 | Alcatel USA, Inc. | Failover apparatus and method for an asynchronous data communication network |
| CN101232357A (en) * | 2008-02-27 | 2008-07-30 | 北京佳讯飞鸿电气股份有限公司 | Apparatus and method for realizing main and spare plate card rearrange |
| CN101807986A (en) * | 2010-04-20 | 2010-08-18 | 杭州和利时自动化有限公司 | Realization method and device of redundant serial bus |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1229677A2 (en) * | 2000-12-11 | 2002-08-07 | Alcatel USA, Inc. | Failover apparatus and method for an asynchronous data communication network |
| CN101232357A (en) * | 2008-02-27 | 2008-07-30 | 北京佳讯飞鸿电气股份有限公司 | Apparatus and method for realizing main and spare plate card rearrange |
| CN101807986A (en) * | 2010-04-20 | 2010-08-18 | 杭州和利时自动化有限公司 | Realization method and device of redundant serial bus |
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