CN104598430A - Network interface interconnection design and control system of CPU interconnection expansion system - Google Patents
Network interface interconnection design and control system of CPU interconnection expansion system Download PDFInfo
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Abstract
The invention particularly relates to a network interface interconnection design and control system of a CPU interconnection expansion system. The network interface interconnection design and control system of the CPU interconnection expansion system realizes the interaction of internal protocol messages among a plurality of CPU interconnection expansion systems by interconnecting through network interfaces on respective boards, encapsulates the messages processed by the CACHE consistency processing module into network link layer messages and sends the network link layer messages to a link, and simultaneously receives the messages from the network link and converts the messages into internal message formats to be sent to the CACHE consistency processing module. The network interface interconnection design and control system of the CPU interconnection expansion system fully utilizes the channel capacity of a transmission medium, reduces the number of required transmission channels and device pins, realizes the interaction of internal protocol messages among a plurality of CPU interconnection expansion systems, and greatly reduces the communication cost.
Description
Technical field
The present invention relates to the communication technology and the interconnected processing technology field of CPU CACHE, particularly the network interface Networking Design of the interconnected expanding system of a kind of CPU and control system.
Background technology
Server, as the node of network, stores, processes data, the information of on network 80%, be therefore also referred to as the soul of network.Do a vivid metaphor: server similarly is the switch of post office, and microcomputer, notebook, PDA, mobile phone etc. are fixing or the network terminal of movement, as being scattered in the telephone set at the places such as family, various office space, public place.Communication on telephone in daily life, work, communication, have to pass through switch, could arrive target phone.In like manner, network-termination device, as the microcomputer online in family, enterprise, obtains information, links up with the external world, amusement etc., and also having to pass through server, is therefore alternatively that server is at " tissue " and " leader " these equipment.It a kind ofly on network provides the high performance computing machine of various service for client computer, it is under the control of network operating system, the customer rs site that coupled hard disk, tape, printer, Modem and various special communication equipment are supplied on network is shared, also can provide centralized calculation for the network user, information delivers and the service such as data management.Its high-performance is mainly reflected in arithmetic capability, for a long time aspect such as reliability service, powerful external data handling capacity of high speed.
Along with the dominant frequency of CPU is more and more higher, CPU external interface QPI, KTI etc., its speed all reaches 6.4G to 10G or higher.But what its single cpu exported tells external interface quantity little, be not suitable for extensive CPU integrated combination and become a large CPU cluster job, Traditional parallel interfacing becomes the bottleneck improving message transmission rate further.Replacing Traditional parallel bus and becoming the main flow of high-speed interface technology.
Summary of the invention
The present invention, in order to make up the defect of prior art, provides network interface Networking Design and the control system of the interconnected expanding system of a kind of brief, efficient CPU.
The present invention is achieved through the following technical solutions:
The network interface Networking Design of the interconnected expanding system of a kind of CPU and control system, it is characterized in that: divide according to network layer, by interconnected for CPU expanding system by respective plate is divided into 4 levels from top to bottom with network interface, be respectively application layer, protocol layer, link layer and Physical layer; Described application layer, transfers to protocol layer process to CACHE consistency treatment module, CACHE nonuniformity processing module transmitting-receiving message after carrying out classification process; Described protocol layer contains N number of router table means, sends request arbitrator module, and message application layer received and dispatched is filled or rejected route field information; Described link layer, has M different type of message to arrange the individual different virtual channel of M according to built-in message, completes the mapping of M virtual channel to T road high speed serdes simultaneously; Described Physical layer, for realizing initialization and the basic coding operation of serdes.M, N, T are natural number.
Described application layer specifically comprises CACHE consistance message and submits to module, CACHE nonuniformity message to submit module, application layer credit processing module, error check module, CACHE consistance message sending module, CACHE nonuniformity message sending module and message packet package module to;
Described CACHE consistance message submits module to: by after application layer credit processing module, error check module process from described protocol layer CACHE consistance packet storage to a degree of depth be 128, width is in the FIFO of 256, submit to and process according to the demand of CACHE consistency treatment resume module;
Described CACHE nonuniformity message submits module to: by after application layer credit processing module, error check module process from described protocol layer CACHE nonuniformity packet storage to a degree of depth be 128, width is in the FIFO of 128, submit to and process according to the demand of CACHE consistency treatment resume module;
Described application layer credit processing module: it is CACHE consistance message, CACHE nonuniformity message or fault-tolerant instruction message that the network message received from protocol layer is distinguished according to information its heading, and it is submitted to respectively described CACHE consistance message and submit to module, described CACHE nonuniformity message to submit module and described error check module to;
Described CACHE consistance message sending module: receive the CACHE consistance message that CACHE consistency treatment module exports, and by CACHE consistance packet storage to a degree of depth be 128, width is in the FIFO of 256, the demand according to described message package module is submitted to and its process;
Described CACHE nonuniformity message sending module: receive the CACHE nonuniformity message that CACHE consistency treatment module exports, and by CACHE nonuniformity packet storage to a degree of depth be 128, width is in the FIFO of 128, the demand according to described message package module is submitted to and its process;
Described message packet package module, is encapsulated into different heading information according to the difference of type of message.
Described type of message comprises 6 six large classes, wherein HOME message comprise request message and monitor response message, message is monitored in the representative of SNP message, the representative of NDR message request, response, read-write etc. have operated message, DRS message represent carry data message, NCB represents and writes message, the NCS literary composition of reading the newspaper not with data not with data;
The heading packaging information of described message type is respectively the register of 128, it is low 6, that is: 6 ' b000001 represents HOME message, 6 ' b000010 represents SNP message, 6 ' b000100 represents NDR message, and 6 ' b001000 represents DRS message, and 6 ' b010000 represents NCB message, 6 ' b100000 represents NCS message, and this message packet header and described network message header according to claim 2 combine the whole heading information of composition.
Described application layer credit processing module is the register of 128 bit widths from the network message header that protocol layer receives, it is low 3, is that 3 ' b001 represents CACHE consistance message, 3 ' b010 represents CACHE nonuniformity message, 3 ' b100 represents fault-tolerant instruction message respectively;
Described error check module: if receive the signal of described application layer credit processing module submission, the direct submittal error information of described error check module, and 4 to 6 that revise the network message header of 128 is 3 ' b111, adds message encapsulation format simultaneously and pass to protocol layer process.
Described protocol layer specifically comprises routing table access control logic module and sends request arbitrator module;
Described routing table access control logic module: 8 to 64 regions route searching result being put into message packet head, need to return to far-end link in the time lift-launch of organizing messages message, error handle, if desired packet loss, handle link wait timeout etc. are carried out to the message being sent to self simultaneously;
The described arbitrator module that sends request is made up of a group state machine, the routing iinformation obtained according to routing table access control logic module and the error message of message type and error check module transmission come mapping from scheduling arbitration message flow to T road high speed serdes one of them.
The mapping of described T road high speed serdes has a link layer separately, and described link layer specifically comprises pseudo channel and divides and message storage module, and pseudo channel sends request moderator.
Described pseudo channel divides and message storage module: set up T virtual channel according to the mapping of T road high speed serdes, simultaneously by heading information, CACHE consistance message information and CACHE nonuniformity message information are bundled in respective virtual channel station according to the mapping of T road high speed serdes, and enable signal is sent to pseudo channel sends request moderator;
Described pseudo channel sends request moderator: according to the enable signal that pseudo channel divides and message storage module provides, and forwards the mapping circulation of T road high speed serdes.
Described Physical layer is a Physical Coding Sublayer with high bandwidth, low delay, the highly reliable and flexible feature of height, for the data by link layer, receiving end is propagated into through maximum T road high speed serdes, and carry out alignment and the restructuring of data, link layer specifically comprises derdes reset processing module, serdes polarity, synchronous alignment and restructuring processing module, crc processing module Reinforced turf processing module;
Institute serdes reset processing module: produce Global reset, resets in order to control whole network interface.The of-step signal produced according to described serdes polarity, synchronous alignment and restructuring processing module in addition produces serdes Self-resetting signal, and control serdes restarts;
Described serdes polarity, synchronous alignment and restructuring processing module: judge serdes positive-negative polarity, to recombinate effective data packets according to the alignment of synchronous head;
Described crc processing module: CRC check data message being done to 32bit, in order to judge the transmission correctness checking of link;
Described Reinforced turf processing module: produce Reinforced turf algorithm routine, to data message scrambling, descrambling according to 64/66 encoding and decoding principle.
The invention has the beneficial effects as follows: the network interface Networking Design of the interconnected expanding system of this CPU and control system, take full advantage of the channel capacity of transmission medium, decrease required transmission channel and device pin number, not only achieve the mutual of internal agreement message between the interconnected expanding system of multiple CPU, also greatly reduce communications cost.
Accompanying drawing explanation
Accompanying drawing 1 is protocol layer, link layer and physical layer architecture schematic diagram in invention logical level structure.
Accompanying drawing 2 is application layer structure schematic diagram in invention logical level structure.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be described in detail.
The network interface Networking Design of the interconnected expanding system of this CPU and control system, divide according to network layer, by interconnected for CPU expanding system by respective plate is divided into 4 levels from top to bottom with network interface, be respectively application layer, protocol layer, link layer and Physical layer; Described application layer, transfers to protocol layer process to CACHE consistency treatment module, CACHE nonuniformity processing module transmitting-receiving message after carrying out classification process; Described protocol layer contains N number of router table means, sends request arbitrator module, and message application layer received and dispatched is filled or rejected route field information; Described link layer, has M different type of message to arrange the individual different virtual channel of M according to built-in message, completes the mapping of M virtual channel to T road high speed serdes simultaneously; Described Physical layer, for realizing initialization and the basic coding operation of serdes.
Described application layer specifically comprises CACHE consistance message and submits to module, CACHE nonuniformity message to submit module, application layer credit processing module, error check module, CACHE consistance message sending module, CACHE nonuniformity message sending module and message packet package module to;
Described CACHE consistance message submits module to: by after application layer credit processing module, error check module process from described protocol layer CACHE consistance packet storage to a degree of depth be 128, width is in the FIFO of 256, submit to and process according to the demand of CACHE consistency treatment resume module;
Described CACHE nonuniformity message submits module to: by after application layer credit processing module, error check module process from described protocol layer CACHE nonuniformity packet storage to a degree of depth be 128, width is in the FIFO of 128, submit to and process according to the demand of CACHE consistency treatment resume module;
Described application layer credit processing module: it is CACHE consistance message, CACHE nonuniformity message or fault-tolerant instruction message that the network message received from protocol layer is distinguished according to information its heading, and it is submitted to respectively described CACHE consistance message and submit to module, described CACHE nonuniformity message to submit module and described error check module to;
Described CACHE consistance message sending module: receive the CACHE consistance message that CACHE consistency treatment module exports, and by CACHE consistance packet storage to a degree of depth be 128, width is in the FIFO of 256, the demand according to described message package module is submitted to and its process;
Described CACHE nonuniformity message sending module: receive the CACHE nonuniformity message that CACHE consistency treatment module exports, and by CACHE nonuniformity packet storage to a degree of depth be 128, width is in the FIFO of 128, the demand according to described message package module is submitted to and its process;
Described message packet package module, is encapsulated into different heading information according to the difference of type of message.
Described type of message comprises 6 six large classes, wherein HOME message comprise request message and monitor response message, message is monitored in the representative of SNP message, the representative of NDR message request, response, read-write etc. have operated message, DRS message represent carry data message, NCB represents and writes message, the NCS literary composition of reading the newspaper not with data not with data;
The heading packaging information of described message type is respectively the register of 128, it is low 6, that is: 6 ' b000001 represents HOME message, 6 ' b000010 represents SNP message, 6 ' b000100 represents NDR message, and 6 ' b001000 represents DRS message, and 6 ' b010000 represents NCB message, 6 ' b100000 represents NCS message, and this message packet header and described network message header according to claim 2 combine the whole heading information of composition.
Described application layer credit processing module is the register of 128 bit widths from the network message header that protocol layer receives, it is low 3, is that 3 ' b001 represents CACHE consistance message, 3 ' b010 represents CACHE nonuniformity message, 3 ' b100 represents fault-tolerant instruction message respectively;
Described error check module: if receive the signal of described application layer credit processing module submission, the direct submittal error information of described error check module, and 4 to 6 that revise the network message header of 128 is 3 ' b111, adds message encapsulation format simultaneously and pass to protocol layer process.
Described protocol layer specifically comprises routing table access control logic module and sends request arbitrator module;
Described routing table access control logic module: 8 to 64 regions route searching result being put into message packet head, need to return to far-end link in the time lift-launch of organizing messages message, error handle, if desired packet loss, handle link wait timeout etc. are carried out to the message being sent to self simultaneously;
The described arbitrator module that sends request is made up of a group state machine, the routing iinformation obtained according to routing table access control logic module and the error message of message type and error check module transmission come mapping from scheduling arbitration message flow to T road high speed serdes one of them.
The mapping of described T road high speed serdes has a link layer separately, and described link layer specifically comprises pseudo channel and divides and message storage module, and pseudo channel sends request moderator.
Described pseudo channel divides and message storage module: set up T virtual channel according to the mapping of T road high speed serdes, simultaneously by heading information, CACHE consistance message information and CACHE nonuniformity message information are bundled in respective virtual channel station according to the mapping of T road high speed serdes, and enable signal is sent to pseudo channel sends request moderator;
Described pseudo channel sends request moderator: according to the enable signal that pseudo channel divides and message storage module provides, and forwards the mapping circulation of T road high speed serdes.
Described Physical layer is a Physical Coding Sublayer with high bandwidth, low delay, the highly reliable and flexible feature of height, for the data by link layer, receiving end is propagated into through maximum T road high speed serdes, and carry out alignment and the restructuring of data, link layer specifically comprises derdes reset processing module, serdes polarity, synchronous alignment and restructuring processing module, crc processing module Reinforced turf processing module;
Institute serdes reset processing module: produce Global reset, resets in order to control whole network interface.The of-step signal produced according to described serdes polarity, synchronous alignment and restructuring processing module in addition produces serdes Self-resetting signal, and control serdes restarts;
Described serdes polarity, synchronous alignment and restructuring processing module: judge serdes positive-negative polarity, to recombinate effective data packets according to the alignment of synchronous head;
Described crc processing module: CRC check data message being done to 32bit, in order to judge the transmission correctness checking of link;
Described Reinforced turf processing module: produce Reinforced turf algorithm routine, to data message scrambling, descrambling according to 64/66 encoding and decoding principle.
Be below a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The Network Interface Unit of the interconnected expanding system of CPU comprises receiving equipment and transmitting apparatus, realizes full-duplex communication between two equipment, supports that ring-like, star-like, chain connects.
As Fig. 1, shown in Fig. 2, its processing procedure of Network Interface Unit message process of transmitting of the interconnected expanding system of CPU is as follows: be shown in the FLIT receiving 236 according to the data_valid signal in 105CACHE consistance message sending module from the reception of CACHE processing module in application layer, because the data cache interface in 105 is 256, bit more than 236 bit data of affixed receipts for filling out 0, to keep the consistance of data path.According to receiving FLIT type, that is: the type of message described in claim 3, type of message is input in register (last_flit_type [5:0]), the type (H/T) of current FLIT is squeezed in current FLIT type register (current_flit_type [127:0] [5:0]) simultaneously, why mask register group, be in order to ensure message may exist can be correct in transmission speed and the unmatched situation of processing speed operation.At each rising edge clock and data_valid signal is effective time, the effective insulation type attribute farthest of time in current_flit_type is moved on in last_flit_type, the type H/T signal of current FLIT is sent in current_flit_type simultaneously and deposit.
According to the attribute of current_flit_type through the content of described message stored in association message Parasites Fauna, the attribute of such as current_flit_type is b000001, i.e. home type message, the Parasites Fauna of this message content is home_data_reg [31:0] [229:0], and this Parasites Fauna eliminates 6bit type of message attribute.Why mask register group, be in order to ensure message may exist can be correct in transmission speed and the unmatched situation of processing speed operation.For said process, define snp_data_reg [31:0] [229:0], ndr_data_reg [31:0] [229:0], drs_data_reg [31:0] [229:0], ncb_data_reg [31:0] [229:0], ncs_data_reg [31:0] [229:0] respectively.
At each rising edge clock, if there is effective attribute in last_flit_type, then effective FLIT message is sent to 201 routing table access control logic module as shown in Figure 1.
Data_valid signal in 106CACHE nonuniformity message sending module receives the FLIT of 115 from the reception of CACHE processing module, because the data cache interface in 101 is 128, bit more than 115 bit data of affixed receipts for filling out 0, to keep the consistance of data path.According to receiving FLIT type, type of message is input in register (last_flit_type [5:0]), the type (H/T) of current FLIT is squeezed in current FLIT type register (current_flit_type [127:0] [5:0]) simultaneously, why mask register group, be in order to ensure message may exist can be correct in transmission speed and the unmatched situation of processing speed operation.At each rising edge clock and data_valid signal is effective time, the effective insulation type attribute farthest of time in current_flit_type is moved on in last_flit_type, the type H/T signal of current FLIT is sent in current_flit_type simultaneously and deposit.
According to the attribute of current_flit_type through the content of described message stored in association message Parasites Fauna, the attribute of such as current_flit_type is b000001, i.e. home type message, the Parasites Fauna of this message content is home_data_reg [31:0] [108:0], and this Parasites Fauna eliminates 6bit type of message attribute.Why mask register group, be in order to ensure message may exist can be correct in transmission speed and the unmatched situation of processing speed operation.For said process, define snp_data_reg [31:0] [108:0], ndr_data_reg [31:0] [108:0], drs_data_reg [31:0] [108:0], ncb_data_reg [31:0] [108:0], ncs_data_reg [31:0] [108:0] respectively.
At each rising edge clock, if there is effective attribute in last_flit_type, then effective FLIT message is sent to 201 routing table access control logic module as shown in Figure 1.
According to flit_type==last_flit_type and snp_data_c [229:0] in 201, ndr_data_c [229:0], drs_data_c [229:0], ncb_data_c [229:0], ncs_data_c [229:0], home_data_c [229:0], these six registers represent CACHE consistance message respectively; Snp_data_nc [108:0], ndr_data_nc [108:0], drs_data_nc [108:0], ncb_data_nc [108:0], ncs_data_nc [108:0], home_data_nc [108:0], these six registers represent CACHE nonuniformity message respectively; They distinguish corresponding Parasites Fauna last_flit_type described in corresponding leading portion effective time output valve.Simultaneously in 201 with home_data_c [229:0], home_data_nc [108:0] message is that example introduces route generative process, and other message expression forms are consistent with it.
Take Installed System Memory as the space of 256G, have T=7 network interface to introduce for board, it is significant to note that the memory size in our practical work process is necessary and network interface will much larger than this quantity.The distribution formula of network interface: (memory size physical address/T+1), is divided into T+1 part by internal memory, every a corresponding corresponding network interface.Physical address as 256G is 2^38, home_data_c corresponding to it [229:166] and home_data_nc [108:45], and the address space of the 0-(32G-1) of place register distributes to the network interface of T=0; The address space of 32G-(64G-1) distributes to the network interface of T=1; Until the address space of 224G-(256G-1) distributes to the network interface of T=7.Comprehensively the above-mentioned home_data_c of learning [229:166] and home_data_nc [108:45] address are that the address space of 0-(32G-1) will hand over 203 and 204 of T=0 as shown in Figure 1 to process.
In 203 and 204 by FLIT message according to the property store of last_flit_type in the virtual channel of correspondence, submit TX Serial output to through 205 after message being sent into 107 message package modules encapsulation.
As shown in Figure 1 and Figure 2, its processing procedure of Network Interface Unit message receiving course of the interconnected expanding system of CPU is as follows: obtain heading, tail, message data and useful signal from 205 Physical layer several mouthfuls, be kept in data RAM according to message type piecemeal, the data RAM degree of depth is 128, and width is that 256(comprises 1 potential head mark and 1 tail tag will).When after rd_en or the rd_done signal receiving 201 routing table access control logic modules, data are taken out from the appropriate address of corresponding message type storage block, often read data, just send corresponding free signal to 102 application layer process modules shown in Fig. 2.As long as packet accouter is not 0, i.e. the avail signal of setable output data, often receive a rd_done signal, injunction avail Signal Fail one is clapped.When packet accouter is 0, for other situation, be then directly read from RAM.
103 error detection module process are from the error message of 205 Physical layers as shown in Figure 1 as shown in Figure 2, and by err_reset(mistake) flit_type of signal and misdata bag returns arbitration result to link layer.Send 102 application layer process modules to simultaneously, when receiving an err_reset(mistake from application layer) signal and flit_type time, if sending a part of data volume of a message, then continue to send, after last FLIT of this message is sent, by err_reset home position signal, the error handle being sent to the message of self is by judging that the information such as destination node number are to physical layer process, inform the measure of far-end receiver enforcing remedies.In link layer 203 shown in Fig. 1,204, virtual channel is unavailable or when receiving err_reset signal, and counter starts counting, virtual channel again effectively time or err_reset signal step-down time, counter O reset.If counter exceedes certain threshold value (threshold value is inputted by external signal) or now receives err_reset signal, then start to enter packet loss state.If:
1) virtual channel can be used again, and does not in fact lose message in packet loss state, and err_reset signal is not high;
2) lost a complete message, now, virtual channel can be used again, and err_reset signal is not high;
3) time-out counter is less than threshold value (expression be carry out packet loss process when receiving rework, only lose a message), and in packet loss state, does not in fact lose message or lost a complete message, then packet loss state terminates.During packet loss state, Message processing process and normal condition only have a place different, namely not transmission valid home position signal.
From RAM, directly reading message information according to above-mentioned process in 102 credit processing modules is as shown in Figure 2 stored in flit_data_reg [255:0], and according to the type of flit_type of flit_data_reg [235:230] correspondence and the low 3bit of the 128bit message of FLIT heading, i.e. flit_data_reg [131:128], distinguishing message is CACHE nonuniformity message or CACHE consistance message, is stored into respectively in relevant RAM.After 102 application layer process modules receive rd_en or the rd_done signal of 101 or 104 modules as shown in Figure 2, data are taken out from the appropriate address of corresponding message type storage block, often read data, just send corresponding free signal to 101 or 104 modules shown in Fig. 2.As long as the packet accouter of (CACHE nonuniformity message or CACHE consistance message) is not 0 separately, i.e. the avail signal of setable output data, often receives a rd_done signal, and injunction avail Signal Fail one is clapped.When packet accouter is 0, for other situation, be then directly read from RAM.
Take Installed System Memory as the space of 256G, have T=7 network interface to introduce for board, it is significant to note that the memory size in our practical work process is necessary and network interface will much larger than this quantity.The distribution formula of network interface: (memory size physical address/T+1), is divided into T+1 part by internal memory, every a corresponding corresponding network interface.Physical address as 256G is 2^38, and the attribute of flit_data_reg corresponding to it [229:166] and flit_data_reg [235:230] and flit_data_reg [131:128] judges that message is from that network interface and be the message of which kind of type.CACHE nonuniformity message submits to 104 resume module; CACHE consistance message submits to 104 resume module.
Claims (7)
1. the network interface Networking Design of the interconnected expanding system of CPU and control system, it is characterized in that: divide according to network layer, by interconnected for CPU expanding system by respective plate is divided into 4 levels from top to bottom with network interface, be respectively application layer, protocol layer, link layer and Physical layer; Described application layer, transfers to protocol layer process to CACHE consistency treatment module, CACHE nonuniformity processing module transmitting-receiving message after carrying out classification process; Described protocol layer contains N number of router table means, sends request arbitrator module, and message application layer received and dispatched is filled or rejected route field information; Described link layer, has M different type of message to arrange the individual different virtual channel of M according to built-in message, completes the mapping of M virtual channel to T road high speed serdes simultaneously; Described Physical layer, for realizing initialization and the basic coding operation of serdes.
2. the network interface Networking Design of the interconnected expanding system of CPU according to claim 1 and control system, is characterized in that: described application layer specifically comprises CACHE consistance message and submits to module, CACHE nonuniformity message to submit module, application layer credit processing module, error check module, CACHE consistance message sending module, CACHE nonuniformity message sending module and message packet package module to;
Described CACHE consistance message submits module to: by after application layer credit processing module, error check module process from described protocol layer CACHE consistance packet storage to a degree of depth be 128, width is in the FIFO of 256, submit to and process according to the demand of CACHE consistency treatment resume module;
Described CACHE nonuniformity message submits module to: by after application layer credit processing module, error check module process from described protocol layer CACHE nonuniformity packet storage to a degree of depth be 128, width is in the FIFO of 128, submit to and process according to the demand of CACHE consistency treatment resume module;
Described application layer credit processing module: it is CACHE consistance message, CACHE nonuniformity message or fault-tolerant instruction message that the network message received from protocol layer is distinguished according to information its heading, and it is submitted to respectively described CACHE consistance message and submit to module, described CACHE nonuniformity message to submit module and described error check module to;
Described CACHE consistance message sending module: receive the CACHE consistance message that CACHE consistency treatment module exports, and by CACHE consistance packet storage to a degree of depth be 128, width is in the FIFO of 256, the demand according to described message package module is submitted to and its process;
Described CACHE nonuniformity message sending module: receive the CACHE nonuniformity message that CACHE consistency treatment module exports, and by CACHE nonuniformity packet storage to a degree of depth be 128, width is in the FIFO of 128, the demand according to described message package module is submitted to and its process;
Described message packet package module, is encapsulated into different heading information according to the difference of type of message.
3. the network interface Networking Design of the interconnected expanding system of CPU according to claim 2 and control system, it is characterized in that: described type of message comprises 6 six large classes, wherein HOME message comprise request message and monitor response message, message is monitored in the representative of SNP message, the representative of NDR message request, response, read-write etc. have operated message, DRS message represent carry data message, NCB represents and writes message, the NCS literary composition of reading the newspaper not with data not with data;
The heading packaging information of described message type is respectively the register of 128, it is low 6, that is: 6 ' b000001 represents HOME message, 6 ' b000010 represents SNP message, 6 ' b000100 represents NDR message, and 6 ' b001000 represents DRS message, and 6 ' b010000 represents NCB message, 6 ' b100000 represents NCS message, and this message packet header and described network message header according to claim 2 combine the whole heading information of composition.
4. the network interface Networking Design of the interconnected expanding system of the CPU according to Claims 2 or 3 and control system, it is characterized in that: described application layer credit processing module is the register of 128 bit widths from the network message header that protocol layer receives, it is low 3, is that 3 ' b001 represents CACHE consistance message, 3 ' b010 represents CACHE nonuniformity message, 3 ' b100 represents fault-tolerant instruction message respectively;
Described error check module: if receive the signal of described application layer credit processing module submission, the direct submittal error information of described error check module, and 4 to 6 that revise the network message header of 128 is 3 ' b111, adds message encapsulation format simultaneously and pass to protocol layer process.
5. the network interface Networking Design of the interconnected expanding system of CPU according to claim 1 and control system, is characterized in that: described protocol layer specifically comprises routing table access control logic module and sends request arbitrator module;
Described routing table access control logic module: 8 to 64 regions route searching result being put into message packet head, need to return to far-end link in the time lift-launch of organizing messages message, error handle, if desired packet loss, handle link wait timeout etc. are carried out to the message being sent to self simultaneously;
The described arbitrator module that sends request is made up of a group state machine, the routing iinformation obtained according to routing table access control logic module and the error message of message type and error check module transmission come mapping from scheduling arbitration message flow to T road high speed serdes one of them.
6. the network interface Networking Design of the interconnected expanding system of CPU according to claim 1 and control system, it is characterized in that: the mapping of described T road high speed serdes has a link layer separately, described link layer specifically comprises pseudo channel and divides and message storage module, and pseudo channel sends request moderator;
Described pseudo channel divides and message storage module: set up T virtual channel according to the mapping of T road high speed serdes, simultaneously by heading information, CACHE consistance message information and CACHE nonuniformity message information are bundled in respective virtual channel station according to the mapping of T road high speed serdes, and enable signal is sent to pseudo channel sends request moderator;
Described pseudo channel sends request moderator: according to the enable signal that pseudo channel divides and message storage module provides, and forwards the mapping circulation of T road high speed serdes.
7. the network interface Networking Design of the interconnected expanding system of CPU according to claim 1 and control system, it is characterized in that: described Physical layer is a Physical Coding Sublayer with high bandwidth, low delay, the highly reliable and flexible feature of height, for the data by link layer, receiving end is propagated into through maximum T road high speed serdes, and carry out alignment and the restructuring of data, link layer specifically comprises derdes reset processing module, serdes polarity, synchronous alignment and restructuring processing module, crc processing module Reinforced turf processing module;
Institute serdes reset processing module: produce Global reset, resets in order to control whole network interface; The of-step signal produced according to described serdes polarity, synchronous alignment and restructuring processing module in addition produces serdes Self-resetting signal, and control serdes restarts;
Described serdes polarity, synchronous alignment and restructuring processing module: judge serdes positive-negative polarity, to recombinate effective data packets according to the alignment of synchronous head;
Described crc processing module: CRC check data message being done to 32bit, in order to judge the transmission correctness checking of link;
Described Reinforced turf processing module: produce Reinforced turf algorithm routine, to data message scrambling, descrambling according to 64/66 encoding and decoding principle.
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