CN104378161A - FCoE protocol acceleration engine IP core based on AXI4 bus formwork - Google Patents
FCoE protocol acceleration engine IP core based on AXI4 bus formwork Download PDFInfo
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Abstract
The invention discloses an FCoE protocol acceleration engine IP core based on an AXI4 bus formwork, and belongs to the field of Ethernet fiber channels. The FCoE protocol acceleration engine IP core based on the AXI4 bus formwork is applied to an FCoE fusion network adapter and comprises a transmitting module, a receiving module and a control module. The FCoE protocol acceleration engine IP core is based on the AXI4 bus formwork, a register is configured for the IP core through an AXI4-Lite bus, an AXI4 bus is used for reading and writing a transmitting/receiving descriptor, and an AXI4-Stream high-speed channel is used for transmitting sent/received data. The FCoE protocol acceleration engine IP core can be controlled by a CPU of the FCoE fusion network adapter, the IP core is specially used for meeting the need of FCoE data frame hardware processing in the field of Ethernet fiber channels, a full duplex operating mode is adopted, real-time performance and high efficiency are achieved in operation, the data throughout is large, the transmission rate is high, and lossless transmission can be achieved. The FCoE protocol acceleration engine IP core based on the AXI4 bus formwork can support FCoE data segmenting/merging processing and cannot damage the function of the Ethernet and simple root virtualization.
Description
Technical field
The invention belongs to Ethernet Fibre Channel technologies field, more specifically, relate to a kind of FCoE agreement accelerating engine IP kernel based on AXI4 bus architecture.
Background technology
Along with the development of the technology such as Internet of Things, cloud computing, Internet firm needs data to be processed to be explosive growth, and huge data volume needs to store efficiently and process at a high speed.In order to cater to this trend, Internet firm must set up the data center of enterprise-level.
Data center is formed by storage network (Storage Area Network, hereinafter referred to as SAN) and local area network (LAN) (Local Area Network, hereinafter referred to as LAN) fusion.Memory device and server are mainly formed network based on fiber channel protocol (Fibre Channel, FC) by SAN, fiber channel protocol be the optimal selection of storage network without frame losing, low delay, high bandwidth.LAN is formed primarily of Ethernet, and Ethernet connects simple, compatible strong, makes it be widely used in LAN.In Enterprise Data center applications, need SAN and LAN to merge, otherwise just there will be that equipment and number of cables are increased sharply, interface type is numerous and diverse, energy resource consumption is huge and the problem such as management complexity is high.Ethernet optical-fibre channel (Fibre Channel over Ethernet, hereinafter referred to as FCoE) optical-fibre channel can be mapped to Ethernet, fiber channel protocol frame is encapsulated in ethernet frame to be referred to as FCoE frame and to transmit in ethernet networks, thus SAN and LAN is merged.The FCoE network adapter needed in UNE also will be novel FCoE UNE adapter CNA card (Converged Network Adapter, CNA).
In existing network adapter scheme, the process of the Internet protocol data flow is mainly undertaken by host CPU, and network adapter just serves the effect of receiving frame or data.Owing to being present in the exchanges data of a large amount of different flow types in UNE communication, host CPU needs data volume to be processed huge, host CPU is born overweight, result in cpu performance and seriously reduce, had a strong impact on the quality of network service and the performance of main frame.
Protocol hardware accelerates to refer to the advantage utilizing hardware concurrency to calculate, and selectively the protocol processes work that part needs host CPU to complete is put on hardware and carries out, can simplify the burden of CPU like this, increase work efficiency.At present for the hardware protocol process of network adapter mainly for ICP/IP protocol, its technology and product all comparative maturities.Be directed to UNE to be exclusively used in the process of FCoE protocol hardware and to be in the starting stage, existing IP kernel scheme also has the following disadvantages:
1, UNE adapter is a network by the originally different network integrations, thus traditional Ethernet protocol can not be re-used in data link layer, New Fusion network needs the support of the harmless Ethernet protocol (Data Center Bridge, hereinafter referred to as DCB) of enhancement mode.Existing IP kernel scheme must be docked with the ethernet mac controller of DCB function with third party, and be not also used widely with the mac controller of DCB function at present, result in existing IP kernel range of application narrow, compatibility is poor, can not practical requirement;
2, existing IP kernel scheme has just carried out the process of cyclic redundancy check (CRC) (Cyclic RedundancyCheck, hereinafter referred to as CRC) and the process of frame head postamble, and protocol processes dynamics is little.In UNE, there is the data traffic FCoE frame being generally former storage network that mass data exchanges.Existing IP kernel, due to the dedicated processes module not for FCoE frame, makes host CPU still will undertake very large procotol process responsibility, thus causes host CPU performance to remain unchanged inefficiency, and UNE overall performance is very low;
3, existing IP kernel scheme supports AXI4-Lite light weight bus and AXI4 bus architecture, when carrying out mass data transmission, speed is not high, the requirement of UNE mass data high-speed transfer can not be met, link data can be caused cannot to be sent to main frame in time process, thus cause data be detained and congested, reduction network performance;
What 4, existing IP kernel scheme was not supported based on example, in hardware is virtual, and hardware based single virtual (SR-IOV) can make the direct access hardware of virtual machine environment, effectively improves performance; There is the advantage of energy-conservation, the adapter minimizing in addition of single virtualized function, simplified wiring, minimizing switch ports themselves.Existing IP kernel scheme cannot provide above advantage, and if use software virtualization also can increase the weight of the burden of host computer system completely.
Summary of the invention
For above defect or the Improvement requirement of prior art, the invention provides a kind of FCoE agreement accelerating engine IP kernel based on AXI4 bus architecture, be applied in FCoE UNE adapter.Utilize the feature of hardware concurrency process, the FCoE data processing work needing CPU to be responsible for all is put in FCoE network adapter hardware and carries out, the speed of protocol processes can be accelerated, offloading the CPU, and be aided with flow control, congestion control and single virtual (SR-IOV) support, thus the effective overall performance promoting network.
The invention provides a kind of FCoE agreement accelerating engine IP kernel based on AXI4 bus architecture, comprise sending module, receiver module and control module, wherein:
Described sending module comprises: send descriptor control unit, for transmitting transmission descriptor; Send high-speed channel control unit, for receiving data to be sent, wherein said data to be sent comprise general data and FCoE data block; Send data buffer storage unit, for the described general data that buffer memory is to be sent; Send FCoE data segmentation unit, form FCoE Frame to be sent for splitting and encapsulating described FCoE data block to be sent; Sending harmless Ethernet unit, generating and ETS scheduling for completing PFC frame; Transmit queue selected cell, for selecting to send described general data and described FCoE Frame to be sent according to described ETS scheduling; Sending data packaging unit, for encapsulating described general data to be sent and described PFC frame according to described transmission descriptor, and CRC interpolation formation frame to be sent being carried out to the Frame after encapsulation and described FCoE Frame to be sent; Send descriptor administrative unit to be used for sending descriptor described in store and management; And transmission frame buffer unit, send described frame to be sent for buffer memory;
Described receiver module comprises: received frame buffer unit, for buffer memory frame to be received; Received frame resolution unit, for completing verification to described frame to be received, resolving to form general data, type identification signal, PFC frame and FCoE Frame; Receiving queue selected cell, the described type identification signal behavior for generating according to described received frame resolution unit receives the described general data after resolving; Receive data buffer storage unit, for general data described in buffer memory; Receive FCoE data combination unit, for merging and FCoE Frame formation FCoE data block described in buffer memory; Receive harmless Ethernet unit, suspend vector for resolving PFC frame and generating to send, to suspend the transmission scheduling of particular flow rate categorical data; Receive descriptor administrative unit, receive descriptor for buffer memory and filling; Receive descriptor control unit, for looking ahead and writing back described reception descriptor; And receive high-speed channel control unit, for the FCoE data block of the general data and described reception FCoE data combination unit buffer memory that write back described reception data buffer storage unit buffer memory; And
Described control module comprises: register configuration unit, for configuring the control register being applied to described FCoE agreement accelerating engine IP kernel, and register management unit, for managing described control register, when described control register needs certain unit configuring described sending module or described receiver module, the value of described control register is sent to corresponding units by described register management unit.
In general, the above technical scheme conceived by the present invention compared with prior art, has following beneficial effect:
1, the present invention is the agreement accelerating engine IP kernel developed for the UNE adapter applied in Ethernet optical-fibre channel field specially, maximum characteristic processes needing the FCoE exchanges data of host CPU process to be put into the special FCoE processing module of IP kernel in UNE adapter, effectively reduces the burden of main frame.All FCoE UNE adapters can adopt IP kernel of the present invention to carry out hardware based FCoE data exchange processing.
2, the present invention is integrated with harmless Ethernet unit to realize the function of harmless Ethernet, high performancely can meet the requirement to bandwidth, time delay and packet loss of the different flow that transmits in UNE.IP kernel of the present invention with DCB function can be compatible with existing traditional ethernet mac controller, makes IP kernel range of application of the present invention become wide, compatible and favorable expandability.
3, the concurrency that present invention utilizes hardware calculates advantage, and in being exchanged by FCoE, a large amount of data processings is put on hardware and carries out, and effectively alleviates the burden of host CPU, obviously can promote the speed of protocol processes and the overall performance of network.
4, the present invention can support the virtual of single virtual form, hardware basedly singlely virtually can make the direct access hardware of virtual machine environment, effectively improves performance; IP kernel has the advantage of energy-conservation, the adapter minimizing in addition of single virtualized function, simplified wiring, minimizing switch ports themselves; IP kernel support single virtual can make software need not specialize based on the virtual design of pure software, effectively can reduce the burden of CPU, improve performance.
5, the present invention is based upon on AXI4 bus architecture basis, utilizes AXI4-Lite to transmit control register information, utilizes AXI4 bus transfer to receive/send descriptor, utilize AXI4-Stream channel transfer to receive/send data.The present invention is controlled by adapter cpu in network adapter; Extensibility is good, can with other IP kernel collaborative works with AXI4 bus interface and AXI4-Stream passage.
Accompanying drawing explanation
Fig. 1 is the position of agreement accelerating engine IP kernel of the present invention in FCoE UNE adapter and Module Division schematic diagram;
Fig. 2 is the structured flowchart of agreement accelerating engine IP kernel sending module of the present invention;
Fig. 3 is the structured flowchart of agreement accelerating engine IP kernel receiver module of the present invention;
Fig. 4 is the structured flowchart of agreement accelerating engine IP kernel control module of the present invention;
Fig. 5 is the schematic diagram that agreement accelerating engine IP kernel of the present invention sends data flow;
Fig. 6 is the schematic diagram of agreement accelerating engine IP kernel receiving data stream of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.In addition, if below in described each execution mode of the present invention involved technical characteristic do not form conflict each other and just can mutually combine.
IP kernel of the present invention is based upon on AXI4 bus architecture basis, AXI4-lite bus is utilized to be configured IP kernel register of the present invention, AXI4 bus is utilized to carry out send/receive the read-write of descriptor, utilize AXIS-Stream high-speed data channel to transmit the data of sending/receiving, under the control of UNE adapter cpu, complete reception/sending function.
Figure 1 shows that the position of agreement accelerating engine IP kernel of the present invention in FCoE UNE adapter and Module Division schematic diagram.As shown in Figure 1, IP kernel of the present invention is applied to FCoE UNE adapter inner, work is carried out under the control of UNE adapter cpu, its data path can connect other IP kernels (such as direct memory access (Direct Memory Access in one end, hereinafter referred to as DMA) controller etc.), the other end connects 10G ethernet mac controller.In embodiments of the present invention, FCoE network adapter CPU is by AXI4-Lite bus and AXI4 bus marco IP kernel of the present invention and by the descriptor of the mode configuration register of address and data and sending/receiving data, and to be sent/data flow of receiving is connected with practical function with other IP kernels by AXI4-Stream passage.There are the register storage area of address number and the descriptor memory block (not shown in figure 1) of address number in IP kernel inside of the present invention, when AXI4_Lite bus imports the value of address and configuration register into this IP kernel, the value of configuration register can carry out corresponding renewal; The transmission of descriptor is also like this, is only undertaken by AXI4 bus.
Agreement accelerating engine IP kernel of the present invention comprises three parts: sending module, receiver module and control module.Sending module is for completing the segmentation of data to be sent, encapsulation and transmission, and it is by AXI4-Stream channel reception data to be sent and carry out segmentation and encapsulation in inside, then it is sent to ethernet mac controller by AXI4-Stream passage.Receiver module merges for the decapsulation and data completing data to be received, its by AXI4-Stream passage from ethernet mac controller receiving data, inside complete data decapsulation and merge after by its by AXI4-Stream channel transfer to other IP kernels such as dma controller etc.The value being used for configuring the control register being applied to this IP kernel by AXI4-Lite bus transfer, for completing the configuration to the control register being applied to this IP kernel, carries out storing and is transferred to sending module and receiver module by control module.
Figure 2 shows that the structured flowchart of agreement accelerating engine IP kernel sending module of the present invention, comprise transmission and send the transmission descriptor control unit of descriptor, the transmission high-speed channel control unit sending high-speed data, transmission data buffer storage unit, transmission FCoE data segmentation unit, the harmless Ethernet unit of transmission, transmit queue selected cell, send data packaging unit, transmission descriptor administrative unit and transmission frame buffer unit.
Send descriptor control unit for completing the transmission sending descriptor.Concrete, when needing when there being data to send, first transmission descriptor control AXI4 bus can be sent to transmission descriptor control unit by UNE adapter cpu, and the descriptor of different flow categorical data is sent to transmission descriptor administrative unit and carries out classification storage by transmission descriptor control unit.In embodiments of the present invention, different flow type can comprise: the tcp/ip communication LAN flow etc. of the interprocess communication IPC flow of low delay requirement, the storage network communication SAN flow of lossless requirement, permission certain time-delay and packet loss.In embodiments of the present invention, IP kernel spans several different clock zone, because the clock of different IP kernels can be different, the problem of cross clock domain must be solved when being connected with other IP kernels by IP kernel of the present invention, this unit can relate to the coupling of two clock zones: the AXI4 bus clock territory passing to IP kernel descriptor of the present invention, and the clock zone of IP kernel of the present invention.
Send high-speed channel control unit and be put into this IP kernel for the data to be sent of being sent by AXI4-Stream passage.Concrete, send high-speed channel control unit and choose certain specific descriptor according to the descriptor quantity sent in descriptor administrative unit, and by AXI4-Stream passage, data to be sent corresponding for particular descriptor are sent to transmission high-speed channel control unit according to its content.Concrete, when certain is when the descriptor amount selected is too many, this kind of descriptor can be selected.Because data to be sent have various flow rate type, send the data to be sent that high-speed channel control unit can carry out controlling to obtain different flow type with certain polling sequence.After sending the data to be sent of high-speed channel control unit acquisition different flow type, if common data to be sent, can be sent to transmission data buffer storage unit; If FCoE data block to be sent, can be sent to and be sent FCoE data segmentation unit.In embodiments of the present invention, this unit can relate to the coupling of two clock zones: the clock zone transmitting the AXI4-Stream passage of data to be sent, and the clock zone of IP kernel of the present invention.
Send data buffer storage unit and be used for buffer memory general data to be sent.Concrete, when common data to be sent are sent to transmission data buffer storage unit by transmission high-speed channel control unit, simultaneously can transmitting function discharge pattern index signal.Send data buffer storage unit, according to function flow type indication signal, the data belonging to different discharge pattern are put into different subelement buffer memorys (in embodiments of the present invention, subelement buffer memory refers to each buffer memory for single virtual and traffic partition sending the segmentation of data buffer storage unit inside, not shown in Fig. 2).Send data buffer storage unit and can support that multiple subelement buffer memory is to adapt to the requirement of single virtual and various flow data in UNE simultaneously.When receiving team's array selecting signal that transmit queue selected cell is sent, sending data buffer storage unit and sending the data of corresponding subelement buffer memory to transmit queue selected cell.
Send FCoE data segmentation unit for completing segmentation and the encapsulation of FCoE data block to be sent.Concrete, send high-speed channel control unit send to the data block sending FCoE data segmentation unit comprise send FCoE Frame frame head postamble template and a large section without the data block split.Send FCoE data segmentation unit, according to the requirement of Ethernet protocol largest frames, data block is cut into suitable size, and adding suitable frame head postamble for each section of partition data block according to frame head postamble template in order, the FCoE Frame to be sent now after adding does not comprise CRC check value.Send FCoE data segmentation unit, when receiving team's array selecting signal that transmit queue selected cell is sent, Frame to be sent for the FCoE handled well is sent to transmit queue selected cell.
Send harmless Ethernet unit for realizing the harmless ethernet feature of sending module, comprise flow control (the Priority-based Flow Control based on priority, hereinafter referred to as PFC) frame transmitter and enhancement mode transmission select (Enhanced Transmission Select, hereinafter referred to as ETS) scheduler (not shown in figure 1).Concrete, when sending harmless Ethernet unit and receiving the threshold level signal from receiver module, represent that in receiver module, have certain to receive buffer memory exceeds its caching capabilities, PFC transmitter can according to this signal be PFC data division generate suitable timing value, and add PFC frame head and be sent to transmission frame encapsulation unit as PFC frame, the PFC frame now transmitted is not containing crc value.When sending the transmission time-out vector that harmless Ethernet unit receives from receiver module, ETS scheduler can according to the transmission of this signal suspension corresponding discharge categorical data, and remove sending the data suspending vector instruction from ETS scheduler, now to generate and the scheduling signals being sent to transmit queue selected cell is the next dispatch value needing the discharge pattern data be sent out.In embodiments of the present invention, the rudimentary algorithm of ETS scheduling is for the discharge pattern (such as IPC flow) of low delay distributes strict preference algorithm, for the discharge pattern (such as SAN flow) without frame losing, assign weight polling algorithm, for not only allowing frame losing but also allowing assignment of traffic (the such as LAN flow) polling algorithm of time delay.
Transmit queue selected cell is for selecting the transmission of frame to be sent.Concrete, transmit queue selected cell selects suitable frame to be sent to send according to the result of calculation of the ETS scheduler sent in harmless Ethernet unit in transmission data buffer storage unit and transmission FCoE data segmentation unit, is namely sent to transmission frame encapsulation unit.Meanwhile, after often sending once, this transmission frame type and size can be fed back to and send harmless Ethernet unit, with the traffic control facilitating ETS scheduler to complete next time.
Transmission frame encapsulation unit is for encapsulating Frame to be sent.Concrete, when transmission frame encapsulation unit receives from when sending the data of data buffer storage unit or send the data of harmless Ethernet unit by transmit queue selected cell, can be obtained it send frame information in descriptor accordingly to sending the application of descriptor administrative unit.Transmission frame encapsulation unit is that data to be sent form suitable frame head postamble and encapsulate according to the information of its descriptor.When transmission frame encapsulation unit receives the data from transmission FCoE data segmentation unit by transmit queue selected cell, can't be that FCoE sends Frame formation frame head postamble (frame of other types all needs to add frame head postamble).Finally, transmission frame encapsulation unit is that all frames to be sent carry out the calculating of CRC check value and add CRC check value.Frame to be sent after encapsulation and CRC have been added by transmission frame encapsulation unit is sent to transmission frame buffer unit.
Send descriptor administrative unit and be used for store and management transmission descriptor.Concrete, send descriptor administrative unit and can store the transmission descriptor sending the different flow type that descriptor control unit sends, after the application receiving transmission frame encapsulation unit, send descriptor administrative unit and the transmission descriptor information of correspondence can be sent to transmission frame encapsulation unit for the encapsulation completing data.After transmission frame is sent to transmission frame buffer unit by transmission frame encapsulation unit, sending descriptor administrative unit can mark used descriptor.When the descriptor of certain discharge pattern overuses, send descriptor administrative unit and can send writing back of descriptor to sending the application of descriptor control unit, and application sends descriptor again.
Transmission frame buffer unit is used for buffer memory and sends frame to be sent.Concrete, transmission frame buffer unit connects transmission frame encapsulation unit and ethernet mac controller, when receiving the frame to be sent of transmission frame encapsulation unit, can treat transmission frame and carrying out buffer memory, and is sent to ethernet mac controller and sends.In embodiments of the present invention, transmission frame buffer unit can complete the coupling of 10G ethernet mac controller IP kernel and IP kernel of the present invention two clock zones.
Figure 3 shows that the structured flowchart of agreement accelerating engine IP kernel receiver module of the present invention, comprise received frame buffer unit, received frame resolution unit, receiving queue selected cell, receive data buffer storage unit, receive FCoE data combination unit, receive harmless Ethernet unit, receive descriptor administrative unit, transmit the reception descriptor control unit receiving descriptor and the reception high-speed channel control unit receiving high-speed data.
Received frame buffer unit is used for buffer memory frame to be received.Concrete, received frame buffer unit connects ethernet mac controller and received frame resolution unit, when receiving the frame to be received transmitted from ethernet mac controller, can treat received frame and carrying out buffer memory, and being sent to received frame resolution unit.Received frame buffer unit can complete the coupling of 10G ethernet mac controller IP kernel and IP kernel of the present invention two clock zones.
Received frame resolution unit is for completing the operation such as verification, parsing of received frame.Concrete, received frame resolution unit receives the frame from received frame buffer unit, first carries out CRC check in received frame resolution unit inside, only has the frame of verification succeeds just can be saved and process.Next in received frame resolution unit inside, the type determining frame is resolved to the frame head of received frame.If normal frames, received frame resolution unit then carries out the judgement of discharge pattern to it, then obtain suitable reception descriptor to the application of reception descriptor administrative unit, frame originating point information is inserted descriptor, finally normal frames data is sent to receiving queue selected cell; If PFC frame, be then directly sent to the harmless Ethernet unit of reception and be further processed; If meet certain FCoE Frame exchanged, be then sent to reception FCoE data combination unit and be further processed.
Receiving queue selected cell is used for other except FCoE data to need the data of buffer memory to classify.In embodiments of the present invention, other data refer to other all data except particular exchange FCoE Frame and PFC frame.Concrete, when receiving queue selected cell receives the data and type identification signal sent from received frame resolution unit, other data can be sent to corresponding subelement buffer memory in reception data buffer storage unit according to type identification signal by receiving queue selected cell.
Receive the general data that data buffer storage unit transmits for buffer memory receiving queue selected cell.Concrete, when the receiving queue that receiving queue selected cell sends selects signal and data, data automatically can be cached to and correspondingly belong to different subelement buffer memory (in embodiments of the present invention, subelement buffer memory refers to each buffer memory for single virtual and traffic partition sending the segmentation of data buffer storage unit inside, not shown in Fig. 3).When data volume reaches certain value in reception data buffer storage unit, to the application of reception high-speed channel control unit, other data can be write back to other IP kernels (such as DMA etc.).If data volume is too many and residual memory space is not enough in reception data buffer storage unit, can generate threshold level signal so that sending module generates suitable PFC frame sends.
Receive FCoE data combination unit for the treatment of the specific FCoE Frame of merging.Concrete, when receiving the FCoE Frame from received frame resolution unit, receiving FCoE data combination unit and can resolve remaining FCoE frame originating point information, data load effective in data being preserved simultaneously.When next FCoE Frame arrives, receive FCoE data combination unit and can continue to preserve effective data load and in order multiple valid data load is sorted and preserves to become data block.When data block reaches a certain size, receive FCoE data combination unit and can apply for by receiving high-speed channel control unit to other IP kernels (such as DMA) transmission block.
Receive harmless Ethernet unit for realizing the harmless ethernet feature of receiver module.Concrete, when receiving the PFC data from received frame resolution unit, the harmless Ethernet unit of reception can be resolved PFC frame and generate and be sent time-out vector.Receive harmless Ethernet unit to suspend transmission that vector is sent to sending module can't harm ETS scheduler in Ethernet unit, for suspending the transmission scheduling of certain specific discharge pattern data by sending.
Receive the descriptor that descriptor administrative unit is used for buffer memory and management receiver module.Concrete, receive the reception descriptor (filling) that descriptor administrative unit sends for buffer memory reception descriptor control unit, and carry out classification buffer memory.When the frame information of certain discharge pattern Frame sends by received frame resolution unit, reception descriptor administrative unit can be chosen corresponding reception descriptor and fill.When the reception descriptor of having filled reaches some, reception descriptor administrative unit can write back this part to the application of reception high-speed channel control unit and fill reception descriptor.
Receive descriptor control unit to be used for looking ahead and write back reception descriptor.Concrete, when the value being used for controlling to receive the register started is sent to this IP kernel by UNE adapter cpu, receiving course starts, and receives descriptor control unit and can obtain a certain amount of reception descriptor and then send it to and receive descriptor administrative unit and carry out buffer memory.Reach some when the filling receiving the storage of descriptor administrative unit receives descriptor, receive descriptor control unit and reception descriptor can be write back to UNE adapter cpu.This unit can relate to the coupling of two clock zones: transmit the AXI4 bus clock territory receiving descriptor, and the clock zone of IP kernel of the present invention.
Receive high-speed channel control unit to be used for writing back reception data.Concrete, receiving high-speed channel control unit can by the general data receiving buffer memory in data buffer storage unit and the FCoE data block back receiving FCoE data combination unit buffer memory to other IP kernels such as dma controller etc.This unit relates to the coupling of two clock zones: transmit the AXIS channel clock territory receiving data, and the clock zone of IP kernel of the present invention.
Figure 4 shows that the structured flowchart of agreement accelerating engine IP kernel control module of the present invention, comprise register configuration unit and register management unit.
Register configuration unit is used for configuration control register.Concrete, when UNE adapter starts, AXI4-Lite bus can by the value of control register write register configuration unit.When needing when there being control register to read, the value of control register is sent to AXI4-Lite bus by register configuration unit.This unit can relate to the coupling of two clock zones: AXI4 bus clock territory, and the clock zone of IP kernel of the present invention.
Register management unit is for managing IP kernel internal control registers of the present invention.Concrete, when control register needs certain unit configuring transmission/reception module, the value of control register is sent to corresponding unit by register management unit.
Figure 5 shows that agreement accelerating engine IP kernel of the present invention sends the schematic diagram of data flow.First FCoE UNE adapter cpu the write of control AXI4 bus can send descriptor to transmission descriptor control unit.Receiver module can be sent to sending module two signals: threshold level signal and transmission suspend vector.When there being data to send, the data to be sent sent from AXI4-Stream high-speed data channel are sent to transmission data buffer storage unit or transmission FCoE data segmentation unit by high-speed channel control unit.If other data, then other data enter send data buffer storage unit carry out classification buffer memory; If FCoE data block, then enter transmission FCoE data segmentation unit and carry out segment encapsulation.Right latter two data enter transmit queue selected cell and carry out transmission selection.Send harmless Ethernet unit and to send and suspend vector and carry out PFC framing and ETS scheduling according to threshold level signal, and produce scheduling signals in conjunction with dispatching algorithm and send to transmit queue selected cell.Transmit queue selected cell carries out transmission according to this scheduling signals and selects.Data after sending and selecting process enter transmission frame encapsulation unit and carry out framing processing and encapsulation, now can need to send interpolation and the CRC interpolation that descriptor carries out frame information.Finally the transmission frame after framing is sent to transmission frame buffer unit, wait to be sent.
Figure 6 shows that the schematic diagram of agreement accelerating engine IP kernel receiving data stream of the present invention.First, when log-on data receives, AXI4 bus can be sent to the unfilled reception descriptor receiving descriptor control unit a certain amount of different flow type.When needing when there being frame to receive, received frame can enter received frame buffer unit.Then received frame is sent to received frame resolution unit and carries out School Affairs parsing, frame information is sent to and receives the filling that descriptor administrative unit is described symbol.Frame through resolving removes frame head postamble (being called data), and other data enter reception data buffer storage unit by the reception selection function of receiving queue selected cell and carry out classification buffer memory.FCoE data enter FCoE and receive merging and the buffer memory that data combination unit carries out data.PFC data enter the harmless Ethernet unit of reception and carry out the parsing of frame to generate transmission time-out vector.FCoE data block and other data of eventually passing buffer memory send to AXI4-Stream passage by receiving high-speed channel control unit.Send time-out vector threshold level signal and send to sending module.And the reception descriptor of having filled writes back via AXI4 bus.
IP kernel provided by the invention can be controlled by FCoE UNE adapter cpu, specially for the needs of hardware handles FCoE Frame in Ethernet optical-fibre channel field, adopt full duplex mode of operation, work real-time high-efficiency, data throughout is large, transmission rate is high, and can realize Lossless transport and support virtual.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1., based on a FCoE agreement accelerating engine IP kernel for AXI4 bus architecture, it is characterized in that, comprise sending module, receiver module and control module, wherein:
Described sending module comprises: send descriptor control unit, for transmitting transmission descriptor; Send high-speed channel control unit, for receiving data to be sent, wherein said data to be sent comprise general data and FCoE data block; Send data buffer storage unit, for the described general data that buffer memory is to be sent; Send FCoE data segmentation unit, form FCoE Frame to be sent for splitting and encapsulating described FCoE data block to be sent; Sending harmless Ethernet unit, generating and ETS scheduling for completing PFC frame; Transmit queue selected cell, for selecting to send described general data and described FCoE Frame to be sent according to described ETS scheduling; Sending data packaging unit, for encapsulating described general data to be sent and described PFC frame according to described transmission descriptor, and CRC interpolation formation frame to be sent being carried out to the Frame after encapsulation and described FCoE Frame to be sent; Send descriptor administrative unit to be used for sending descriptor described in store and management; And transmission frame buffer unit, send described frame to be sent for buffer memory;
Described receiver module comprises: received frame buffer unit, for buffer memory frame to be received; Received frame resolution unit, for completing verification to described frame to be received, resolving to form general data, type identification signal, PFC frame and FCoE Frame; Receiving queue selected cell, the described type identification signal behavior for generating according to described received frame resolution unit receives the described general data after resolving; Receive data buffer storage unit, for general data described in buffer memory; Receive FCoE data combination unit, for merging and FCoE Frame formation FCoE data block described in buffer memory; Receive harmless Ethernet unit, suspend vector for resolving PFC frame and generating to send, to suspend the transmission scheduling of particular flow rate categorical data; Receive descriptor administrative unit, receive descriptor for buffer memory and filling; Receive descriptor control unit, for looking ahead and writing back described reception descriptor; And receive high-speed channel control unit, for the FCoE data block of the general data and described reception FCoE data combination unit buffer memory that write back described reception data buffer storage unit buffer memory; And
Described control module comprises: register configuration unit, for configuring the control register being applied to described FCoE agreement accelerating engine IP kernel, and register management unit, for managing described control register, when described control register needs certain unit configuring described sending module or described receiver module, the value of described control register is sent to corresponding units by described register management unit.
2. as claimed in claim 1 based on the FCoE agreement accelerating engine IP kernel of AXI4 bus architecture, it is characterized in that, described FCoE agreement accelerating engine IP kernel is based upon on AXI4 bus, AXI4-Lite bus and AXI4-Stream high-speed channel basis, is controlled by FCoE network adapter CPU.
3., as claimed in claim 1 or 2 based on the FCoE agreement accelerating engine IP kernel of AXI4 bus architecture, it is characterized in that, each unit of described sending module specifically for:
Described transmission descriptor control unit is for transmitting described transmission descriptor, when needs send data, described transmission descriptor first can be sent to described transmission descriptor control unit by FCoE network adapter CPU, and the transmission descriptor of different flow categorical data is sent to described transmission descriptor administrative unit and carries out classification storage by described transmission descriptor control unit;
Described transmission high-speed channel control unit is for receiving described data to be sent, AXI4-Stream high-speed channel is sent to described transmission high-speed channel control unit by needing the data sent, described transmission high-speed channel control unit is according to the discharge pattern of described data to be sent, send described general data and function flow type indication signal to described transmission data buffer storage unit, described FCoE data block is sent to described transmission FCoE data segmentation unit;
Described transmission data buffer storage unit is used for buffer memory described general data to be sent, the general data belonging to different discharge pattern is put into different subelement buffer memorys, to realize single virtual and traffic partition according to described function flow type indication signal by described transmission data buffer storage unit;
Described transmission FCoE data segmentation unit is exclusively used in FCoE Frame described in merging and buffer memory and forms described FCoE data block, described FCoE data block is cut into suitable size according to the requirement of Ethernet protocol largest frames by described transmission FCoE data segmentation unit, and form described FCoE Frame for each section of partition data block adds suitable frame head postamble in order, and when receiving team's array selecting signal that described transmit queue selected cell is sent, described FCoE Frame is sent to described transmit queue selected cell;
Described transmission can't harm Ethernet unit and dispatches for the generation and described ETS completing described PFC frame, when described transmission can't harm the threshold level signal that Ethernet unit receives from described receiver module, can be the timing value that PFC data genaration is suitable according to described threshold level signal, and add PFC frame head and form described PFC frame and be sent to described transmission frame encapsulation unit part; When described transmission can't harm the transmission received from described receiver module of Ethernet unit suspend vector time, can suspend according to described transmission the transmission that vector suspends corresponding discharge categorical data, and the described data suspending vector instruction that send are removed from ETS scheduler;
Described transmit queue selected cell is used for selecting to send described general data and described FCoE Frame to be sent according to described ETS scheduling, being sent completely after at every turn, sent data type and size can being fed back to described transmission and can't harm Ethernet unit;
Described transmission frame encapsulation unit is used for encapsulating described general data to be sent and described PFC frame according to described transmission descriptor, and CRC interpolation formation frame to be sent is carried out to the Frame after encapsulation and described FCoE Frame to be sent, when described transmission frame encapsulation unit receives described general data to be sent and described PFC frame, obtain its corresponding frame information sent in descriptor to the application of described transmission descriptor administrative unit;
Described transmission descriptor administrative unit is used for sending descriptor described in store and management, after the application receiving described transmission frame encapsulation unit, the transmission descriptor information of correspondence can be sent to described transmission frame encapsulation unit to complete the encapsulation of data by described transmission descriptor administrative unit;
Described transmission frame buffer unit is used for buffer memory send described frame to be sent, when receiving the described frame to be sent of described transmission frame encapsulation unit, can carry out buffer memory to described frame to be sent, and is sent to ethernet mac controller and sends.
4. as claimed in claim 3 based on the FCoE agreement accelerating engine IP kernel of AXI4 bus architecture, it is characterized in that, described transmission descriptor control unit completes the coupling of two clock zones: the clock zone of AXI4 bus clock territory and described FCoE agreement accelerating engine IP kernel; Described transmission high-speed channel control unit completes the coupling of two clock zones: the clock zone of AXI4-Stream passage and the clock zone of described FCoE agreement accelerating engine IP kernel; Described transmission frame buffer unit completes the coupling of two clock zones: the clock zone of ethernet mac controller and the clock zone of described FCoE agreement accelerating engine IP kernel.
5., as claimed in claim 1 or 2 based on the FCoE agreement accelerating engine IP kernel of AXI4 bus architecture, it is characterized in that, each unit of described receiver module specifically for:
Described received frame buffer unit is used for frame to be received described in buffer memory, when receiving the described frame to be received transmitted from ethernet mac controller, can carry out buffer memory to described frame to be received and be sent to described received frame resolution unit;
Described received frame resolution unit is for completing the verification to described frame to be received, resolve to form general data, type identification signal, PFC frame and FCoE Frame, first in described received frame resolution unit inside, CRC check is carried out to described frame to be received, resolve to determine its type to the frame head of the frame to be received of verification succeeds again, if normal frames, then it is carried out to the judgement of discharge pattern, then corresponding reception descriptor is obtained to described reception descriptor administrative unit application, frame originating point information is inserted after corresponding reception descriptor forms general data and be sent to described receiving queue selected cell, if PFC frame, be then sent to described reception and can't harm Ethernet unit, if FCoE Frame, be then sent to described reception FCoE data combination unit,
The described type identification signal behavior that described receiving queue selected cell is used for generating according to described received frame resolution unit receives the described general data after resolving, when receiving the general data and type identification signal sent from described received frame resolution unit, described general data can be sent to corresponding subelement buffer memory in described reception data buffer storage unit according to described type identification signal by described receiving queue selected cell;
Described reception data buffer storage unit is used for general data described in buffer memory, when in described reception data buffer storage unit, data volume reaches certain value, to the application of described reception high-speed channel control unit, its data can be write back to other IP kernels, if in described reception data buffer storage unit data volume too many and residual memory space is not enough time, generating threshold level signal is sent to described sending module to generate suitable PFC frame and sends;
Described reception FCoE data combination unit is used for FCoE Frame described in merging and buffer memory and forms described FCoE data block, when receiving the described FCoE Frame from described received frame resolution unit, described reception FCoE data combination unit can resolve remaining FCoE frame originating point information, to wherein effective data load preserve simultaneously, when next FCoE Frame arrives, described reception FCoE data combination unit can continue to preserve its valid data load and multiple valid data load sorted in order and preserve the described FCoE data block of formation;
Described reception can't harm Ethernet unit and suspends vector for resolving PFC frame and generating described transmission, the described transmission that described transmission time-out vector is sent to described sending module be can't harm the ETS scheduler in Ethernet unit, to suspend the transmission scheduling of particular flow rate categorical data;
Described reception descriptor administrative unit is used for buffer memory and fills receiving descriptor, when the frame information of certain discharge pattern Frame sends by described received frame resolution unit, described reception descriptor administrative unit can be chosen corresponding reception descriptor and fill, when the reception descriptor of having filled reaches some, described reception descriptor administrative unit can write back this part reception descriptor of having filled to the application of described reception high-speed channel control unit;
Described reception descriptor control unit is used for looking ahead and write back described reception descriptor, when the reception of the filling descriptor that described reception descriptor administrative unit stores reaches some, the reception descriptor of having filled can be received descriptor by described reception descriptor control unit write back to UNE adapter cpu;
Described reception high-speed channel control unit for the FCoE data block of the general data and described reception FCoE data combination unit buffer memory that write back described reception data buffer storage unit buffer memory, and writes back to other IP kernels.
6. as claimed in claim 5 based on the FCoE agreement accelerating engine IP kernel of AXI4 bus architecture, it is characterized in that, described reception descriptor control unit completes the coupling of two clock zones: the clock zone of AXI4 bus clock territory and described FCoE agreement accelerating engine IP kernel; Described reception high-speed channel control unit completes the coupling of two clock zones: the clock zone of AXI4-Stream passage and the clock zone of described FCoE agreement accelerating engine IP kernel; Described received frame buffer unit completes the coupling of two clock zones: the clock zone of ethernet mac controller and the clock zone of described FCoE agreement accelerating engine IP kernel.
7. as claimed in claim 1 or 2 based on the FCoE agreement accelerating engine IP kernel of AXI4 bus architecture, it is characterized in that, described register configuration unit completes the coupling of two clock zones: the clock zone of AXI4 bus clock territory and described FCoE agreement accelerating engine IP kernel.
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