CN113507424A - FC engine frame receiving buffer management mechanism - Google Patents
FC engine frame receiving buffer management mechanism Download PDFInfo
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- CN113507424A CN113507424A CN202110717677.7A CN202110717677A CN113507424A CN 113507424 A CN113507424 A CN 113507424A CN 202110717677 A CN202110717677 A CN 202110717677A CN 113507424 A CN113507424 A CN 113507424A
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- 238000011084 recovery Methods 0.000 claims description 28
- 230000005540 biological transmission Effects 0.000 claims description 8
- 239000007853 buffer solution Substances 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/12—Avoiding congestion; Recovering from congestion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/50—Overload detection or protection within a single switching element
- H04L49/505—Corrective measures
- H04L49/506—Backpressure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
Abstract
The invention discloses a FC engine frame receiving cache management mechanism.A frame receiving processing submodule receives frame data and related information thereof from a front-end module through an AXI-Stream interface, implements receiving frame writing operation, and writes the data into a receiving shared dual-port RAM; receiving FC frame data cached and received by a shared dual-port RAM, dividing the FC frame data into a plurality of cache blocks and carrying out flow control; the forwarding and receiving interface adaptation submodule implements a receiving frame reading operation, reads data from the receiving shared dual-port RAM, and sends frame data to the back-end module through the AXI-Stream interface; the invention is compatible with two receiving modes of direct connection and storage and forwarding, converts normal frame data received by the FC engine from 106.25MHz to 400MHz after table look-up, accurately transmits the frame data to the back end, designs a fault-tolerant mechanism, does not influence the normal operation of a receiving channel and the management of caching to flow control, ensures that an FC engine link forms proper back pressure on a connected transmitting end when abnormal blockage occurs at the back end, and automatically recovers the receiving of the frame data after the blockage is eliminated.
Description
Technical Field
The invention belongs to the technical field of data transmission, and particularly relates to a receiving and caching technology.
Background
A fiber Channel, FC for short, is a high-reliability lossless network, and has two characteristics of a network and a Channel, so that a data transmission service with high bandwidth, low delay and high stability can be provided.
The FC engine is responsible for FC link initialization, flow control mechanism establishment, frame data transceiving, encoding and decoding, transmission word transceiving and link synchronization. The frame receiving buffer management mechanism is an important part of the flow control mechanism, and is a key technology in relation to the stability of the FC link, the accuracy of receiving frame data, and the efficiency of receiving frame data. If the receiving, storing and forwarding of the FC engine across clock domains can be realized, and different error frame processing mechanisms are selected according to different error frame strategies, the abnormal blockage of the FC link can be effectively dealt with.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a frame receiving and buffering management mechanism for an FC engine.
The mechanism comprises a frame receiving processing sub-module, a forwarding receiving interface adaptation sub-module, a receiving sharing dual-port RAM, a receiving back pressure signal FIFO, a receiving cache frame base address recovery FIFO, a receiving discarded frame base address recovery FIFO, a receiving frame read-write address comparator and a receiving frame information FIFO, and adopts a standard AXI _ Stream bus interface; the receiving and sharing dual-port RAM and all the FIFO work asynchronously, one side connected with the frame receiving and processing sub-module is a low-frequency clock domain, and one side connected with the forwarding and receiving interface adaptation sub-module is a high-frequency clock domain; and performing Gray code conversion on the write cache address and the read cache address by adopting a received frame read-write address comparator.
The frame receiving processing submodule receives frame data and relevant information thereof from the front-end module through an AXI-Stream interface, implements received frame writing operation, and writes the data into the receiving shared dual-port RAM; receiving FC frame data cached and received by a shared dual-port RAM, dividing the FC frame data into a plurality of cache blocks and carrying out flow control; the forwarding and receiving interface adaptation submodule implements a receiving frame reading operation, reads data from the receiving shared dual-port RAM, and sends frame data to the back-end module through the AXI-Stream interface.
The frame receiving and processing submodule sends a minimum frame check passing signal to the routing table look-up control in the module to confirm that the received frame is complete, and sends a routing query request to the routing table look-up module to obtain routing query feedback.
Further, the lookup table includes a pass-through mode and a store-and-forward mode.
A through mode: the frame receiving processing submodule writes buffer frame information into the receiving frame information FIFO, and directly writes the base address of the receiving frame and the relevant information thereof together with the table look-up result into the receiving frame information FIFO.
Store-and-forward mode: the frame receiving processing sub-module waits for the completion of frame receiving, if the table lookup result contains a discarding indication, the base address of the frame is written into a receiving discarding frame base address recovery FIFO, otherwise, the relevant information of the frame and the table lookup result are written into a receiving frame information FIFO.
Further, the flow control comprises a store-and-forward mode, a direct mode, an error frame mode and a back-end congestion mode.
Store-and-forward mode: the frame receiving processing submodule recovers a receiving frame storage base address sent by the FIFO according to the receiving cache base address, writes the received frame into the receiving shared dual-port RAM, and writes the table look-up result and the base address information into the receiving frame information FIFO; and the forwarding and receiving interface adaptation submodule reads frame data and frame information from the receiving shared dual-port RAM according to the cache frame information sent by the receiving frame information FIFO, and sends the frame data and the frame information to the back-end module through the AXI _ Stream interface.
Further, the forwarding and receiving interface adaptation submodule reads a frame of data from the receiving shared dual-port RAM, sends a backpressure indication signal of 1' b1 to the receiving backpressure signal FIFO, and the receiving backpressure signal FIFO sends the signal to the frame receiving processing submodule, which sends an R _ RDY primitive indication signal to the front-end module.
A through mode: and comparing the read-write addresses of the received frames on the basis of the store-and-forward mode, and if the frequency of the read clock for receiving the shared dual-port RAM is far higher than that of the write clock, reducing the frequency of the read address and increasing the frequency of the write address.
Error frame mode: if the frame receiving and processing submodule finds that a CRC error or an illegal transmission word exists in the frame or the received frame start character is not matched with the frame start character supported in the strategy register or the frame is discarded by table look-up feedback, the value of the strategy register is read, if the value prompts to discard, the next frame is waited to be received, otherwise, the end character of the frame is replaced by EOFa; if the frame length is smaller than the shortest frame, waiting for receiving the next frame, and sending a discard signal to a forwarding and receiving interface adaptation submodule to count the number of discard frames; if the frame receiving processing submodule finds that the frame is an ultra-long frame, the value of the strategy register is read, if the value prompts discarding, the base address of the frame is written into a receiving discarded frame base address recovery FIFO, and if not, the action is not carried out; if the frame receiving processing submodule finds that the frame end symbol is invalid, the value of the strategy register is read, if the value prompts discarding, the base address of the frame is written into the receiving discarding frame base address recovery FIFO, otherwise, the frame information is written into the receiving frame information FIFO.
Further, if the super-long frame is discarded, the current write data is replaced by EOFa, and the receiving is continued until the frame end symbol is received, and the next frame is waited to be received.
Further, if the frame with invalid end symbol is discarded, the end symbol of the current frame is replaced by EOFa.
Back-end congestion mode: and if the forwarding and receiving interface adapter submodule cannot read data from the receiving shared dual-port RAM in time and the receiving buffer frame base address recovery FIFO is empty, the frame receiving processing submodule discards frame data and sends an R _ RDY primitive indication signal to the front-end module.
The forwarding and receiving interface adaptation submodule reads the buffer base address and the related information of the frame from the receiving frame information FIFO, takes the base address as the initial address, reads the frame data from the receiving shared dual-port RAM and sends the frame data to the back-end module.
Further, the forwarding and receiving interface adaptation submodule writes the released cache space base address into a receiving cache frame base address recovery FIFO; if the receiving discarded frame base address recovery FIFO is not empty, reading the frame base address from the receiving discarded frame base address recovery FIFO and writing the frame base address into the receiving cache frame base address recovery FIFO.
The invention has the beneficial effects that: the method is compatible with two receiving modes of direct connection and storage forwarding, converts normal frame data received by an FC engine from 106.25MHz to 400MHz after table lookup, and accurately transmits the normal frame data to a rear end; a fault-tolerant mechanism is designed for errors such as CRC (cyclic redundancy check) errors, illegal transmission words, ultra-short frames, ultra-long frames, invalid frame end characters, unsupported frame start characters, table look-up feedback frame loss and the like, normal operation of a receiving channel is not influenced, and the errors are reported to an FC engine external system; according to the processing strategy of the external system on the error frame data, the error frame data is continuously cached and sent or discarded, and the caching to the flow control management is not influenced; when abnormal blockage occurs at the back end, the FC engine link is ensured to form proper back pressure on the connected sending end, and the frame data receiving is automatically recovered after the blockage is eliminated.
Drawings
Fig. 1 is a schematic diagram of a receive buffer.
Detailed Description
The technical scheme of the invention is specifically explained in the following by combining the attached drawings.
The principle of the mechanism is shown in fig. 1, and the mechanism comprises a frame receiving processing sub-module, a forwarding receiving interface adaptation sub-module, a receiving shared dual-port RAM, a receiving back-pressure signal FIFO, a receiving buffer frame base address recovery FIFO, a receiving discarded frame base address recovery FIFO, a receiving frame read-write address comparator and a receiving frame information FIFO.
The frame receiving processing sub-module receives frame data and related information thereof from the front-end module through an AXI-Stream interface, controls and sends a minimum frame check passing signal to a routing table look-up in the module, confirms that the received frame is complete, sends a routing query request to the routing table look-up module, acquires routing query feedback, implements received frame write operation, and writes data into the receiving shared dual-port RAM.
Under the direct mode, the frame receiving processing sub-module writes buffer frame information into the receiving frame information FIFO, and directly writes the base address of the receiving frame and the relevant information thereof into the receiving frame information FIFO together with the table look-up result.
Under the store-and-forward mode, the frame receiving processing sub-module waits for the completion of frame receiving, if the table lookup result contains a discard indication, the base address of the frame is written into the receiving discard frame base address recovery FIFO, otherwise, the relevant information of the frame and the table lookup result are written into the receiving frame information FIFO.
And the receiving shared dual-port RAM and all FIFOs work asynchronously, one side connected with the frame receiving and processing submodule is a low-frequency clock domain, one side connected with the forwarding and receiving interface adaptation submodule is a high-frequency clock domain, the received FC frame data is cached, and the FC frame data is divided into a plurality of cache blocks and flow-controlled.
Under the store-and-forward mode, the frame receiving processing sub-module recovers a receiving frame storage base address sent by the FIFO according to the receiving cache base address, writes the received frame into the receiving shared dual-port RAM, and writes the table look-up result and the base address information into the receiving frame information FIFO; and the forwarding and receiving interface adaptation submodule reads frame data and frame information from the receiving shared dual-port RAM according to the cache frame information sent by the receiving frame information FIFO, and sends the frame data and the frame information to the back-end module through the AXI _ Stream interface.
And comparing the read-write addresses of the received frames on the basis of the store-and-forward mode in the direct-through mode, and if the frequency of a read clock for receiving the shared dual-port RAM is far higher than that of a write clock, reducing the frequency of the read address and increasing the frequency of the write address.
Under the error frame mode, if the frame receiving and processing submodule finds that a CRC error or an illegal transmission word exists in the frame or the received frame start character is not matched with the frame start character supported in the strategy register or the frame is discarded by table look-up feedback, the value of the strategy register is read, if the value prompts to discard, the next frame is waited to be received, otherwise, the end character of the frame is replaced by EOFa; if the frame length is smaller than the shortest frame, waiting for receiving the next frame, and sending a discard signal to a forwarding and receiving interface adaptation submodule to count the number of discard frames; if the frame receiving processing submodule finds that the frame is an ultra-long frame, the value of the strategy register is read, if the value prompts discarding, the base address of the frame is written into a receiving discarded frame base address recovery FIFO, and if not, the action is not carried out; if the frame receiving processing submodule finds that the frame end symbol is invalid, the value of the strategy register is read, if the value prompts discarding, the base address of the frame is written into the receiving discarding frame base address recovery FIFO, otherwise, the frame information is written into the receiving frame information FIFO.
Under the back-end congestion mode, if the forwarding and receiving interface adapter sub-module cannot read data from the receiving shared dual-port RAM in time and the receiving buffer frame base address recovery FIFO is empty, the frame receiving processing sub-module discards the frame data and sends an R _ RDY primitive indication signal to the front-end module.
The forwarding receiving interface adaptation submodule reads a cache base address and relevant information of a frame from the receiving frame information FIFO, takes the base address as an initial address, implements receiving frame reading operation, reads data from the receiving shared dual-port RAM, and sends frame data to the back-end module through the AXI-Stream interface.
Starting from the FC engine power-on reset:
the FC engine establishes a link with connected FC endpoint equipment, starts to receive FC frame data, transmits the FC frame data to a frame receiving processing submodule from the front end through an AXI-Stream bus with 64bit data bit width, and simultaneously transmits frame information such as CRC (cyclic redundancy check) errors, illegal transmission words, ultra-short frames, ultra-long frames, invalid frame end symbols, unsupported frame start symbols and the like.
2. If the receiving buffer base address recovery FIFO is empty, the frame receiving processing submodule discards the received frame data and sends an indication of sending an R _ RDY primitive to the front end.
3. If the receiving buffer base address recovery FIFO is not empty, the frame receiving processing submodule reads out a receiving base address from the FIFO and then makes corresponding processing measures according to different working modes.
4. In store-and-forward mode: if the received frame is a normal frame, initiating query to a lookup table module, if a discarding command is not returned, writing the frame data into a receiving shared dual-port RAM, and if the discarding command is returned, discarding the current frame; if the received frame is an error frame, corresponding processing measures are made according to an error frame processing strategy, if the received frame is an error frame discarding strategy, the data of the current frame is discarded, and if the received frame is an error frame retaining strategy, the data of the frame is written into the receiving shared dual-port RAM according to the read base address information.
5. In the pass-through mode: if the received frame is a normal frame, initiating query to a lookup table module, and writing the frame data into a storage interval starting from the base address in the receiving shared dual-port RAM according to the read base address information; if the received frame is an error frame, all the frame data of the rest error frame types except the unsupported frame type of the frame start symbol are written into the receiving shared dual-port RAM, and if the received frame is the unsupported frame type of the frame start symbol, the current frame data is discarded.
6. When the back end allows to receive frame data and the receiving frame information FIFO is not empty, the forwarding receiving interface adaptation submodule receives the frame data
And after reading out one frame of data from the shared double-port RAM, sending the frame of data to the back end through an AXI-Stream bus with a 128bit data bit width.
7. Once the receive discard frame base address reclaim FIFO is not empty, the forward receive interface adapter submodule immediately reads base address data from the FIFO and then writes the base address data into the receive buffer base address reclaim FIFO.
The above-described embodiments are not intended to limit the present invention, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present invention are included in the scope of the present invention.
Claims (10)
1. An FC engine frame reception buffer management mechanism, comprising: the frame receiving processing sub-module, the forwarding receiving interface adaptation sub-module, the receiving sharing dual-port RAM, the receiving back pressure signal FIFO, the receiving buffer frame base address recovery FIFO, the receiving discarding frame base address recovery FIFO, the receiving frame read-write address comparator, the receiving frame information FIFO, and the standard AXI _ Stream bus interface is adopted; the receiving and sharing dual-port RAM and all the FIFO work asynchronously, one side connected with the frame receiving and processing sub-module is a low-frequency clock domain, and one side connected with the forwarding and receiving interface adaptation sub-module is a high-frequency clock domain;
and performing Gray code conversion on the write cache address and the read cache address by adopting a received frame read-write address comparator.
2. The FC engine frame reception buffer management mechanism of claim 1, further comprising: the frame receiving processing submodule receives frame data and relevant information thereof from the front-end module through an AXI-Stream interface, implements received frame writing operation, and writes the data into the receiving shared dual-port RAM; receiving FC frame data cached and received by a shared dual-port RAM, dividing the FC frame data into a plurality of cache blocks and carrying out flow control; the forwarding and receiving interface adaptation submodule implements a receiving frame reading operation, reads data from the receiving shared dual-port RAM, and sends frame data to the back-end module through the AXI-Stream interface.
3. The FC engine frame reception buffer management mechanism of claim 2, wherein the receiving frame data from the front-end module comprises: the frame receiving and processing submodule sends a minimum frame check passing signal to the routing table look-up control in the module to confirm that the received frame is complete, and sends a routing query request to the routing table look-up module to obtain routing query feedback.
4. The FC engine frame reception buffer management mechanism of claim 3, wherein the table lookup comprises:
a pass-through mode and a store-and-forward mode; a through mode: the frame receiving processing submodule writes cache frame information into the receiving frame information FIFO, and directly writes the base address of the receiving frame and the relevant information thereof as well as a table look-up result into the receiving frame information FIFO;
store-and-forward mode: the frame receiving processing sub-module waits for the completion of frame receiving, if the table lookup result contains a discarding indication, the base address of the frame is written into a receiving discarding frame base address recovery FIFO, otherwise, the relevant information of the frame and the table lookup result are written into a receiving frame information FIFO.
5. The FC engine frame reception buffer management mechanism of claim 3, wherein the flow control comprises:
a store-and-forward mode, a direct-through mode, an error frame mode and a back-end congestion mode;
store-and-forward mode: the frame receiving processing submodule recovers a receiving frame storage base address sent by the FIFO according to the receiving cache base address, writes the received frame into the receiving shared dual-port RAM, and writes the table look-up result and the base address information into the receiving frame information FIFO; the forwarding and receiving interface adaptation submodule reads frame data and frame information from the receiving shared dual-port RAM according to cache frame information sent by the receiving frame information FIFO, and sends the frame data and the frame information to the back-end module through the AXI _ Stream interface;
a through mode: on the basis of a store-and-forward mode, comparing read-write addresses of received frames, and if the frequency of a read clock for receiving the shared dual-port RAM is far higher than that of a write clock, reducing the frequency of the read address and increasing the frequency of the write address;
error frame mode: if the frame receiving and processing submodule finds that a CRC error or an illegal transmission word exists in the frame or the received frame start character is not matched with the frame start character supported in the strategy register or the frame is discarded by table look-up feedback, the value of the strategy register is read, if the value prompts to discard, the next frame is waited to be received, otherwise, the end character of the frame is replaced by EOFa; if the frame length is smaller than the shortest frame, waiting for receiving the next frame, and sending a discard signal to a forwarding and receiving interface adaptation submodule to count the number of discard frames; if the frame receiving processing submodule finds that the frame is an ultra-long frame, the value of the strategy register is read, if the value prompts discarding, the base address of the frame is written into a receiving discarded frame base address recovery FIFO, and if not, the action is not carried out; if the frame receiving processing submodule finds that the frame end symbol is invalid, the value of the strategy register is read, if the value prompts discarding, the base address of the frame is written into a receiving discarding frame base address recovery FIFO, otherwise, the frame information is written into a receiving frame information FIFO;
back-end congestion mode: and if the forwarding and receiving interface adapter submodule cannot read data from the receiving shared dual-port RAM in time and the receiving buffer frame base address recovery FIFO is empty, the frame receiving processing submodule discards frame data and sends an R _ RDY primitive indication signal to the front-end module.
6. The FC engine frame reception buffer management mechanism of claim 5, wherein the store-and-forward mode further comprises: the forwarding and receiving interface adaptation submodule reads a frame of data from the receiving shared dual-port RAM, sends a backpressure indicating signal of 1' b1 to the receiving backpressure signal FIFO, the receiving backpressure signal FIFO sends the signal to the frame receiving processing submodule, and the frame receiving processing submodule sends an R _ RDY primitive indicating signal to the front-end module.
7. The FC engine frame reception buffer management mechanism of claim 5, wherein the dropping of very long frames comprises: and replacing the current written data with EOFa, continuing to receive until a frame end symbol is received, and waiting for receiving the next frame.
8. The FC engine frame reception buffer management mechanism of claim 5, wherein the dropping of frames with invalid end-of-line comprises: the current frame end symbol is replaced with EOFa.
9. The FC engine frame reception buffer management mechanism of claim 2, wherein the sending frame data to the back-end module comprises: the forwarding and receiving interface adaptation submodule reads the buffer base address and the related information of the frame from the receiving frame information FIFO, takes the base address as the initial address, reads the frame data from the receiving shared dual-port RAM and sends the frame data to the back-end module.
10. The FC engine frame reception buffer management mechanism of claim 9, further comprising: the forwarding receiving interface adaptation submodule writes the released cache space base address into a receiving cache frame base address recovery FIFO; if the receiving discarded frame base address recovery FIFO is not empty, reading the frame base address from the receiving discarded frame base address recovery FIFO and writing the frame base address into the receiving cache frame base address recovery FIFO.
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