CN113507424B - FC engine frame receiving buffer management system - Google Patents
FC engine frame receiving buffer management system Download PDFInfo
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- CN113507424B CN113507424B CN202110717677.7A CN202110717677A CN113507424B CN 113507424 B CN113507424 B CN 113507424B CN 202110717677 A CN202110717677 A CN 202110717677A CN 113507424 B CN113507424 B CN 113507424B
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- 239000000872 buffer Substances 0.000 title claims abstract description 35
- 230000006978 adaptation Effects 0.000 claims abstract description 26
- 238000011084 recovery Methods 0.000 claims description 31
- 239000003999 initiator Substances 0.000 claims description 11
- 230000005540 biological transmission Effects 0.000 claims description 10
- 239000007853 buffer solution Substances 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 claims description 2
- 230000007246 mechanism Effects 0.000 abstract description 7
- 230000002159 abnormal effect Effects 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/12—Avoiding congestion; Recovering from congestion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/50—Overload detection or protection within a single switching element
- H04L49/505—Corrective measures
- H04L49/506—Backpressure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
Abstract
The invention discloses an FC engine frame receiving buffer management system, wherein a frame receiving processing sub-module receives frame data and relevant information thereof from a front-end module through an AXI-Stream interface, performs a frame receiving write operation, and writes the data into a receiving shared dual-port RAM; receiving FC frame data received by a shared dual-port RAM cache, dividing the FC frame data into a plurality of cache blocks and performing flow control; the forwarding receiving interface adaptation submodule carries out receiving frame reading operation, reads data from a receiving shared dual-port RAM, and sends frame data to the back-end module through an AXI-Stream interface; the invention is compatible with two receiving modes of direct connection and store and forward, normal frame data received by the FC engine is converted from 106.25MHz to 400MHz after table lookup and is accurately transmitted to the back end, a fault tolerance mechanism is designed, normal operation of a receiving channel and buffer memory to management of flow control are not influenced, when abnormal blockage occurs at the back end, the FC engine link is ensured to form proper back pressure on a connected transmitting end, and the receiving of the frame data is automatically restored after the blockage is eliminated.
Description
Technical Field
The invention belongs to the technical field of data transmission, and particularly relates to a receiving and buffering technology.
Background
The fiber Channel, abbreviated as FC, is a high-reliability lossless network, has two characteristics of a network and a Channel, can provide high-bandwidth, low-delay and high-stability data transmission service, is mainly used for data communication between devices, and is usually implemented in an ASIC or an FPGA.
The FC engine is responsible for FC link initialization, establishment of a flow control mechanism, transmission and reception of frame data, encoding and decoding, transmission and reception of transmission words and synchronization of links. The frame receiving buffer management mechanism is an important part of the flow control mechanism, and is a key technology concerning the stability of the FC link, the accuracy of receiving frame data and the efficiency of receiving frame data. If the FC engine can realize the cross-clock domain receiving, storing and forwarding, according to different frame-misplacement strategies, different frame-misplacement processing mechanisms are selected, and abnormal blockage of the FC link can be effectively treated.
Disclosure of Invention
The invention provides an FC engine frame receiving buffer management system for solving the problems in the prior art, and adopts the following technical scheme for realizing the purposes.
The mechanism comprises a frame receiving processing submodule, a forwarding receiving interface adaptation submodule, a receiving shared double-port RAM, a receiving back pressure signal FIFO, a receiving buffer frame base address recovery FIFO, a receiving discarding frame base address recovery FIFO, a receiving frame read-write address comparator and a receiving frame information FIFO, and adopts a standard AXI_stream bus interface; the receiving and sharing dual-port RAM and all the FIFO work asynchronously, one side connected with the frame receiving and processing submodule is a low-frequency clock domain, and one side connected with the forwarding and receiving interface adaptation submodule is a high-frequency clock domain; and adopting a receiving frame read-write address comparator to implement Gray code conversion on the write buffer address and the read buffer address.
The frame receiving processing sub-module receives frame data and related information thereof from the front-end module through an AXI-Stream interface, implements a received frame writing operation, and writes the data into a received shared dual-port RAM; receiving FC frame data received by a shared dual-port RAM cache, dividing the FC frame data into a plurality of cache blocks and performing flow control; the forwarding receiving interface adaptation submodule carries out receiving frame reading operation, reads data from the receiving shared dual-port RAM, and sends frame data to the back-end module through an AXI-Stream interface.
The frame receiving processing sub-module sends a minimum frame check passing signal to the route table look-up control in the module to confirm that the received frame is complete, sends a route query request to the route table look-up module and obtains route query feedback.
Further, the lookup table includes a pass-through mode and a store-and-forward mode.
Through mode: the frame receiving processing sub-module writes the buffer frame information into the receiving frame information FIFO, and directly writes the base address of the receiving frame and the relevant information thereof together with the table look-up result into the receiving frame information FIFO.
Store-and-forward mode: the frame receiving processing sub-module waits for the frame to be received, if the table lookup result contains a discarding indication, the base address of the frame is written into the receiving discarding frame base address recovery FIFO, otherwise, the relevant information of the frame is written into the receiving frame information FIFO together with the table lookup result.
Further, the flow control comprises a store-and-forward mode, a pass-through mode, a frame error mode and a back-end congestion mode.
Store-and-forward mode: the frame receiving processing sub-module stores a base address of a received frame sent by the receiving buffer base address recovery FIFO, writes the received frame into the receiving shared dual-port RAM, and writes a table look-up result and base address information into the receiving frame information FIFO; and the forwarding receiving interface adaptation submodule reads frame data and frame information from the receiving and sharing dual-port RAM according to the buffer frame information sent by the receiving frame information FIFO and sends the frame data and the frame information to the back-end module through the AXI_stream interface.
Further, the forwarding and receiving interface adaptation submodule reads a frame of data from the receiving and sharing dual-port RAM, sends a 1' b1 back pressure indication signal to the receiving back pressure signal FIFO, and sends the signal to the frame receiving and processing submodule, and the frame receiving and processing submodule sends an r_rdy primitive indication signal to the front-end module.
Through mode: on the basis of the store-and-forward mode, comparing the read-write addresses of the received frames, if the frequency of the read clock of the received shared dual-port RAM is far higher than the write clock, the frequency of the read address is reduced, and the frequency of the write address is increased.
Error frame mode: if the frame receiving processing submodule finds that the frame has CRC check error or illegal transmission word or the received frame initiator is not matched with the frame initiator supported in the strategy register or the frame initiator is fed back to discard the frame, reading the value of the strategy register, if the value prompts discard, waiting for receiving the next frame, otherwise, replacing the ending symbol of the frame with EOFa; if the frame length is smaller than the shortest frame, waiting for receiving the next frame, and sending a discarding signal to the forwarding receiving interface adaptation submodule so as to discard the frame number statistics; if the frame receiving processing submodule finds that the frame is an ultra-long frame, reading a value of a strategy register, if the value prompts discarding, writing a base address of the frame into a receiving discarded frame base address recovery FIFO, otherwise, stopping acting; if the frame receiving processing sub-module finds that the frame end symbol is invalid, the value of the strategy register is read, if the value prompts discarding, the base address of the frame is written into the receiving discarding frame base address recovery FIFO, otherwise, the frame information is written into the receiving frame information FIFO.
Further, if the extra-long frame is discarded, the current writing data is replaced by EOFa, and the reception is continued until the frame ending symbol is received, and the next frame is waited for being received.
Further, if a frame whose terminator is invalid is discarded, the current frame terminator is replaced with EOFa.
Back-end congestion mode: if the forwarding receiving interface adaptation submodule cannot timely read data from the receiving shared dual-port RAM so that the receiving buffer frame base address recovery FIFO is empty, the frame receiving processing submodule discards the frame data and sends an R_RDY primitive indication signal to the front-end module.
The forwarding and receiving interface adaptation submodule reads the buffer base address of the frame and relevant information of the frame from the receiving frame information FIFO, takes the base address as a starting address, reads frame data from the receiving shared dual-port RAM and sends the frame data to the back-end module.
Further, the forwarding receiving interface adaptation submodule writes the released base address of the buffer space into a receiving buffer frame base address recovery FIFO; if the receiving discarding frame base address recovery FIFO is not empty, the frame base address is read from the receiving discarding frame base address recovery FIFO and written into the receiving buffer frame base address recovery FIFO.
The invention has the beneficial effects that: the method is compatible with two receiving modes of direct connection and store and forward, normal frame data received by the FC engine is converted from 106.25MHz to 400MHz after table lookup, and the normal frame data is accurately transmitted to the rear end; the error tolerance mechanism is designed for the errors such as CRC check errors, illegal transmission words, ultrashort frames, ultralong frames, invalid frame ending symbols, unsupported frame starting symbols, table lookup feedback frame loss and the like, the normal operation of a receiving channel is not affected, and reports are sent to an FC engine external system; according to the processing strategy of the external system on the error frame data, the error frame data is continuously cached and sent or discarded, and the caching of the error frame data to the flow control management is not affected; when the back end is abnormally blocked, the FC engine link is ensured to form proper back pressure on the connected transmitting end, and the frame data is automatically recovered after the blocking is eliminated.
Drawings
Fig. 1 is a receive buffer schematic.
Description of the embodiments
The technical scheme of the invention is specifically described below with reference to the accompanying drawings.
The principle of the system is shown in fig. 1, and the system comprises a frame receiving processing submodule, a forwarding and receiving interface adaptation submodule, a receiving shared dual-port RAM, a receiving back pressure signal FIFO, a receiving buffer frame base address recovery FIFO, a receiving discarded frame base address recovery FIFO, a receiving frame read-write address comparator and a receiving frame information FIFO.
The frame receiving processing sub-module receives frame data and relevant information thereof from the front end module through an AXI-Stream interface, sends a minimum frame check passing signal to route table look-up control in the module, confirms that the received frame is complete, sends a route query request to the route table look-up module, acquires route query feedback, implements received frame writing operation, and writes data into a receiving shared dual-port RAM.
In the through mode, the frame receiving processing sub-module writes the buffer frame information into the receiving frame information FIFO, and directly writes the base address of the receiving frame and the relevant information thereof together with the table look-up result into the receiving frame information FIFO.
In the store-and-forward mode, the frame receiving processing submodule waits for the frame to be received, if the table lookup result contains a discarding instruction, the base address of the frame is written into the receiving and discarding frame base address recovery FIFO, otherwise, the relevant information of the frame and the table lookup result are written into the receiving frame information FIFO.
The receiving and sharing dual-port RAM and all the FIFO work asynchronously, one side of the connection frame receiving and processing submodule is a low-frequency clock domain, one side of the connection forwarding and receiving interface adaptation submodule is a high-frequency clock domain, the received FC frame data is cached, and the FC frame data is divided into a plurality of cache blocks and is subjected to flow control.
In a storage forwarding mode, the frame receiving processing submodule stores a base address of a received frame sent by the receiving buffer base address recovery FIFO, writes the received frame into the receiving shared dual-port RAM, and writes a table lookup result and base address information into the receiving frame information FIFO; and the forwarding receiving interface adaptation submodule reads frame data and frame information from the receiving and sharing dual-port RAM according to the buffer frame information sent by the receiving frame information FIFO and sends the frame data and the frame information to the back-end module through the AXI_stream interface.
And comparing the read-write addresses of the received frames on the basis of the storage forwarding mode in the through mode, and if the frequency of the read clock of the shared dual-port RAM is far higher than the write clock, reducing the frequency of the read address and increasing the frequency of the write address.
In the error frame mode, if the frame receiving processing submodule finds that the frame has CRC check errors or illegal transmission words or the received frame initiator is not matched with the frame initiator supported in the strategy register or the frame initiator is fed back to discard the frame, reading the value of the strategy register, if the value prompts to discard, waiting for receiving the next frame, otherwise, replacing the ending symbol of the frame with EOFa; if the frame length is smaller than the shortest frame, waiting for receiving the next frame, and sending a discarding signal to the forwarding receiving interface adaptation submodule so as to discard the frame number statistics; if the frame receiving processing submodule finds that the frame is an ultra-long frame, reading a value of a strategy register, if the value prompts discarding, writing a base address of the frame into a receiving discarded frame base address recovery FIFO, otherwise, stopping acting; if the frame receiving processing sub-module finds that the frame end symbol is invalid, the value of the strategy register is read, if the value prompts discarding, the base address of the frame is written into the receiving discarding frame base address recovery FIFO, otherwise, the frame information is written into the receiving frame information FIFO.
In the back-end congestion mode, if the forwarding and receiving interface adapter submodule cannot timely read data from the receiving and sharing dual-port RAM so that the receiving buffer frame base address recovery FIFO is empty, the frame receiving and processing submodule discards the frame data and sends an R_RDY primitive indication signal to the front-end module.
The forwarding receiving interface adaptation submodule reads the buffer base address of the frame and relevant information of the frame from the receiving frame information FIFO, takes the base address as a starting address, implements receiving frame reading operation, reads data from the receiving shared dual-port RAM, and sends frame data to the back-end module through an AXI-Stream interface.
Beginning with a power-on reset of the FC engine:
the FC engine establishes a link with the connected FC endpoint equipment, starts to receive FC frame data, and transmits frame information such as CRC check errors, illegal transmission words, ultrashort frames, ultralong frames, invalid frame ending symbols, unsupported frame starting symbols and the like to a frame receiving processing submodule from the front end through an AXI-Stream bus with a data bit width of 64 bits.
If the receive buffer base address recovery FIFO is empty, the frame receive processing submodule discards the received frame data and issues an indication to the front end to send an R_RDY primitive.
If the receive buffer base address recovery FIFO is not empty, the frame receive processing sub-module reads a receive base address from the FIFO and then makes corresponding processing measures according to different modes of operation.
In store-and-forward mode: if the received frame is a normal frame, a query is initiated to a lookup table module, if a discard command is not returned, the frame data is written into a receiving shared dual-port RAM, and if the discard command is returned, the current frame is discarded; if the received frame is an error frame, corresponding processing measures are made according to an error frame processing strategy, if the received frame is an error frame discarding strategy, the current frame data is discarded, and if the received frame is an error frame retaining strategy, the frame data is written into a receiving shared dual-port RAM according to the read base address information.
In the pass-through mode: if the frame is received as a normal frame, a query is initiated to a lookup table module, and the frame data is written into a storage interval taking the base address as the start in a receiving and sharing dual-port RAM according to the read base address information; if the frame is received in error, the frame data of the rest error frame types are written into the receiving shared dual-port RAM except the frame type of the frame initiator error which is not supported, and if the frame data is the frame type of the frame initiator error which is not supported, the current frame data is discarded.
When the back end allows to receive frame data and the received frame information FIFO is not empty, the forwarding and receiving interface adaptation submodule reads one frame of data from the received shared dual-port RAM and sends the frame of data to the back end through an AXI-Stream bus with 128bit data bit width.
Upon receiving the discarded frame base address reclamation FIFO not empty, the forwarding receive interface adaptation submodule immediately reads the base address data from the FIFO and then writes it into the receive buffer base address reclamation FIFO.
The foregoing is illustrative of the present invention and is not to be construed as limiting thereof, but rather as being included within the spirit and scope of the present invention.
Claims (6)
1. A FC engine frame receiving buffer management system adopts a standard AXI_stream bus interface and comprises a frame receiving processing submodule, a forwarding receiving interface adaptation submodule, a receiving shared double-port RAM, a receiving back pressure signal FIFO, a receiving buffer frame base address recovery FIFO, a receiving discarding frame base address recovery FIFO, a receiving frame read-write address comparator and a receiving frame information FIFO; the receiving and sharing dual-port RAM and all the FIFO work asynchronously, one side connected with the frame receiving and processing submodule is a low-frequency clock domain, and one side connected with the forwarding and receiving interface adaptation submodule is a high-frequency clock domain; a received frame read-write address comparator is adopted to implement Gray code conversion on the write buffer address and the read buffer address; the frame receiving processing sub-module receives frame data and related information thereof from the front-end module through an AXI-Stream interface, implements a received frame writing operation, and writes the data into a received shared dual-port RAM; receiving FC frame data received by a shared dual-port RAM cache, dividing the FC frame data into a plurality of cache blocks and performing flow control; the forwarding receiving interface adaptation submodule carries out receiving frame reading operation, reads data from a receiving shared dual-port RAM, and sends frame data to the back-end module through an AXI-Stream interface; the frame receiving processing sub-module sends a minimum frame check passing signal to the routing table look-up control in the module to confirm that the received frame is complete, sends a routing query request to the routing table look-up module and obtains routing query feedback; the table look-up comprises a direct mode and a store-and-forward mode, in the direct mode, the frame receiving processing submodule writes the buffer frame information into the received frame information FIFO, and directly writes the base address of the received frame and relevant information thereof together with the table look-up result into the received frame information FIFO; in the store-and-forward mode, the frame receiving processing submodule waits for the frame to be received, if the table lookup result contains a discarding instruction, the base address of the frame is written into a receiving discarding frame base address recovery FIFO, otherwise, the related information of the frame and the table lookup result are written into a receiving frame information FIFO;
the method is characterized in that: the flow control comprises a store-and-forward mode, a direct-through mode, an error frame mode and a back-end congestion mode;
store-and-forward mode: the frame receiving processing sub-module stores a base address of a received frame sent by the receiving buffer base address recovery FIFO, writes the received frame into the receiving shared dual-port RAM, and writes a table look-up result and base address information into the receiving frame information FIFO; the forwarding receiving interface adaptation submodule reads frame data and frame information from the receiving and sharing dual-port RAM according to the buffer frame information sent by the receiving frame information FIFO and sends the frame data and the frame information to the back-end module through an AXI_stream interface;
through mode: on the basis of a store-and-forward mode, comparing read-write addresses of received frames, and if the frequency of a read clock of the received shared dual-port RAM is far higher than that of a write clock, reducing the frequency of the read addresses and increasing the frequency of the write addresses;
error frame mode: if the frame receiving processing submodule finds that the frame has CRC check error or illegal transmission word or the received frame initiator is not matched with the frame initiator supported in the strategy register or the frame initiator is fed back to discard the frame, reading the value of the strategy register, if the value prompts discard, waiting for receiving the next frame, otherwise, replacing the ending symbol of the frame with EOFa; if the frame length is smaller than the shortest frame, waiting for receiving the next frame, and sending a discarding signal to the forwarding receiving interface adaptation submodule so as to discard the frame number statistics; if the frame receiving processing submodule finds that the frame is an ultra-long frame, reading a value of a strategy register, if the value prompts discarding, writing a base address of the frame into a receiving discarded frame base address recovery FIFO, otherwise, stopping acting; if the frame receiving processing sub-module finds that the frame ending symbol is invalid, reading a value of a strategy register, if the value prompts discarding, writing a base address of the frame into a receiving discarded frame base address recovery FIFO, otherwise, writing the frame information into a receiving frame information FIFO;
back-end congestion mode: if the forwarding receiving interface adaptation submodule cannot timely read data from the receiving shared dual-port RAM so that the receiving buffer frame base address recovery FIFO is empty, the frame receiving processing submodule discards the frame data and sends an R_RDY primitive indication signal to the front-end module.
2. The FC engine frame reception buffer management system of claim 1, wherein said store-and-forward mode further comprises: the forwarding and receiving interface adaptation submodule reads a frame of data from the receiving and sharing dual-port RAM, sends a 1' b1 back pressure indication signal to a receiving back pressure signal FIFO, and sends the signal to the frame receiving and processing submodule, and the frame receiving and processing submodule sends an R_RDY primitive indication signal to the front-end module.
3. The FC engine frame reception buffer management system of claim 1, wherein said discarding of an ultralong frame comprises: and replacing the current writing data with the EOFa, continuing to receive until the frame ending symbol is received, and waiting for receiving the next frame.
4. The FC engine frame reception buffer management system according to claim 1, wherein said discarding the frame whose end-symbol is invalid includes: the current frame terminator is replaced with EOFa.
5. The FC engine frame reception buffer management system of claim 1, wherein said sending frame data to the back-end module comprises: the forwarding and receiving interface adaptation submodule reads the buffer base address of the frame and relevant information of the frame from the receiving frame information FIFO, takes the base address as a starting address, reads frame data from the receiving shared dual-port RAM and sends the frame data to the back-end module.
6. The FC engine frame reception buffer management system of claim 5, further comprising: the forwarding and receiving interface adaptation submodule writes the released base address of the buffer space into a receiving buffer frame base address recovery FIFO; if the receiving discarding frame base address recovery FIFO is not empty, the frame base address is read from the receiving discarding frame base address recovery FIFO and written into the receiving buffer frame base address recovery FIFO.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104378161A (en) * | 2014-10-22 | 2015-02-25 | 华中科技大学 | FCoE protocol acceleration engine IP core based on AXI4 bus formwork |
| CN105187227A (en) * | 2015-06-12 | 2015-12-23 | 北京航空航天大学 | Device utilizing RMAP protocol to realize plug-and-play function of CAN bus equipment |
| CN105553636A (en) * | 2015-12-11 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | Redundancy mode FC sending channel frame synchronization circuit |
| CN106656425A (en) * | 2017-01-09 | 2017-05-10 | 电子科技大学 | Efficient error retransmission and access mechanism of fixed frame length in fiber channel |
| WO2020015201A1 (en) * | 2018-07-14 | 2020-01-23 | 苏州大学张家港工业技术研究院 | Single chip onu of fpga transceiver facing multi-application pon |
| CN111367495A (en) * | 2020-03-06 | 2020-07-03 | 电子科技大学 | Asynchronous first-in first-out data cache controller |
-
2021
- 2021-06-28 CN CN202110717677.7A patent/CN113507424B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104378161A (en) * | 2014-10-22 | 2015-02-25 | 华中科技大学 | FCoE protocol acceleration engine IP core based on AXI4 bus formwork |
| CN105187227A (en) * | 2015-06-12 | 2015-12-23 | 北京航空航天大学 | Device utilizing RMAP protocol to realize plug-and-play function of CAN bus equipment |
| CN105553636A (en) * | 2015-12-11 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | Redundancy mode FC sending channel frame synchronization circuit |
| CN106656425A (en) * | 2017-01-09 | 2017-05-10 | 电子科技大学 | Efficient error retransmission and access mechanism of fixed frame length in fiber channel |
| WO2020015201A1 (en) * | 2018-07-14 | 2020-01-23 | 苏州大学张家港工业技术研究院 | Single chip onu of fpga transceiver facing multi-application pon |
| CN111367495A (en) * | 2020-03-06 | 2020-07-03 | 电子科技大学 | Asynchronous first-in first-out data cache controller |
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