CN105512070B - A kind of control system based on universal serial bus - Google Patents
A kind of control system based on universal serial bus Download PDFInfo
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- CN105512070B CN105512070B CN201510888530.9A CN201510888530A CN105512070B CN 105512070 B CN105512070 B CN 105512070B CN 201510888530 A CN201510888530 A CN 201510888530A CN 105512070 B CN105512070 B CN 105512070B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3812—USB port controller
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Abstract
The invention discloses a kind of control systems based on universal serial bus, and in particular to communication control field.It solves in the prior art that CPU is limited to controlling the size for wiring board, and the quantity of interconnection signal is more between wiring board and bottom plate in system, be unfavorable for PCB layout, system reliability difference deficiency.The control system based on universal serial bus, including multigroup universal serial bus circuit, include universal serial bus per string formation row bus circuit, universal serial bus main equipment and serial bus slave, universal serial bus main equipment is interconnected with serial bus slave by universal serial bus, the transmission signal of universal serial bus includes chip selection signal, clock signal, serial bus data input signal, serial bus data output signal, clock output signal, universal serial bus main equipment connects CPU by interface signal, interface signal includes cpu i/f chip selection signal, read signal, write signal, address signal, data-signal, clock input signal.
Description
Technical field
The present invention relates to communication control fields, and in particular to a kind of control system based on universal serial bus.
Background technology
There are many type of bus, divide by use scope, can be divided into computer (including peripheral hardware) bus, measurement and control bus and net
Network communication bus；Divide by data mode, there is parallel-by-bit transmission bus and Bits Serial transmission bus；Parallel transmission bus is pressed
Its data-bus width transmitted, and 8,16 and 32 BITBUS networks, etc. can be divided into.No matter which kind of bus, they are total to
Same-action is the template in computer or TT＆C system or various equipment can be linked to be an entirety by common signal wire, with
Just information exchange to each other is carried out.In order to effectively and reliably carry out information exchange and to bus signals and its transmission rule and
It transmits a series of regulations that the physical mediums of these signals is done and is known as bus protocols.Ratified or recommended by a certain standardization body
Bus protocols be certain bus standard.
The parallel bus being commonly used on computer has isa bus, pci bus.Isa bus has 62 signal wires by one
The socket for having 36 numbers lines with one is formed, and is had 23 address wires, 16 data lines, memory read/write line, IO read-writes line, is interrupted
Ask line, DMA request line, DMA line of response, 14.31818MHz high-speed clock signal OSC, 4.77MHz clock signal of system etc.
Deng.The read-write of memory or IO are at least 4 system clock cycles, therefore the data throughput of isa bus is up to 2.39MB/
s。
Pci bus originates from microcomputer, has become computer bus standard now, working frequency 33MHz,
66MHz, data bits are 32,64, and transmission bandwidth reaches 132MB/s, 264MB/s, 528MB/s, has pole than isa bus
Big improvement, widely used at present is the pci bus of 32 33MHz.Pci bus signal is as shown in Figure 1.System signal includes
Reset signal RST# and clock signal clk.Arbitrating signals have bus application REQ# and bus grant signal GNT#.Interface Controller is believed
Number including the FRAME# signals that main equipment starts PCI, main equipment gets out signal IRDY#, and slave device gets out signal TRDY#,
Stop data transfer signals STOP#, locking signal LOCK#, initialization apparatus selection signal IDSEL#, equipment selection signal
DEVSEL#.PCI does not have the read-write in general data period, but uses the read-write category of command code formal definition pci cycle
Property.Each pci cycle is started by main equipment, in first clock cycle, AD [31..0] signal transmission address information, and C/BE#
[3..0] forms control command, defines pci cycle.After second clock, AD [31..0] carries out data transmission, C/BE# [3..0]
Identification byte effective information.Parity signal is PAR.Error reporting signal has data parity check error reporting signal
PERR#, system mistake report signal SERR#.In addition, also interrupt signal INTA#, INTB#, INTC#, INTD#.
GPIB be it is a kind of between programmable instrument device, instrument and computer inter even international compiling
Gift of money for a friend going on a journey device Digital Interface Standard.Gpib interface bus is a kind of bidirectional bus of asynchronous data transfer mode, using the spring of 24 feet
Chip plug.The information transmitted between equipment by cable has two classes, and one kind is for the information of interface system self-management；
Another kind of is information used in the equipment interconnected by interface system.Gpib bus has 16 signal wires, wherein 8 are data
Line DIO1~DIO8,3 communications link DAV data are effective, the unripe reception data of NRFD, NDAC data have not received
Finish, 5 root interface management line IFC interface clears, ATN pays attention to, SRQ service requests, REN far are enabled, EOI terminates or identifies.
Control system based on parallel bus, interconnection signal is more between each wiring board and bottom plate, generally there is address/data
Line, also control line cause pcb board wiring complicated.For example, when using 32 pci bus, at least needed on each wiring board
51 root interface signal wires cause the wiring difficulty of pcb board to increase.In order to reduce pcb board wiring complexity, the reliable of system is improved
Universal serial bus may be used in property, the interconnection signal between wiring board.
Traditionally, the interface of PC machine and peripheral hardware is divided into serial ports and parallel port.Serial ports is generally used to connection mouse and external
Modem, data transmission rate is from every number of seconds kbps to hundreds of kbps.The data transmission rate of parallel port is generally used to up to 1MB per second
Connect printer, scanner etc..
For traditional interface mode when with keyboard, mouse, printer, Modem when Peripheral Interfaces, data transmission bauds is low,
Poor expandability, it is impossible to which plug and play can not adapt to the rapid development of PC software and hardwares.For the problem present on, again
Be born universal serial bus (Universal Serial Bus, abbreviation USB), on the computer and peripheral hardware for supporting USB
Universal accepted standard can support keyboard, mouse, wideband multimedia equipment, scanner, printer and storage device etc..USB is
A kind of universal serial bus of point-to- point communication, the transmission speed provided have low speed 1.5Mbps, full speed 12Mbps, high speed
480Mbps etc. is several.The shortcomings that USB system is agreement complexity, needs the support of operating system, the design difficulty of driver compared with
It is high.
Invention content
It is limited to controlling the size for wiring board the purpose of the present invention is being directed to CPU in the prior art, in system wiring board with
The quantity of interconnection signal is more between bottom plate, be unfavorable for PCB layout, system reliability difference deficiency, it is proposed that a kind of CPU can be real
Now to the control of multiple wiring boards, in reduction system between wiring board and bottom plate interconnection signal quantity, facilitate the wiring of PCB,
A kind of control system based on universal serial bus of the reliability of raising system.
The present invention specifically adopts the following technical scheme that：
A kind of control system based on universal serial bus, including multigroup universal serial bus circuit, universal serial bus circuit described in every group
Including universal serial bus, universal serial bus main equipment and serial bus slave, the universal serial bus main equipment and universal serial bus are from setting
Standby to be interconnected by universal serial bus, the transmission signal of the universal serial bus is defeated including chip selection signal, clock signal, serial bus data
Enter signal, serial bus data output signal, clock output signal, universal serial bus main equipment connects CPU, institute by interface signal
It states interface signal and includes cpu i/f chip selection signal, read signal, write signal, address signal, data-signal, clock input signal.
Preferably, the chip selection signal of the universal serial bus is output signal, and low level is effective, on the clock output signal
It rises along effective, the serial bus data input signal is connected with the data output signal of serial bus slave, universal serial bus
Data output signal is connected with the data input signal of serial bus slave, and the clock output signal makes universal serial bus from setting
It is standby to generate control sequential.
Preferably, the cpu i/f chip selection signal is input signal, and low level is effective, and the read signal is input signal,
Low level is effective, and the write signal is input signal, and low level is effective, and described address signal is input signal, the data letter
Number for input/output signal, the clock input signal is used, universal serial bus main equipment generates control sequential.
Preferably, the universal serial bus main equipment generates the first interrupt request singal, and the serial bus slave generates
Second interrupt request singal can select to use as needed.
Preferably, the universal serial bus main equipment includes idle mode, main sending mode and main reception pattern, described serial
Bus slave includes idle mode, from reception pattern and from sending mode.
The invention has the advantages that：Using the control system based on universal serial bus, CPU can be realized to multiple lines
The control of road plate, while reduce the quantity of interconnection signal between wiring board and bottom plate in system, the wiring of PCB is facilitated, is carried
The high reliability of system.
Description of the drawings
Fig. 1 pci bus signals；
Fig. 2 this serial bus control system wiring board connection diagrams；
Fig. 3 this serial bus control system functional block diagrams；
Fig. 4 universal serial bus main equipment, slave device connection diagram；
Fig. 5 universal serial bus write order sequence diagrams；
Fig. 6 universal serial bus read command sequence diagrams；
The main sending mode sequence diagram of Fig. 7 universal serial bus；
The main reception pattern sequence diagram of Fig. 8 universal serial bus；
Universal serial bus main sending mode sequence diagram when Fig. 9 sets delay register；
Universal serial bus main reception pattern sequence diagram when Figure 10 sets delay register；
The increased interrupt status of Figure 11/interrupt clear register circuit.
Specific embodiment
The specific embodiment of the present invention is described further in the following with reference to the drawings and specific embodiments：
As described in Fig. 2-4, a kind of control system based on universal serial bus, including multigroup universal serial bus circuit, per string formation row
Bus circuit includes universal serial bus, universal serial bus master (Master) circuitry and universal serial bus from (Slaver) circuitry,
Universal serial bus main equipment is interconnected with serial bus slave by universal serial bus, and the transmission signal of universal serial bus includes chip selection signal
(SCS), clock signal (SCLK), serial bus data input signal (SDI), serial bus data output signal (SDO), clock
Output signal (CLKOUT), universal serial bus main equipment connect CPU by interface signal, and interface signal includes cpu i/f piece choosing letter
Number (/CS), read signal (/RD), write signal (/WR), address signal (A [1..0]), data-signal (D [x..0]), clock input
Signal (CLK).Wherein x+1 is the digit of data/address bus, can be 8,16,24,32,64.Universal serial bus main equipment generates first
Interrupt request singal (/INT), serial bus slave generate the second interrupt request singal (/S_INT).
The chip selection signal of universal serial bus is output signal, and low level is effective, and clock output signal rising edge is effective, serial total
Line data input signal is connected with the data output signal of serial bus slave, serial bus data output signal with it is serial total
The data input signal of line slave device is connected, and clock output signal makes serial bus slave generate control sequential.
Cpu i/f chip selection signal is input signal, and low level is effective, and read signal is input signal, and low level is effective, is write letter
Number for input signal, low level is effective, and address signal is input signal, and data-signal is input/output signal, defeated using clock
Enter signal, universal serial bus main equipment generates control sequential.
Universal serial bus main equipment generates the first interrupt request singal (/INT), and serial bus slave generates the second interruption please
Seek signal (/S_INT).It can select to use as needed.For NMOSFET type circuits ,/INT signal and/S_INT signal suggestions
Using open-drain pole (open drain) output circuit structure, external pull-up resistor need to be connect.For NPN type triode circuit ,/INT
Signal and/S_INT signals are proposed with open collector (open collector) output circuit structure, need to connect external pull-up electricity
Resistance.
Universal serial bus main equipment includes idle mode, main sending mode and main reception pattern, passes through read status register
Series bus controller state machine information can be obtained.Serial bus slave includes idle mode, from reception pattern and from transmission
Pattern, status register storage serial bus slave state machine information.
Universal serial bus write order sequence diagram of the present invention is as shown in figure 5, with 7 bit addressing spaces, 8 data instances.It is serial total
The write operation of line forms write command byte and latter one byte or multiple bytes by the addresses of 7 and the write order of 1
Write data composition.SCS becomes low level first, and expression will be written and read universal serial bus.After SCS becomes low level, SCLK
8 pulses are sent out, rising edge is effective, and SDO sends out the addressable address of 7 and the write order of 1, write order are represented with low level.
Then SCLK sends out 8 pulses, and rising edge is effective, and for data write operation, while SDO shifts output data byte.For n
The write operation of byte, SCLK send out n and are multiplied by 8 shift clock pulses.After completing write order, SCS signals are set to high level.Fig. 5
Shown example is into universal serial bus address 0x78, and 0xaa and 0x55 is written successively.
Universal serial bus read command sequence diagram is as shown in fig. 6, with 7 bit addressing spaces, 8 data instances.The reading of universal serial bus
Operation, read command byte and the reading of latter one byte or multiple bytes are formed by the addresses of 7 and the read command of 1
According to composition.SCS becomes low level first, and expression will be written and read universal serial bus.After SCS becomes low level, SCLK sends out 8
Pulse, rising edge is effective, and SDO sends out the addressable address of 7 and the read command of 1, read command are represented with high level.Then SCLK
8 pulses are sent out, rising edge is effective, and for data reading operation, while SDI inputs shifted data byte.For writing for n byte
Operation, SCLK send out n and are multiplied by 8 shift clock pulses.After completing read command, SCS signals are set to high level.Example shown in Fig. 6
It is from the 0x78 of universal serial bus address, reads in 0xaa and 0x55 successively.
Similar, universal serial bus of the present invention can be written and read operation to 15 bit addressing spaces, 16 data, can also be right
23 bit addressing spaces, 24 data are written and read operation, can also be written and read operation to 31 bit addressing spaces, 32 data,
Operation can also be written and read to 63 bit addressing spaces, 64 data.
When using 8 bit CPU interface, this Serial Bus Implementers is 8 bit patterns, i.e. each operating procedure production of universal serial bus
Raw 8 serial clocks, each register of series bus controller are designed to 8.Command register include 7 bit address A6~
A0 and Read-write Catrol positionWhich address expression will operate, and be read operation or write operation.7 bit address can
To address 128 address spaces.When Read-write Catrol position is 0, expression will carry out write operation, represent to carry out read operation when being 1.
When using 16 bit CPU interface, this Serial Bus Implementers is each operating procedure of 16 bit patterns, i.e. universal serial bus
16 serial clocks are generated, the register design of series bus controller is 16.Command register include 15 bit address A14~
A0 and Read-write Catrol positionAddressing space is 32k, i.e. 32768 units.
When using 32 bit CPU interface, this Serial Bus Implementers is each operating procedure of 32 bit patterns, i.e. universal serial bus
32 serial clocks are generated, the register design of series bus controller is 32.Command register include 31 bit address A30~
A0 and Read-write Catrol positionAddressing space is 2G, i.e. 2147483648 units.
The CPU access ports of series bus controller are 4, two address wires of A1 and A0 are needed to address, register
Summarize as shown in table 1.When the interrupt request singal/S_INT generated using serial bus slave is as the interrupt requests to CPU
It during signal, needs to increase a read-write port, register is as shown in table 2, and at this moment needing, which increases an address wire A2, comes
Addressing.Illustrate the design of series bus controller of the present invention with 8 bit patterns below.
The data bit of status register is as shown in table 3, is read-only register, universal serial bus control is represented with 8 bit S
The state machine information of device processed.
The data bit of delay register is as shown in table 4, is write-only register, and universal serial bus control is controlled with 8 bit T
The delay of device processed defaults to numerical value 0, and practical delay time is KT, and K is constant, is some time cycle.
The data bit of command register is as shown in table 5, is read-write register, universal serial bus is represented with 7 bit A
Addressable address, with 1 Read-write Catrol positionIt is read operation to be carried out or write operation to represent this instruction, and being represented for 0 will
Write operation is carried out, represents to carry out read operation for 1.
The data bit of data register is as shown in table 6, is read-write register, with 8 bit D represents that string is written
The data of row bus slave device and the data read from serial bus slave.
The data bit of write control register is as shown in table 7, have Reset_SCS, Clear_INT, Create_event,
Reset, Mode [1..0] data bit, physical significance are as follows.
SCS output signals for resetting SCS signals, are put 1, the position after the completion of reset by Reset_SCS data bit when being 1
0 is automatically become, does not influence SCS signals when being 0.
Clear_INT data bit, for removing/INT signal and mark, general/INT output signals put 1 when being 0, while clearly
Except INT status datas position.
Create_event data bit, for generating next sequential of universal serial bus.Universal serial bus is triggered when being 1 to generate
Next sequential, after the completion the position automatically become 0.
Reset data bit resets entire bus when being 1, and the position automatically becomes 0 after the completion of reset, does not influence bus when being 0
Signal.
Mode [1..0] data bit, scheme control position select non-interrupted pattern when being 1, and selection edge type interrupts mould when being 2
Formula selects level-type interrupt mode when being 3, keep original interrupt mode when being 0, default to level-type interrupt mode.Non-
Under interrupt mode ,/INT signal line exports high level always.Under edge type interrupt mode, when having interrupt requests ,/INT signal
Line generates low level pulse signal, while INT status datas position is 1.Under level-type interrupt mode, without interrupt requests
When ,/INT signal line is high level, and when having interrupt requests ,/INT signal line becomes low level, while INT status datas position is
1。
| Register name | Register functions | A2 | A1 | A0 | Read-write type |
| Status register | State machine information | 0 | 0 | 0 | It reads |
| Delay register | Control delay | 0 | 0 | 0 | It writes |
| Command register | Order | 0 | 0 | 1 | Read/write |
| Data register | Data | 0 | 1 | 0 | Read/write |
| Control register | Control/state | 0 | 1 | 1 | Read/write |
Table 1
| Register name | Register functions | A2 | A1 | A0 | Read-write type |
| Interrupt status | Interrupt status | 1 | 0 | 0 | It reads |
| Interrupt clear | It is clear to interrupt | 1 | 0 | 0 | It writes |
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
The data bit of read control register is as shown in table 8, there is SCS, INT, Create_event, Reset, Mode [1..0]
Data bit, physical significance are as follows.
SCS status datas position shows the state of SCS signals.SCS signal wires are high level when being 1, SCS signal wires when being 0
For low level, represent that the choosing of universal serial bus piece is effective.
INT status datas position, the state of display/INT signal.In level-type interrupt mode, it is for 0 when/INT signal line
It is low level that high level, which is 1 when/INT signal line, and expression produces interrupt requests.In edge type interrupt mode, when being 0/
INT signal line does not generate low level pulse, produces low level pulse for 1 when/INT signal line, expression produces interruption please
It asks.In non-interrupted pattern, when being 0 inside/INT signal is high level, when being 1 inside/INT signal is low level, represent production
Interrupt requests state is given birth to.
Create_event status datas position, the state of Create_even data bit in display control register.
Reset status datas position represents that controller is in reset state when being 1, represent that controller resets when being 0 and complete.
Mode [1..0] status datas position, mode state position are non-interrupted pattern when being 1, are that edge type interrupts mould when being 2
Formula is level-type interrupt mode when being 3, defaults to level-type interrupt mode.
When use serial bus slave /S_INT signals generate to the interrupt request singal of CPU when, need increase by one
A addressable read-write register, as shown in table 9, the register only have 1, the D of corresponding CPU0Data line.It is deposited when reading this
During device, which is interrupt status register, represents to produce interrupt requests state when value is 1, represents do not have when value is 0
Have and generate interrupt requests state.When writing this register, which is interrupt clear register, as long as writing this deposit
Device, internal interrupt request signal/INT_O are just set to 1, and interrupt status register is set to 0.
There are three types of patterns, i.e. idle mode (idle for series bus controller (serial bus controller)
Mode), main sending mode (master transmitter mode), main reception pattern (master receiver mode).It is logical
Series bus controller state machine information can be obtained by crossing read status register.
Idle mode represents that master controller is in idle condition, and at this moment the value of status register is hexadecimal 0xE8.
When this serial operation instruction is when writing type, master controller is in main sending mode, the value point of status register
It Wei not 0xA0,0xE0,0xA2,0xE2.When series bus controller, which is in, sends address state, the value of status register is
0xA0.Address is sent, and after generating the delay that delay register is specified, the value of status register becomes 0xE0, generates simultaneously
The INT mode bits of internal interrupt signal, i.e. control register are 1, and when in interrupt mode ,/INT signal line generates low simultaneously
Level or low level pulse interrupt request singal.When series bus controller is in transmission data state, status register
It is worth for 0xA2.Data are sent, and after generating the delay that delay register is specified, the value of status register becomes 0xE2, simultaneously
Internal interrupt signal is generated, when in interrupt mode ,/INT signal line generates interrupt request singal.
When this serial operation instruction is reads type, master controller is in main reception pattern, the value point of status register
It Wei not 0xA0,0xE1,0xA3,0xE3.When series bus controller, which is in, sends address state, the value of status register is
0xA0.Address is sent, and after generating the delay that delay register is specified, the value of status register becomes 0xE1, generates simultaneously
The INT mode bits of internal interrupt signal, i.e. control register are 1, and when in interrupt mode ,/INT signal line generates low simultaneously
Level or low level pulse interrupt request singal.When series bus controller, which is in, receives data mode, status register
It is worth for 0xA3.Data receiver finishes, and after generating the delay that delay register is specified, the value of status register becomes 0xE3, simultaneously
Internal interrupt signal is generated, when in interrupt mode ,/INT signal line generates interrupt request singal.
There are three types of patterns, i.e. idle mode (idle for serial bus slave (serial bus slave device)
Mode), from sending mode (slave transmitter mode), from reception pattern (slave receiver mode).State
Register stores serial bus slave state machine information.Illustrate setting for serial bus slave of the present invention below with 8 bit patterns
Count thought.
Idle mode represents that slave device is in idle condition, and at this moment the value of status register is hexadecimal 0xF8.
When this serial operation instruction is when writing type, slave device is in from reception pattern, and the value of status register is distinguished
For 0xB1,0xF1,0xB3,0xF3,0xB5.When slave device detects that S_SCS signal wires become low level from high level ,/S_
INT signal line is set to high level.When slave device, which is in, receives address state, the value of status register is 0xB1.Address receives
It finishes, the value of status register becomes 0xF1, and/S_INT signal wires generate low level interrupt request singal simultaneously.At slave device
When data mode is received, the value of status register is 0xB3, and/S_INT signal wires are set to high level.Data receiver finishes, shape
The value of state register becomes 0xF3, and/S_INT signal wires generate low level interrupt request singal simultaneously.When S_SCS signal wires become
High level, this command reception finish, and slave device is in execute instruction state, and the value of status register becomes 0xB5 ,/S_INT
Signal wire is set to high level.Instruction is finished, and slave device is in idle condition, and the value of status register becomes 0xF8 ,/S_
INT signal line generates low level interrupt request singal simultaneously.
When this serial operation instruction is reads type, slave device is in from sending mode, and the value of status register is distinguished
For 0xB1,0xB4,0xF0,0xB2,0xF2.When slave device detects that S_SCS signal wires become low level from high level ,/S_
INT signal line is set to high level.When slave device, which is in, receives address state, the value of status register is 0xB1.Address receives
It finishes, performs the instruction, the value of status register becomes 0xB4.After DSR, the value of status register becomes 0xF0 ,/
S_INT signal wires generate low level interrupt request singal simultaneously.When slave device is in transmission data state, status register
It is worth for 0xB2 ,/S_INT signal wires are set to high level.Data are sent, and the value of status register becomes 0xF2 ,/S_INT letters
Number line generates low level interrupt request singal simultaneously.When slave device detects that S_SCS signal wires become high level from low level
When ,/S_INT signal wires are set to high level.
Fig. 7 is the main sending mode sequence diagram of universal serial bus.Wherein, CLK ,/CS ,/RD ,/WR, A [1..0], D [7..0] ,/
INT is series bus controller and cpu i/f signal.SCS, SCLK, SDI, SDO are series bus controller end signal,
STATUS is series bus controller status register.S_SCS, S_SCLK, S_SDI, S_SDO believe for serial bus slave end
Number ,/S_INT exports interrupt request singal for serial bus slave, and S_STATUS is serial bus slave status register.
0xAA and 0x55 is written in the 0x78 address locations of CPU serially buses successively in this example.Series bus controller
During in the free time, the value of status register is 0xE8.CPU serially bus control unit command register write-in 0xF0, start
Universal serial bus is main to send operation, and SCS signals become low, and the value of status register becomes 0xA0, and SCLK generates 8 clocks
Pulse, SDO Serial outputs 0xF0, SDO output finish, and the value of status register becomes 0xE0, represents that last step operation finishes,
Under level-type interrupt mode, interrupt request singal/INT becomes low, under edge type interrupt mode, interrupt request singal/INT
Low level pulse is generated, while the INT positions of read control register are 1, expression produces interrupt requests state.CPU is serially
The control register write-in 0x04 of the data register write-in 0xAA of bus control unit, serially bus control unit, interrupt requests
Signal/INT becomes high, and the INT positions of read control register are 0, and expression removes interrupt requests state, the value of status register
Become 0xA2, while start the next step of universal serial bus operation.SCLK generates 8 clock pulses, SDO SOD serial output datas
0xAA, SDO output finish, and the value of status register becomes 0xE2, represents that last step operation finishes, in level-type interrupt mode
Under, interrupt request singal/INT becomes low, and under edge type interrupt mode, interrupt request singal/INT generates low level pulse,
The INT positions of read control register are 1 simultaneously, and expression produces interrupt requests state.If there is next data will export, example
Such as, CPU serially bus control unit data register write-in 0x55, serially bus control unit control register write-in
0x04, interrupt request singal/INT become high, and the INT positions of read control register are 0, and expression removes interrupt requests state,
The value of status register becomes 0xA2, while starts the next step of universal serial bus operation.SCLK generates 8 clock pulses,
SDO SOD serial output datas 0x55, SDO output finishes, and the value of status register becomes 0xE2, represents that last step operation finishes,
Under level-type interrupt mode, interrupt request singal/INT becomes low, under edge type interrupt mode, interrupt request singal/INT
Low level pulse is generated, while the INT positions of read control register are 1, expression produces interrupt requests state.Data have been sent
Control register the write-in 0x01, interrupt request singal/INT of Bi Hou, CPU serially bus control unit become high, read control and post
The INT positions of storage are 0, and expression removes interrupt requests state, and SCS signals become high, this operation is completed, status register
Value become 0xE8.
When series bus controller is main sending mode, serial bus slave is in from reception pattern.Universal serial bus
When slave device is in idle, the value of status register is 0xF8.After serial bus slave detects that S_SCS signals become low,
The value of status register becomes 0xB1, and 8 clock pulses, S_SDI serial received order datas, in this example are received on S_SCLK
In be 0xF0, S_SDI inputs finish, and the value of status register becomes 0xF1, represents that last step operation finishes, interrupt requests letter
Number/S_INT becomes low.SCLK subsequently receives 8 clock pulses, in the rising edge status register of the 1st clock pulses
Value becomes 0xB3, and S_SDI Serial data receivings finish, and numerical value is 0xAA in this example, and the value of status register becomes 0xF3, table
Show that last step operation finishes, interrupt request singal/S_INT becomes low.If there is next data will input, connect on S_SCLK
8 clock pulses are received, become 0xB3 in the value of the rising edge status register of the 1st clock pulses, S_SDI serial datas connect
Harvest complete, numerical value is 0x55 in this example, and the value of status register becomes 0xF3, represents that last step operation finishes, and interrupting please
Signal/S_INT is asked to become low.After serial bus slave detects that S_SCS signals become height, by interrupt request singal/S_INT
Height is set to, represents that this instruction has received.The value of status register becomes 0xB5, and expression is carrying out this instruction.
After having performed this instruction, interrupt request singal/S_INT is set to low, serial bus slave is in idle condition, and state is posted
The value of storage becomes 0xF8.
Fig. 8 is the main reception pattern sequence diagram of universal serial bus, in this example CPU from the 0x78 address locations of universal serial bus successively
Read 0xAA and 0x55.When series bus controller is in idle, the value of status register is 0xE8.CPU serially total line traffic controls
The command register write-in 0xF1 of device processed starts main receive of a universal serial bus and operates, and SCS signals become low, Status register
The value of device becomes 0xA0, and SCLK generates 8 clock pulses, and SDO Serial outputs 0xF1, SDO output finishes, the value of status register
Become 0xE1, represent that last step operation finishes, under level-type interrupt mode, interrupt request singal/INT becomes low, on side
Along under type interrupt mode, interrupt request singal/INT generates low level pulse, while the INT positions of read control register are 1, table
Show and produce interrupt requests state.CPU serially bus control unit control register write-in 0x04, interrupt request singal/INT
Become high, the INT positions of read control register are 0, and expression removes interrupt requests state, and the value of status register becomes
0xA3, while start the next step of universal serial bus operation.SCLK generates 8 clock pulses, SDI serial input datas
0xAA, SDI input finish, and the value of status register becomes 0xE3, represents that last step operation finishes, in level-type interrupt mode
Under, interrupt request singal/INT becomes low, and under edge type interrupt mode, interrupt request singal/INT generates low level pulse,
The INT positions of read control register are 1 simultaneously, and expression produces interrupt requests state.Then CPU reads series bus controller
Data register, in this example numerical value be 0xAA.If necessary to read next data, the control of CPU serially bus control units
0x04 is written in register processed, and interrupt request singal/INT becomes high, and the INT positions of read control register are 0, during expression removes
Disconnected solicited status, the value of status register become 0xA3, while start the next step of universal serial bus operation.SCLK generates 8
A clock pulses, SDI serial input datas 0x55, SDI input finish, and the value of status register becomes 0xE3, represents last step
Rapid end of operation, under level-type interrupt mode, interrupt request singal/INT becomes low, under edge type interrupt mode, interrupts
Request signal/INT generates low level pulse, while the INT positions of read control register are 1, and expression produces interrupt requests shape
State.After data receiver, the control register write-in 0x01 of CPU serially bus control units, interrupt request singal/INT becomes
For height, the INT positions of read control register are 0, and expression removes interrupt requests state, and SCS signals become high, this has been operated
Into the value of status register becomes 0xE8.
When series bus controller is main reception pattern, serial bus slave is in from sending mode.Universal serial bus
When slave device is in idle, the value of status register is 0xF8.After serial bus slave detects that S_SCS signals become low,
The value of status register becomes 0xB1, and 8 clock pulses, S_SDI serial received order datas, in this example are received on S_SCLK
In be 0xF1, S_SDI inputs finish, and the value of status register becomes 0xB4, represent that serial bus slave is preparing to read
Data, be ready to read data after, the value of status register becomes 0xF0, represents that last step operation finishes, interrupt
Request signal/S_INT becomes low.SCLK subsequently receives 8 clock pulses, is posted in the rising edge state of the 1st clock pulses
The value of storage becomes 0xB2, and S_SDO serial datas are sent, and is 0xAA in this example, and the value of status register becomes 0xF2,
Represent that last step operation finishes, interrupt request singal/S_INT becomes low.If there is next data will export, on S_SCLK
8 clock pulses are received, become 0xB2, S_SDO serial datas in the value of the rising edge status register of the 1st clock pulses
It is sent, is 0x55 in this example, the value of status register becomes 0xF2, represents that last step operation finishes, interrupt requests
Signal/S_INT becomes low.After serial bus slave detects that S_SCS signals become height, interrupt request singal/S_INT is put
For height, represent that this instruction has been finished.Serial bus slave is in idle condition, and the value of status register becomes
0xF8。
Universal serial bus main sending mode sequence diagram when Fig. 9 is setting delay register.When Figure 10 is setting delay register
The main reception pattern sequence diagram of universal serial bus.The value for setting delay register is T, then the actual time delay time is KT, and K is constant, is
Some time cycle.In main sending mode, actually the 0xA0 and 0xA2 states of series bus controller are extended respectively
The KT times, that is to say, that the KT times have been postponed into the generation of 0xE0 and 0xE2 states and/INT interrupt request singals respectively.In master
In reception pattern, 0xA0 the and 0xA3 states of series bus controller are actually extended into the KT times respectively, that is to say, that will
The KT times have been postponed in the generation of 0xE1 and 0xE3 states and/INT interrupt request singals respectively.This use/INT signal generate to
During the interrupt request singal of CPU, it is contemplated that the processing delay of serial bus slave is of great significance, the delay time of setting
More than the response time of serial bus slave.
The interrupt request singal that series bus controller generates is /INT, the interrupt requests letter that serial bus slave generates
Number for/S_INT.Can use/INT signal or/S_INT signals generated to the interrupt request singal of CPU.When using/INT signal
When generating to the interrupt request singal of CPU, direct general/INT signal is as interrupt request singal.
Under edge type interrupt mode, when use/S_INT signals generate to the interrupt request singal of CPU when, directly will/
S_INT signals are as interrupt request singal.When use/S_INT signals generate to the interrupt request singal of CPU when, need to increase
One addressable read-write register, as shown in table 9, the register only have 1, the D of corresponding CPU0Data line.It is posted when reading this
During storage, which is interrupt status register, represents to produce interrupt requests state when value is 1, value represents when being 0
Interrupt requests state is not generated.When writing this register, which is interrupt clear register, as long as writing this deposit
Device, internal interrupt request signal/INT_O are just set to 1, and interrupt status register is set to 0.At this moment it needs in increasing as shown in figure 11
Disconnected processor logic, under level-type interrupt mode, general/INT_O signals are exported to the interrupt requests input pin of CPU, on side
Along under type interrupt mode, general/S_INT signals are exported to the interrupt requests input pin of CPU./ S_INT signals often generate a decline
Edge, internal interrupt request signal/INT_O are set to 0, and interrupt status register is set to 1, writes interrupt clear register, internal interrupt
Request signal/INT_O is set to 1, and interrupt status register is set to 0.
When there is multiple wiring boards, can by multiple universal serial bus /INT signal or/S_INT signals be connected to CPU not
On same interrupt requests input pin.Can also by multiple universal serial bus /INT signal or/S_INT signals be connected to the one of CPU
On a interrupt requests input pin, as long as soon as logic at this moment be /INT signal or/S_INT signals produce interrupt requests,
CPU interrupt request singals are generated, are equivalent to and operation, until the interrupt request singal of CPU is proposed with opening with pull-up resistor
Drain electrode or open collector output circuit structure.CPU needs to inquire the read control register of each series bus controller successively
INT status datas position or interrupt status register, inquiry are to produce interrupt requests on which universal serial bus, when software needs clearly
During except interrupt requests state, the Clear_INT data bit or interrupt clear register of the corresponding control register of CPU write.
When the SCS, SCLK of this universal serial bus, SDI, SDO ,/S_INT signals use difference output form, have good
Anti- common mode interference ability, available for long-line transmission.At this moment CLKOUT signals can not be transmitted, serial bus slave uses local
Clock signal.The signal transmitted on universal serial bus for SCS ,/SCS, SCLK ,/SCLK, SDI ,/SDI, SDO ,/SDO ,/
S_INT、S_INT.In the transmitting terminal of signal, using differential driver, single-ended signal is changed into differential signal, in connecing for signal
Differential signal using differential receiver, is changed into single-ended signal by receiving end.At this moment this universal serial bus can be used for inter-system data
Transmission, since this universal serial bus employs synchronous data transfer mode, than the speed of the asynchronous serial transmissions mode such as RS232
Rate greatly improves.
It is the design philosophy that universal serial bus main equipment and serial bus slave of the present invention are illustrated with 8 bit patterns in specification
And circuit sequence, it can be easy to be generalized to 16,24,32,64 bit-serial bus control systems.Using high-speed figure
This universal serial bus of circuit design, working frequency are more than the data of 100MHz, universal serial bus main equipment and serial bus slave
Exchange rate is high.Multipair universal serial bus can concurrent working.When there is multigroup universal serial bus in system, the data throughput of system is high.
Certainly, above description is not limitation of the present invention, and the present invention is also not limited to the example above, this technology neck
The variations, modifications, additions or substitutions that the technical staff in domain is made in the essential scope of the present invention should also belong to the present invention's
Protection domain.
Claims (3)
1. a kind of control system based on universal serial bus, which is characterized in that serial described in every group including multigroup universal serial bus circuit
Bus circuit includes universal serial bus, universal serial bus main equipment and serial bus slave, the universal serial bus main equipment with it is serial
Bus slave is interconnected by universal serial bus, and the transmission signal of the universal serial bus includes chip selection signal, clock signal, serial total
Line data input signal, serial bus data output signal, clock output signal, universal serial bus main equipment are connected by interface signal
CPU is met, it is defeated that the interface signal includes cpu i/f chip selection signal, read signal, write signal, address signal, data-signal, clock
Enter signal, the chip selection signal of the universal serial bus is output signal, and low level is effective, and the clock output signal rising edge has
Effect, the serial bus data input signal are connected with the data output signal of serial bus slave, and serial bus data is defeated
Go out signal with the data input signal of serial bus slave to be connected, the clock output signal generates serial bus slave
Control sequential, the cpu i/f chip selection signal be input signal, low level is effective, the read signal be input signal, low level
Effectively, the write signal is input signal, and low level is effective, and described address signal is input signal, and the data-signal is defeated
Enter output signal, using the clock input signal, universal serial bus main equipment generates control sequential.
2. a kind of control system based on universal serial bus as described in claim 1, which is characterized in that the universal serial bus master sets
Standby to generate the first interrupt request singal, the serial bus slave generates the second interrupt request singal.
3. a kind of control system based on universal serial bus as described in claim 1, which is characterized in that the universal serial bus master sets
Standby to include idle mode, main sending mode and main reception pattern, the serial bus slave includes idle mode, from receiving mould
Formula and from sending mode.
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| CN109710556B (en) * | 2018-12-10 | 2020-08-11 | 北京集创北方科技股份有限公司 | Slave device and method for serial communication |
| CN111858436B (en) * | 2020-07-30 | 2021-10-26 | 南京英锐创电子科技有限公司 | Switching circuit for high-speed bus read-write low-speed bus and data read-write equipment |
| CN114691580B (en) * | 2020-12-28 | 2024-07-12 | 格科微电子（上海）有限公司 | Integrated circuit, digital circuit module, chip, camera and electronic information device |
| CN112711558B (en) | 2021-01-15 | 2023-07-21 | 飞腾信息技术有限公司 | Serial interrupt system, method and medium of LPC bus |
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