CN212135417U

CN212135417U - Device and single board for configuring slave equipment address

Info

Publication number: CN212135417U
Application number: CN202020668557.3U
Authority: CN
Inventors: 孟庆振; 邓文博
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2020-04-27
Filing date: 2020-04-27
Publication date: 2020-12-11
Anticipated expiration: 2030-04-27

Abstract

The utility model provides a device and veneer of configuration slave unit address includes main equipment and a plurality of slot on the veneer, the slot is used for main equipment is connected with the slave unit, every draw forth the PIN of a plurality of quantities on the slot, PIN configures respectively to high level or low level. Through directly setting up different high-low level combinations on the integrated circuit board of installation communication master, even there is the slave unit of the same model to insert same master after, also can not have the same I2C address, avoid the problem of slave unit address conflict, simultaneously through the mode of pull-down resistance in master's board card end setting, form different level combinations, simple easy realization has enlarged the applicable scene of this scheme.

Description

Device and single board for configuring slave equipment address

Technical Field

The utility model belongs to the technical field of the communication technology and specifically relates to a device and veneer of configuration slave unit address.

Background

The I2C bus is a bidirectional two-wire synchronous serial bus that only requires one data bus SDA and one clock bus SCL to transfer information between master and slave devices attached to the bus. According to the bus protocol, whether the master device sends or receives data from the slave device, the slave device needs to be addressed first, and when the slave device address matches the address required by the master device, the data transmission is started. Usually, there is only one master device on a set of I2C buses to enable the buses to transfer data and generate clocks, but often multiple slave devices are hooked up on a set of buses, with different slave devices defining different device addresses. When the slave devices hung on the same I2C bus have the same I2C address, an address conflict will occur, and data transmission on the bus cannot be performed.

In a group of I2C buses, a master chip is often hooked with a plurality of slave chips with different addresses, in the design process of a circuit system, the eight-bit device address of the slave chip is often in a user semi-defined mode, that is, except for the lowest bit of a read/write flag bit R/W, a chip manufacturer solidifies the device address of the upper four bits in the chip when designing the chip, and the remaining three-bit address users can customize the chip according to requirements, and the common method is to pull up a specific address pin to a high level 1 or pull down to a ground 0 outside the chip to configure the three-bit address of the chip. For some board cards with simpler structures and functions, such as a power supply board, a Riser card and the like, an I2C link carried by the board cards is usually to extend one path of I2C to multiple paths through an I2C Switch chip such as PCA9548 and the like, so that the PCA9548 chip on the Riser card needs to be configured with an I2C address to connect each I2C device on the board. However, when a plurality of Riser cards of the same type are inserted into slots of the same server motherboard, the Riser cards may be inserted under the same I2C bus on the motherboard (I2C host devices on the server are BMC chips), that is, I2C in different slots of the motherboard are connected to the same BMC-I2C bus. As shown in fig. 1, models of the riser cards 0 to 1 are the same, and PCA9548 addresses on the riser cards of the same model are the same, and when the riser cards are directly connected to a motherboard, an I2C address conflict occurs.

SUMMERY OF THE UTILITY MODEL

The utility model provides a device and veneer of configuration slave unit address for when solving current same model slave unit and insert, easily produce the problem of I2C address conflict.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

the utility model discloses an aspect provides a veneer, including the master, still include a plurality of slots on the veneer, the slot is used for being connected of master and slave, every draw forth the PIN of a plurality of quantities on the slot, PIN configures respectively to high level or low level.

Further, the PIN is connected with a pull-up resistor which is configured to be at a high level; the PIN is connected with a pull-down resistor and is configured to be at a low level.

Further, the combination of high and low levels of the PIN in each of the slots is different.

The utility model discloses the second aspect provides a device of configuration slave unit address, include the veneer, equipment still includes from the equipment integrated circuit board, set up slave unit and signal conversion chip from the equipment integrated circuit board, the signal conversion chip is used for being connected of master unit slot and slave unit, draw forth PIN on the slot quantity with the signal conversion chip is treated to dispose PIN quantity the same to correspond the connection.

Further, the slave device is a riser card.

Further, the signal conversion chip is an I2C switch chip.

Furthermore, a male connector is further arranged on the slave device board card, and the male connectors are respectively connected with the signal converter and the slot.

Further, the main device is a BMC chip, the single board is the only effect of the embodiment provided in the content of the main board utility model, not all the effects of the utility model, and one of the above technical solutions has the following advantages or beneficial effects:

the utility model discloses a directly set up different high-low level combinations on the integrated circuit board of installation communication master, even have the slave unit of the same model to insert same master after, also can not have the same I2C address, avoid the problem of slave unit address conflict, hold the mode that sets up pull-down resistance through the master board simultaneously, form different level combinations, simple easy realization has enlarged the suitable scene of this scheme.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a prior art master-slave device connection;

FIG. 2 is a schematic structural diagram of an embodiment 1 of the device of the present invention;

fig. 3 is a schematic structural diagram of an embodiment 2 of the device of the present invention.

Detailed Description

In order to clearly illustrate the technical features of the present invention, the present invention is explained in detail by the following embodiments in combination with the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily limit the invention.

The utility model discloses a veneer, including master equipment and a plurality of slot, the slot is used for being connected of master equipment and slave unit, every draw forth the PIN of a plurality of quantities on the slot, PIN configures respectively to high level or low level. When the PIN is connected with a pull-up resistor, the high-level switch is configured to be at a high level; when the PIN is connected with the pull-down resistor, the configuration is low. The high and low level combinations of the PIN in each slot are different, thus forming a plurality of different I2C addresses.

Based on the above single board, the utility model provides a device for configuring slave device address. The equipment further comprises a slave equipment board card, the slave equipment board card is provided with slave equipment and a signal conversion chip, the signal conversion chip is used for connecting the master equipment slot and the slave equipment, and the number of PIN led out from the slot is the same as the number of PIN to be configured of the signal conversion chip and is correspondingly connected with the signal conversion chip.

As shown in fig. 2, the board is used for communication between the master BMC chip 111 and the slave device on the motherboard 101. In fig. 2, 102, 103 and 104 are same type of Riser cards, on which a PCA9548/PCA9546 signal conversion chip is generally mounted, and the main function of the PCA9548 is to spread a single I2C signal from a main board BMC chip to multiple circuits and connect to each slave device on the Riser card, and the same type of Riser card has the same defined I2C address of the PCA 9548.

In the figures, 108, 109 and 110 are male connectors on the Riser card, and 105, 106 and 107 are slots on the motherboard, usually PCIe slots or GenZ slots, through which the motherboard and the Riser card are plugged and signal transmission is realized.

In the figure, 113 is an I2C bus link, in which a BMC chip on a motherboard is a master device, and a PCA9548 chip on each Riser card and other chips mounted under the PCA9548 are slave devices. The upper four bits of the address of the chip I2C of the PCA9548 are in internal fixed configuration, and configurable lower three-bit addresses A2, A1 and A0 are led out from the chip PIN and then are respectively connected to the

male connector

108, 109 and 110, and special PINs of A2, A1 and A0 are reserved on the male connector.

In the figure, 112 is a pull-up resistor on a motherboard, connections of addresses PIN a2, a1 and a0 corresponding to a male connector are reserved in a slot position of the motherboard, an I2C address of PCA9548 on a Riser card is defined by the pull-up resistor at a motherboard end, wherein the address of the pull-up to the high level is defined as "1", the address of the pull-down to the ground is defined as "0", and in order to avoid address conflict, the pull-up and the pull-down of each slot position on the motherboard are ensured to be different.

The PCA9548 definition address of the Riser inserted in the slot position is predefined on the mainboard slot position through the form of the PIN pull-up resistor and the PIN pull-down resistor, so that the problem that address conflict does not occur even if the Riser cards of the same type are inserted in the same I2C bus under the mainboard BMC is solved, and the design flexibility is enhanced.

As shown in fig. 3, two Riser cards of the same type are inserted into the same I2C bus of the motherboard BMC for illustration. In the figure, the whole 201 is a server mainboard on which a BMC chip 204 is mounted; 202 and 203 are two Riser cards with the same model, and the two Riser cards are respectively inserted into the slot positions 207 and 208 of the mainboard through

PCIe connectors

205 and 206; 210 is an I2C bus of a Riser card connected to a mainboard, PCA9548 chips of two Riser cards of the same model are hung on the same BMC-I2C bus, the upper four bits of an I2C address of the PCA9548 chip are in internal fixed configuration, which is defined as 1110, configurable lower three-bit addresses A2, A1 and A0 are led out from the chip PIN and are respectively connected to

PCIe connectors

205 and 206, and special PINs of A2, A1 and A0 are reserved on the PCIe connectors, wiring of the A2, A1 and A0 address PINs corresponding to the PCIe connectors is reserved in a slot of the mainboard, the end of the mainboard defines an I2C address of the PCA9548 on the Riser card through a pull-up resistor 209 and the like, wherein the pull-up high level address is defined as '1', the pull-down address is defined as '0', and the PCA 9548I 2C address of the Riser card 0 is defined as a '000', and the PCA 9584 of the Riser card is defined as a 9584 '100'. When the number of PCIe slots on the mainboard is increased, the I2C address of the PCA9548 chip can be expanded according to the method, but the pull-down combination of each slot on the mainboard is ensured to be different, so that I2C address conflict is avoided.

Although the present invention has been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without inventive work are still within the scope of the present invention.

Claims

1. A device for configuring slave device address comprises a single board, wherein the single board comprises a master device and a plurality of slots, the slots are used for connecting the master device and the slave device, a plurality of PIN are led out from each slot, and the PIN is respectively configured to be high level or low level; the equipment is characterized by further comprising a slave equipment board card, wherein the slave equipment board card is provided with slave equipment and a signal conversion chip, the signal conversion chip is used for connecting a master equipment slot and the slave equipment, and the number of PIN led out from the slot is the same as the number of PIN to be configured of the signal conversion chip and is correspondingly connected with the PIN.

2. The apparatus of claim 1, wherein the slave device is a riser card.

3. The apparatus of claim 2, wherein the signal conversion chip is an I2C switch chip.

4. The apparatus for configuring slave device address according to any one of claims 1-3, wherein a male connector is further provided on the slave device board, and the male connector is connected to the signal conversion chip and the slot respectively.

5. The apparatus of claim 4, wherein the master device is a BMC chip, and the board is a motherboard.