CN102902647B - Be arranged on I2C from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB) - Google Patents
Be arranged on I2C from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB) Download PDFInfo
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Abstract
The invention provides a kind of I2C that is arranged on from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB).This asic chip comprises at least two functional modules, the Slave I2C control module identical with the number of functional module and a memory module; Wherein, functional module connects with corresponding Slave I2C control module; Slave I2C control module is connected with Master I2C control module by I2C bus, and Slave I2C control module is also connected with memory module.The asic chip that the embodiment of the present invention provides has the function of multiple I2C chip, does not need to improve Master I2C control module namely to conduct interviews to described AISC chip.
Description
Technical field
The embodiment of the present invention relates to electronic technology, particularly relates to a kind of I2C that is arranged on from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB).
Background technology
Inter-integrated circuit (English full name is Inter-Integrated Circuit, referred to as I2C) is a kind of twin wire universal serial bus, for connecting microcontroller and peripherals thereof, is a kind of bus standard that microelectronics Control on Communication field extensively adopts.According to the I2C agreement of standard, each I2C equipment has a unique I2C address for accessing this equipment.Main frame is by other I2C equipment of this Address Recognition.Above-mentioned main frame refers to the equipment of initialization I2C bus, and other are called from machine by the I2C equipment of host addressing.
The I2C control module of main frame is commonly called Master I2C control module, is commonly called Slave I2C control module from the I2C control module of machine.When having multiple SlaveI2C control module from the printed circuit board (PCB) of machine, Master I2C module is by I2C address access Slave I2C control module.Master I2C control module can be CPU (central processing unit) (English full name is Center ProcessorUnit, referred to as CPU), also can be other logic processing device.
In order to an application-specific IC, (English full name is Application SpecificIntegrated Circuit, referred to as ASIC) chip substitutes multiple I2C chip, can will comprise the module integration of these I2C chip functions on an asic chip.But, because an I2C chip only has an I2C address, asic chip also only has an I2C address, therefore needs to improve the software of Master I2C control module, makes Master I2C control module can access multiple disparate modules integrated on asic chip.Which increase software upgrading maintenance cost, thus add the cost and complexity that use asic chip.
Summary of the invention
The embodiment of the present invention provides a kind of I2C that is arranged on from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB), can when not needing to improve Master I2C module software, identify and be integrated in I2C from the different I 2C control module in the asic chip machine printed circuit board (PCB), reduce the cost and complexity that use asic chip.
A first aspect of the present invention provides a kind of and is arranged on the asic chip of I2C from machine printed circuit board (PCB), and this asic chip comprises: at least two functional modules, the SlaveI2C control module identical with the number of described functional module and memory modules; Wherein, described functional module connects with corresponding Slave I2C control module; Described Slave I2C control module is connected with Master I2C control module by I2C bus, and described Slave I2C control module is also connected with described memory module.
In a first aspect of the present invention, the first possible being embodied as: described Slave I2C control module is for receiving the I2C address of Master I2C control module broadcast, the I2C address of described Master I2C control module broadcast is mated with the I2C address of described Slave I2C control module, if determine that described Slave I2C control module is the access object of Master I2C control module, described Slave I2C control module is further used for carrying out information interaction with described Master I2C control module.
In a first aspect of the present invention, or, during the first of first aspect present invention may realize, possible being embodied as of the second: described asic chip also comprises one or more Schema control line, for gating signal is transferred to described asic chip, with the I2C address making the Slave I2C control module received in the described asic chip of described gating signal receive the transmission of described Master I2C control module.
A second aspect of the present invention provides a kind of I2C from the printed circuit board (PCB) of machine, comprise at least one asic chip, wherein, the first having at least one to be a first aspect of the present invention or first aspect present invention may realize, or may realize in second of first party aspect of the present invention, or the first of first aspect present invention may realize in the second may realize describe asic chip.
The asic chip that the present embodiment provides is integrated with at least two functional modules, each functional module is connected with different Slave I2C control modules, therefore Master I2C control module can access the inner different Slave I2C control module of asic chip by different I2C addresses, and then accesses different functional modules by different SlaveI2C control modules.Therefore, do not need to improve Master I2C control module, reduce use cost and the complexity of asic chip.
Accompanying drawing explanation
A kind of asic chip structural representation that Fig. 1 provides for the embodiment of the present invention;
A kind of printed circuit board arrangement schematic diagram that Fig. 2 provides for the embodiment of the present invention;
The another kind of printed circuit board arrangement schematic diagram that Fig. 3 provides for the embodiment of the present invention.
Embodiment
What Fig. 1 provided for the embodiment of the present invention is a kind ofly arranged on the asic chip structural representation of I2C from machine printed circuit board (PCB).The asic chip of I2C bus that what the present embodiment provided have comprises at least two functional modules, the Slave I2C control module identical with the number of above-mentioned functions module and a memory module.
As shown in Figure 1, asic chip comprises N number of Slave I2C control module and N number of functional module, wherein, N be greater than 1 natural number.Functional module 21, functional module 22 ..., functional module 2N is respectively the functional module in the mutually different N number of I2C chip of function.Slave I2C control module 11, Slave I2C control module 12 ..., Slave I2C control module 1N is respectively the Slave I2C control module in above-mentioned N number of I2C chip.
Each functional module connects a Slave I2C control module respectively, and different functional modules is controlled by different Slave I2C control modules.As shown in Figure 1, functional module 21 is controlled by Slave I2C control module 11, and functional module 22 is controlled by Slave I2C control module 12, and by that analogy, functional module 2N is controlled by Slave I2C control module 1N.
Slave I2C control module is connected with Master I2C control module by I2C bus.Slave I2C control module is also connected with memory module.Memory module comprises the specific store module of each Slave I2C control module access.As shown in Figure 1, memory module 31 comprises the specific store module of Slave I2C control module 11 access, the specific store module of Slave I2C control module 12 access ..., the specific store module that Slave I2C control module 1N accesses.Exemplary, in an embodiment of the present invention, above-mentioned memory module can be a Parasites Fauna of multiple register composition, also can refer to a register.
Slave I2C control module controls functional module, stores data in the specific store module be connected with this Slave I2C control module in memory module, is also controlled functional module by these data.
Master I2C control module broadcasts the I2C address of the Slave I2C control module that will access to each Slave I2C control module of this asic chip.The I2C address of broadcast is mated with the I2C address of oneself by each Slave I2C control module in this asic chip, if determine it oneself is the access object of MasterI2C control module, then carry out information interaction with Master I2C control module, thus Master I2C control module may have access to Slave I2C control modules different in asic chip.
Such as, Master I2C control module is to the Slave I2C control module broadcast I2C address in asic chip, after Slave I2C control module 11 or Slave I2C control module 12 receive, mate with the I2C address of oneself, determine whether oneself to be whether the access object of Master I2C control module.If destination address is the I2C address of Slave I2C control module 11 in the information of broadcast, Slave I2C control module 11 can carry out information interaction with Master I2C control module.Such as, can according to the instruction of MasterI2C control module, specific store module in access function module 11 and memory module, the data of acquisition are sent to Master I2C control module, thus realize the information interaction of Slave I2C control module in Master I2C control module and asic chip.
Alternatively, in such scheme, asic chip can also be arranged one or more Schema control line.When above-mentioned I2C comprises the chip of more than one ASIC from the printed circuit board (PCB) of machine, by Schema control line gating signal is transferred on an asic chip on described printed circuit board (PCB), the address information receiving Master I2C control module to make the Slave I2C control module received in the asic chip of gating signal and send.
Such as, the input end of P.e.c. on board supply connects pull-up resistor, and after printed circuit board (PCB) powers on, power supply is by pull-up resistor to Schema control line input high level signal, and this high level signal is gating signal.
The number of Schema control line can set according to actual needs.If the number of Schema control line is n, then n bar Schema control line at most can a gating 2n asic chip.Such as, if there are two Schema control lines, then can by adjustment low and high level signal, make these two Schema control lines can export at most 4 kinds of signals (00,01,10,11), therefore, these two Schema control lines at most can gating 4 chips.
The asic chip that the present embodiment provides is integrated with at least two functional modules, each functional module is connected with different Slave I2C control modules, therefore Master I2C control module can access the inner different Slave I2C control module of asic chip by different I2C addresses, and then accesses different functional modules by different SlaveI2C control modules.Therefore, do not need to improve Master I2C control module, reduce use cost and the complexity of asic chip.
A kind of I2C that the embodiment of the present invention also provides is from the printed circuit board (PCB) of machine, and this printed circuit board (PCB) comprises at least one asic chip.An asic chip is had at least for the asic chip shown in Fig. 1 in described asic chip.
For ease of illustrating, the printed circuit board (PCB) shown in Fig. 2 comprises asic chip 41 and asic chip 42.Wherein, asic chip 41 is the asic chip shown in Fig. 1, and asic chip 42 comprises a functional module, a Slave I2C control module and a memory module.
As shown in Figure 2, described I2C also comprises Schema control line from the printed circuit board (PCB) of machine, for gating signal being transferred to asic chip 41 or asic chip 42, Slave I2C control module in asic chip 41 or asic chip 42 is made to receive the address information of Master I2C control module broadcast.
For a more detailed description of the embodiment of the present invention, for the printed circuit board (PCB) shown in Fig. 3, be further detailed.
Printed circuit board (PCB) shown in Fig. 3 comprises four asic chips: asic chip 51, asic chip 52, asic chip 53 and asic chip 54.Wherein, asic chip 51, asic chip 52, asic chip 53 inside comprise a functional module respectively, a Slave I2C control module and a memory module, and asic chip 54 is the asic chip shown in Fig. 1.
On asic chip 51, the I2C address of Slave I2C control module is 1001000, on asic chip 52, the I2C address of Slave I2C control module is 1001001, on asic chip 53, the I2C address of Slave I2C control module is 1001011, on asic chip 54, the I2C address of Slave I2C control module 543 is 1001010, and on asic chip 54, the I2C address of Slave I2C control module 544 is 0100000.Functional module 542 is controlled by Slave I2C control module 544, and functional module 541 is controlled by Slave I2C control module 543.
Be provided with two Schema control lines in Fig. 3, the mapping relations of the low and high level value of Schema control line and the asic chip of gating are as shown in table 1.
Table 1
On the printed circuit board (PCB) that the present embodiment provides, at least one asic chip is integrated with the not identical functional module of at least two functions, each functional module is connected with different Slave I2C control modules, therefore Master I2C control module can access the inner different Slave I2C control module of asic chip by different I2C addresses, and then accesses different functional modules by different Slave I2C control modules.Therefore, do not need to improve Master I2C control module, reduce use cost and the complexity of asic chip.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (4)
1. one kind is arranged on the application-specific IC asic chip of inter-integrated circuit I2C from machine printed circuit board (PCB), it is characterized in that, comprising: at least two different functional module, the different Slave I2C control module identical from the number of described functional module and memory modules; Wherein,
Each described functional module connects with corresponding Slave I2C control module, and each described functional module is controlled by the Slave I2C control module of described correspondence; Described Slave I2C control module is connected with Master I2C control module by I2C bus, and described Slave I2C control module is also connected with described memory module.
2. application-specific IC asic chip according to claim 1, is characterized in that,
Described Slave I2C control module is for receiving the I2C address of Master I2C control module broadcast, the I2C address of described Master I2C control module broadcast is mated with the I2C address of described Slave I2C control module, if determine that described Slave I2C control module is the access object of Master I2C control module, described Slave I2C control module is further used for carrying out information interaction with described Master I2C control module.
3. application-specific IC asic chip according to claim 1 and 2, it is characterized in that, described asic chip also comprises one or more Schema control line, for gating signal is transferred to described asic chip, with the I2C address making the Slave I2C control module received in the described asic chip of described gating signal receive the transmission of described Master I2C control module.
4. inter-integrated circuit I2C is from a printed circuit board (PCB) for machine, it is characterized in that, comprises at least one application-specific IC asic chip; Wherein, an asic chip according to any one of claim 1-3 is had in described asic chip at least.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210361085.7A CN102902647B (en) | 2012-09-25 | 2012-09-25 | Be arranged on I2C from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210361085.7A CN102902647B (en) | 2012-09-25 | 2012-09-25 | Be arranged on I2C from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB) |
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| CN102902647A CN102902647A (en) | 2013-01-30 |
| CN102902647B true CN102902647B (en) | 2015-09-30 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE102015214133A1 (en) * | 2015-07-27 | 2017-02-02 | Continental Automotive Gmbh | Integrated circuit for operating on a bus and method for operating the integrated circuit |
| CN110046120B (en) * | 2019-04-12 | 2022-02-18 | 苏州浪潮智能科技有限公司 | Data processing method, device and system based on IIC protocol and storage medium |
Citations (3)
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|---|---|---|---|---|
| EP1494125A1 (en) * | 2003-07-03 | 2005-01-05 | Thomson Licensing S.A. | Method and data structure for random access via a bus connection |
| CN102023953A (en) * | 2009-09-17 | 2011-04-20 | 研祥智能科技股份有限公司 | Control method of system having many inter-integrated circuit (I2C) buses |
| CN102231839A (en) * | 2011-05-24 | 2011-11-02 | 深圳市掌网立体时代视讯技术有限公司 | Inter-integrated circuit (I2C) control device and method for double sensors |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1494125A1 (en) * | 2003-07-03 | 2005-01-05 | Thomson Licensing S.A. | Method and data structure for random access via a bus connection |
| CN102023953A (en) * | 2009-09-17 | 2011-04-20 | 研祥智能科技股份有限公司 | Control method of system having many inter-integrated circuit (I2C) buses |
| CN102231839A (en) * | 2011-05-24 | 2011-11-02 | 深圳市掌网立体时代视讯技术有限公司 | Inter-integrated circuit (I2C) control device and method for double sensors |
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Effective date of registration: 20191220 Address after: No.1, floor 3, No.319, zhanggongshan Road, Yuhui District, Bengbu City, Anhui Province Patentee after: Bengbu guijiu Intellectual Property Service Co., Ltd Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: Huawei Technologies Co., Ltd. |
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Effective date of registration: 20201021 Address after: 226000 south of Zhongxiu East Road West of Jinshan Road, high tech Zone, Nantong City, Jiangsu Province Patentee after: Nantong Tenglong Communication Technology Co.,Ltd. Address before: No.1, floor 3, No.319, zhanggongshan Road, Yuhui District, Bengbu City, Anhui Province Patentee before: Bengbu guijiu Intellectual Property Service Co.,Ltd. |