CN207503207U - For the integrated test system of multiplex roles - Google Patents
For the integrated test system of multiplex roles Download PDFInfo
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- CN207503207U CN207503207U CN201720944728.9U CN201720944728U CN207503207U CN 207503207 U CN207503207 U CN 207503207U CN 201720944728 U CN201720944728 U CN 201720944728U CN 207503207 U CN207503207 U CN 207503207U
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- multiplex roles
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- 238000012360 testing method Methods 0.000 title claims abstract description 23
- 230000005540 biological transmission Effects 0.000 claims abstract description 18
- 239000013307 optical fiber Substances 0.000 claims abstract description 10
- 230000006870 function Effects 0.000 description 17
- 238000013461 design Methods 0.000 description 13
- 230000002093 peripheral effect Effects 0.000 description 10
- 238000012546 transfer Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 4
- 239000008358 core component Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000001568 sexual effect Effects 0.000 description 2
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Abstract
The utility model discloses the integrated test systems that the utility model is used for multiplex roles, for the integrated test system of multiplex roles, including being provided with power module, pci expansion slot, PCI function cards and mainboard module on rear panel module, rear panel module is carried out data transmission with PC machine by NGA/DVI, several PCI e are provided in pci expansion slot and carry card, PCI e load cards are internally provided with FMC expansion interfaces and are connect with external module.The external module includes LVDS high-speed interfaces submodule, digital audio interface submodule, optical fiber interface submodule, expansion module, the high-speed interface submodule, optical fiber interface submodule are carried out data transmission by PCIE high-speed buses, and digital audio interface submodule receives PCI e and carries the data progress audio output that card is sent.
Description
Technical field
The utility model is related to a kind of test systems, and in particular to for the integrated test system of multiplex roles.
Background technology
The interface used in many test systems now can only all meet single function.And efficiency of transmission is slow, often
It influences each other between normal modules, the efficiency for transmitting data is low, and test is slow, and then influences working efficiency, is adopted in industrial personal computer
It transmits the bus mismatch of data to interface, and mutually first stream is relatively difficult between data.
The integrated test system for multiplex roles that the utility model uses has the function of to test multiple interfaces, meet
In the case of minimum interface and quantity, it is desirable that the interface of the equipment is also equipped with certain scalability, in case increasing follow-up
Function.By the analysis to demand, the interface function that equipment needs are tested has the characteristics of type is more, and quantity is more, while certain
The index request of a little interfaces is of little use, in the case where meeting above-mentioned function and interface requirements, it is also necessary to have certain interface
Scalability.
Detailed comparisons and demonstration by kinds of schemes propose to use general industrial personal computer, are internally integrated multiple types and connect
The board of mouth, while member-retaining portion general-purpose interface is for the scheme of extension.Wherein board uses two kinds of card insert types of PCI-E and PCI
Board solution.
Utility model content
Technical problem to be solved in the utility model is current integrated test system, and transmission signal is single, between data
Difficult interface, and the scalability of many systems is poor, and the utility model aim is to provide the integration test for multiplex roles
System solves the problem above-mentioned.
The utility model is achieved through the following technical solutions：
For the integrated test system of multiplex roles, including being provided with power module, pci expansion slot, PCI work(on rear panel module
It can block and mainboard module, rear panel module are carried out data transmission with host computer by NGA/DVI, be provided in pci expansion slot several
A PCI-e carries card, and PCI-e load cards are internally provided with FMC expansion interfaces and are connect with external module.
Further, the external module connects including LVDS high-speed interfaces submodule, digital audio interface submodule, optical fiber
Openning module, expansion module, the high-speed interface submodule, optical fiber interface submodule carry out data biography by PCIE high-speed buses
Defeated, digital audio interface submodule receives PCI-e and carries the data progress audio output that card is sent.
Further, the PCI-e carries card and further includes memory modules, flash memory module, FPGA module, the memory modules and
Flash memory module is connect with FPGA module, and FPGA module is expanded by LVDS high speed ports, serdes high speed ports, I/O high speed ports and FMC
Exhibition interface carries out data transmission, and FPGA module also sends data to mainboard module.
Further, the pci expansion slot of the rear panel module setting is at least 2.
Further, the PCI function cards of the rear panel module setting are at least 2.
The PCI-e that the utility model uses carries card mainly by FPGA as core processor, is used with host computer
PCIE2.0x8 interfaces, data transfer bandwidth theoretical value be up to 40Gbps, and FPGA external harmoniousness DDR3 caches, externally
Using FMC connectors, three kinds of signals have been drawn from FPGA：
1st, LVDS high-speed differential signals, can external common LVDS signals peripheral hardware, multigroup LVDS signals can combine
Carry out transmitting data in parallel, significantly increase data transfer bandwidth.
2nd, serdes high-speed differential signals, the signal are from the signal of the GTP mouths extraction of FPGA, can be connect customized
Serdes signal peripheral hardwares, can do RapidIO buses, connect RapidIO bus peripheral hardwares, can also do SGMII high-speed interfaces and
Other serdes signal peripheral hardwares.
3rd, IO parallel signals can be used as common IO to control signal, can also form parallel signal and carry out data transmission,
It can also be used as the common bus such as SPI, I2C, UART such as and connect corresponding peripheral hardware.The I/O port of FPGA is a kind of flexibly to connect very much
Mouthful.
PCI-e carries card since the high speed ports such as LVDS have been drawn in front end, and rear end is again using PCIE high-speed buses, the load card
The interfaces such as high speed data transfer, therefore LVDS, optical fiber are very suitable for mainly to integrate using the load card.
The utility model uses PICMG frameworks, is internally integrated the backboard and mainboard of PICMG1.3, chooses the framework mode,
Reason of both mainly having：1st, the functional interface to be realized of this equipment itself is more, and PCIE or PCI more than comparison is needed to connect
Mouthful integrate the board of different function and interface；2nd, it is more flexible in view of autgmentability, if only consider to design a kind of PCIE or
Or the card of person PCI is limited to interface quantity or is limited to function, for example only designs the card of PCI, then conveyor is limited to
Width, can not be by the real-time data transmission more than several Gbps, and interface quantity is generally insufficient if the only card of design PCI-e, because
There are an x1, x4, x8 for PCI-e, tetra- kinds of interfaces of x16, wherein only PCIE x16 are compatible with 4 kinds of protocol interfaces, but x16 Universal joints
The higher industrial control mainboard of sexual valence be usually no more than two, it is considerably less, be unfavorable for extending, and only PCIE x1 are compatible with 4 kinds of objects
Interface is managed, but x1 bandwidth is insufficient, unlike PCI advantageously.
PCI carries card and is mainly used for the relatively low function subcard of integrated rate, which is also mainly as data using FPGA
The core component exchanged with interface is handled, front end is also to have drawn LVDS signals and I/O signal using FMC, and rear end is integrated with
PCI bridge chips, design as core architecture.Front terminal module is shown, can be integrated on the subcard.
It develops PCI and carries card, the insufficient situation in expansion slot position can either be alleviated, while Ben Kanei increases PCI Bridge, the bridge core
Piece has certain processing capacity, the function control of processing and data forwarding and submodule for data, and software development rises
Coming all can be more flexible and conveniently.
The utility model compared with prior art, has the following advantages and advantages：
1st, the utility model is used for the integrated test system of multiplex roles, and transmission signal is various, can carry out different signals
Transmission；
2nd, the utility model is used for the integrated test system of multiplex roles, is set on rear panel module there are many expansion interface, expanded
Malleability can be strong；
3rd, the utility model is used for the integrated test system of multiplex roles, is used uniformly PCIE buses, data exchange facilitates fast
Speed.
Description of the drawings
Attached drawing described herein is used for providing further understanding the utility model embodiment, forms the one of the application
Part does not form the restriction to the utility model embodiment.In the accompanying drawings：
Fig. 1 is Tthe utility model system block diagram.
Fig. 2 carries card and interface sub-module functional block diagram for the utility model PCI-e.
Specific embodiment
For the purpose of this utility model, technical solution and advantage is more clearly understood, with reference to embodiment and attached drawing,
The utility model is described in further detail, and the exemplary embodiment and its explanation of the utility model are only used for explaining this
Utility model is not intended to limit the scope of the present invention.
Embodiment
As shown in Figure 1, 2, the utility model is used for the integrated test system of multiplex roles, for the integration test system of multiplex roles
System, including being provided with power module, pci expansion slot, PCI function cards and mainboard module, rear panel module and PC machine on rear panel module
Carried out data transmission by NGA/DVI, several PCI-e are provided in pci expansion slot and carry card, PCI-e carries card and is internally provided with
FMC expansion interfaces are connect with external module.The external module includes LVDS high-speed interfaces submodule, digital audio interface submodule
Block, optical fiber interface submodule, expansion module, the high-speed interface submodule, optical fiber interface submodule pass through PCIE high-speed buses
Carry out data transmission, digital audio interface submodule receives PCI-e and carries the data progress audio output that card is sent.The PCI-e
It carrying card and further includes memory modules, flash memory module, FPGA module, the memory modules and flash memory module are connect with FPGA module,
FPGA module is carried out data transmission by LVDS high speed ports, serdes high speed ports, I/O high speed ports and FMC expansion interfaces, FPGA
Module also sends data to mainboard module.The pci expansion slot of the rear panel module setting is at least 2.The rear panel module
The PCI function cards of setting are at least 2.
The PCI-e that the utility model uses carries card mainly by FPGA as core processor, is used with host computer
PCIE2.0x8 interfaces, data transfer bandwidth theoretical value be up to 40Gbps, and FPGA external harmoniousness DDR3 caches, externally
Using FMC connectors, three kinds of signals have been drawn from FPGA：LVDS high-speed differential signals, being capable of external common LVDS signals
Peripheral hardware, multigroup LVDS signals can combine transmitting data in parallel, significantly increase data transfer bandwidth.Serdes high
Speed difference sub-signal, the signal are from the signal of the GTP mouths of FPGA extraction, can connect customized serdes signals peripheral hardware, can be with
RapidIO buses are done, connect RapidIO bus peripheral hardwares, SGMII high-speed interfaces and other serdes signal peripheral hardwares can also be done.
IO parallel signals can be used as common IO to control signal, can also form parallel signal and carry out data transmission, can also be used as
As the common bus such as SPI, I2C, UART connects corresponding peripheral hardware.The I/O port of FPGA is a kind of very flexible interface.
PCI-e carries card since the high speed ports such as LVDS have been drawn in front end, and rear end is again using PCIE high-speed buses, the load card
The interfaces such as high speed data transfer, therefore LVDS, optical fiber are very suitable for mainly to integrate using the load card.
This system just can not possibly can integrate all functions since interface is more with one or two card, and must design
The multiple boards of multiple interfaces realize all functions, and the mode that our company considers is that two kinds of design carries card, a kind of is PCI-e
Card is carried, another is that PCI carries card, then all interfaces are designed as to the solution of subcard.Two kinds of design carries card not
Only facilitate the extension between different interface subcards, and be more advantageous to the Function Extension in user's future, user needs in future
It when increasing certain interfaces, does not need to redesign entire function, it is only necessary to design an interface card, be integrated into PCI-e or PCI
Load card on can be realized as, the development time can greatly be shortened in this way, while can be that user saves a large amount of funds.
The utility model uses PICMG frameworks, is internally integrated the backboard and mainboard of PICMG1.3, chooses the framework mode,
Reason of both mainly having：1st, the functional interface to be realized of this equipment itself is more, and PCIE or PCI more than comparison is needed to connect
Mouthful integrate the board of different function and interface；2nd, it is more flexible in view of autgmentability, if only consider to design a kind of PCIE or
Or the card of person PCI is limited to interface quantity or is limited to function, for example only designs the card of PCI, then conveyor is limited to
Width, can not be by the real-time data transmission more than several Gbps, and interface quantity is generally insufficient if the only card of design PCI-e, because
There are an x1, x4, x8 for PCI-e, tetra- kinds of interfaces of x16, wherein only PCIE x16 are compatible with 4 kinds of protocol interfaces, but x16 Universal joints
The higher industrial control mainboard of sexual valence be usually no more than two, it is considerably less, be unfavorable for extending, and only PCIE x1 are compatible with 4 kinds of objects
Interface is managed, but x1 bandwidth is insufficient, unlike PCI advantageously.
PCI carries card and is mainly used for the relatively low function subcard of integrated rate, which is also mainly as data using FPGA
The core component exchanged with interface is handled, front end is also to have drawn LVDS signals and I/O signal using FMC, and rear end is integrated with
PCI bridge chips, design as core architecture.Front terminal module can be integrated on the subcard.
It develops PCI and carries card, the insufficient situation in expansion slot position can either be alleviated, while Ben Kanei increases PCI Bridge, the bridge core
Piece has certain processing capacity, the function control of processing and data forwarding and submodule for data, and software development rises
Coming all can be more flexible and conveniently.
Above two carries the design of card plus subcard, and most subcard can both select PCI-e to carry card to integrate, can also
PCI is selected to carry, and card is integrated, subject to the space that the quantity of integrated card can be accommodated according to interface connector.Therefore, it either selects
The integrated card of PCI-e or the integrated card of PCI, it is final to need to be considered according to the number of slots amount of PICMG backboards.
Above-described specific embodiment, the purpose of this utility model, technical solution and advantageous effect have been carried out into
One step is described in detail, it should be understood that the foregoing is merely specific embodiment of the present utility model, is not used to limit
Determine the scope of protection of the utility model, within the spirit and principle of the utility model, any modification for being made equally is replaced
It changes, improve, should be included within the scope of protection of this utility model.
Claims (5)
1. for the integrated test system of multiplex roles, which is characterized in that including being provided with power module on rear panel module, PCI expands
Slot, PCI function cards and mainboard module are opened up, rear panel module is carried out data transmission with host computer by NGA/DVI, in pci expansion slot
It is provided with several PCI-e and carries card, PCI-e load cards are internally provided with FMC expansion interfaces and are connect with external module.
2. the integrated test system according to claim 1 for multiplex roles, which is characterized in that the external module includes
LVDS high-speed interfaces submodule, digital audio interface submodule, optical fiber interface submodule, expansion module, high-speed interface
Module, optical fiber interface submodule are carried out data transmission by PCIE high-speed buses, and digital audio interface submodule receives PCI-e and carries
The data that card is sent carry out audio output.
3. the integrated test system according to claim 1 for multiplex roles, which is characterized in that the PCI-e carries card also
Including memory modules, flash memory module, FPGA module, the memory modules and flash memory module are connect with FPGA module, FPGA module
Carried out data transmission by LVDS high speed ports, serdes high speed ports, I/O high speed ports and FMC expansion interfaces, FPGA module is also by number
According to being sent to mainboard module.
4. the integrated test system according to claim 1 for multiplex roles, which is characterized in that the rear panel module setting
Pci expansion slot be at least 2.
5. the integrated test system according to claim 1 for multiplex roles, which is characterized in that the rear panel module setting
PCI function cards be at least 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720944728.9U CN207503207U (en) | 2017-07-31 | 2017-07-31 | For the integrated test system of multiplex roles |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720944728.9U CN207503207U (en) | 2017-07-31 | 2017-07-31 | For the integrated test system of multiplex roles |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207503207U true CN207503207U (en) | 2018-06-15 |
Family
ID=62496088
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720944728.9U Expired - Fee Related CN207503207U (en) | 2017-07-31 | 2017-07-31 | For the integrated test system of multiplex roles |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207503207U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107480085A (en) * | 2017-07-31 | 2017-12-15 | 成都普诺科技有限公司 | Multiplex roles integrated test system |
| CN108989000A (en) * | 2018-08-13 | 2018-12-11 | 苏州联讯仪器有限公司 | A kind of novel hand-held PAM4 Error Detector |
-
2017
- 2017-07-31 CN CN201720944728.9U patent/CN207503207U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107480085A (en) * | 2017-07-31 | 2017-12-15 | 成都普诺科技有限公司 | Multiplex roles integrated test system |
| CN108989000A (en) * | 2018-08-13 | 2018-12-11 | 苏州联讯仪器有限公司 | A kind of novel hand-held PAM4 Error Detector |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180615 |
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| CF01 | Termination of patent right due to non-payment of annual fee |